CN114121865A - System-in-package structure and manufacturing method thereof - Google Patents
System-in-package structure and manufacturing method thereof Download PDFInfo
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- CN114121865A CN114121865A CN202111223302.1A CN202111223302A CN114121865A CN 114121865 A CN114121865 A CN 114121865A CN 202111223302 A CN202111223302 A CN 202111223302A CN 114121865 A CN114121865 A CN 114121865A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention discloses a system-level packaging structure, which comprises: at least one bare chip, a plurality of first bonding pads, at least one passive device, a conductive frame, a base island and a plastic encapsulation layer; the conductive frame is multiplexed into the passive device and the base island; the die is disposed on the base island, the first bonding pad is disposed on the die, and the die is electrically connected to the first bonding pad; the first bonding pad is electrically connected with the passive device; the encapsulation layer encapsulates the die, the first pad, the passive device, the conductive frame, and the base island. The system-in-package structure provided by the invention omits a packaging entity passive device from a chip, so that the production efficiency can be improved on one hand, and the miniaturization of the system-in-package structure can be realized on the other hand.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a system-in-package structure and a method for fabricating the same.
Background
With the development of the semiconductor industry, the overall volume of products such as consumer electronics, vehicle-mounted products, pen electronics and the like is developing towards miniaturization and multi-functionalization, and with the development trend of miniaturization, the size of a circuit board inside the product is also developing towards miniaturization, and important device chips and peripheral circuits on the circuit board are also required to be designed in a miniaturized and compact manner.
The system in package (sip) technology is a technology that a plurality of chips and passive devices are integrated in a package structure, so as to realize a substantially complete function. Compared with the traditional separate packaging structure of a single chip and a passive device, the system-in-package structure can realize smaller packaging volume and lower packaging cost.
In the existing packaging structure, for the miniaturization of the SIP package, in addition to packaging the bare chips of different chips together, peripheral components of the chips, such as resistance, capacitance, inductance and the like, can also be packaged together. Because passive devices such as a resistor, a capacitor, an inductor and the like have the volume and the size which are standard in the industry, the volume of the packaged SIP chip is inevitably increased, the miniaturization requirement of the SIP chip is not facilitated, if peripheral devices are not packaged together, the problems that the volume of the whole flexible circuit board is overlarge and the like are caused, the parasitic parameters of the whole circuit are increased, and the electrical performance is reduced.
Disclosure of Invention
To solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a system in package structure and a method for fabricating the same.
An embodiment of the present invention provides a system-in-package structure, including: at least one bare chip, a plurality of first bonding pads, a conductive frame and a plastic encapsulation layer; the conductive frame is multiplexed into a passive device and a base island; the die is disposed on the base island, the first bonding pad is disposed on the die, and the die is electrically connected to the first bonding pad; the first bonding pad is electrically connected with the passive device; the encapsulation layer encapsulates the die, the first pad, the passive device, the conductive frame, and the base island.
Preferably, the passive device is at least one of a resistive, inductive and capacitive element.
Preferably, a pin is included; the pins comprise a first pin and a second pin, the first pin is electrically connected with the passive device, and the second pin is used for connecting an external circuit.
Preferably, a conductive lead is included, and the first pad is electrically connected to the first pin and the second pin through the conductive lead.
Preferably, the thickness of the plastic sealing layer is 0.4mm-1.5 mm.
Preferably, the thickness of the conductive frame is 50um-300 um.
The embodiment of the invention also provides a manufacturing method of the system-level packaging structure, which comprises the following steps:
providing a carrier plate, and forming a metal layer on the carrier plate;
etching the metal layer to obtain a conductive frame, wherein at least part of the conductive frame is multiplexed into a passive device and a base island;
disposing at least one die on the base island;
providing a number of first bonding pads on the die, the die being electrically connected to the first bonding pads;
forming a molding layer embedding the die, the first bonding pad, the passive device, the conductive frame and the base island on the carrier board;
removing the carrier plate;
and cutting to form the system-in-package structure.
Preferably, the etching the metal layer to obtain a conductive frame, the conductive frame being at least partially multiplexed into a passive device and a base island, includes:
and etching the metal layer to obtain pins, wherein the pins comprise a first pin and a second pin, the first pin is electrically connected with the passive device, and the second pin is used for connecting an external circuit.
Preferably, before forming an encapsulating layer embedding the die, the first pad, the passive device, the conductive frame and the base island on the carrier board, the encapsulating layer comprises:
and arranging a conductive lead on the first bonding pad, wherein the first bonding pad is electrically connected with the first pin and the second pin through the conductive lead respectively.
Preferably, the forming a molding layer embedding the die, the first pad, the passive device, the conductive frame and the base island on the carrier board includes: exposing the second pin.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the embodiment of the invention, the conductive frame support frame is etched into different shapes by utilizing an etching technology so as to simulate the function of a related passive device and reuse the conductive frame as the passive device; therefore, the method can not only save the passive device of the packaging entity to the SIP chip, but also achieve the function of the passive device necessary for the circuit, greatly reduce the size of the whole SIP chip, and well solve the problem of SIP miniaturization on the basis of meeting the circuit performance requirement.
In the embodiment of the invention, the conductive frame is reused as the base island, so that a substrate for placing a bare chip can be omitted, the structure is simple, and the process flow can be simplified.
In addition, the method for manufacturing the system-in-package structure provided by the embodiment of the invention can realize that the conductive frame and the passive device and the base island are formed in the same process, so that the production efficiency can be improved, and the miniaturization of the system-in-package structure can be realized.
The manufacturing method of the system-in-package structure provided by the embodiment of the invention can form passive devices with different functions in the same process, has simple manufacturing process and can improve the production efficiency.
In the embodiment of the invention, the bare chip is arranged on the base island, the first bonding pad is arranged on the bare chip, and the bare chip is directly arranged on the base island, so that the whole manufacturing process is simple and easy to operate.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a top view of a system in package structure according to an embodiment of the invention;
FIG. 1a is a schematic cross-sectional view taken along line A-A' of FIG. 1;
fig. 2 is a top view of a system in package structure according to an embodiment of the invention;
fig. 3 is a top view of a system in package structure according to an embodiment of the invention;
fig. 4 is a process flow chart of a method for manufacturing a system in package structure according to an embodiment of the invention.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
Fig. 1 is a top view of a system in package structure according to an embodiment of the invention. FIG. 1a is a schematic cross-sectional view taken along line A-A' of FIG. 1.
Referring to fig. 1 and 1a, a system in package structure 1 includes: at least one bare chip 2, a plurality of first bonding pads 3, a conductive frame 5 and a plastic encapsulation layer 7; the conductive frame 5 is at least partially multiplexed into a passive device 4 and a base island 6; the die 2 is arranged on the base island 6, the first bonding pad 3 is arranged on the die 2, and the die 2 is electrically connected with the first bonding pad 3; the first bonding pad 3 is electrically connected with the passive device 4; the encapsulation layer 7 covers the die 2, the first bonding pad 3, the passive component 4, the conductive frame 5 and the base island 6. In the system-in-package structure, the conductive frame 5 mainly plays a role of supporting, the conductive frame 5 serves as a substrate, and electronic elements such as the bare chip 2 and the passive device 4 in the package structure 1 are all arranged on the conductive frame 5; the bare chip 2 is arranged in a forward mounting mode, specifically, the bare chip 2 is arranged on the base island 6, the first bonding pad 3 is arranged on the bare chip 2, and the bare chip 2 is electrically connected with the first bonding pad 3; the first bonding pad 3 is electrically connected with the passive device 4; thereby constituting a structure in which the die 2 is electrically connected to the passive device 4. And then the bare chip 2, the first bonding pad 3, the passive device 4, the conductive frame 5 and the base island 6 are coated by a plastic encapsulating layer 7, so that the whole chip is encapsulated.
In this embodiment, the conductive frame 5 is at least partially multiplexed into the passive device 4 and the base island 6, so that the function of packaging a solid passive device into an SIP chip can be omitted, the function of the passive device necessary for a circuit can be achieved, the size of the whole SIP chip is greatly reduced, and the problem of SIP miniaturization is well solved on the basis of meeting the performance requirement of the circuit.
In this embodiment, as shown in fig. 1 and 1a, the passive devices 4 and the base islands 6 are both part of the conductive frame 5. The number of the base islands 6 may be 1, 2, 3, etc., the shape of the base island 6 may be a polygonal or circular structure such as a square, a rectangle, etc., and 1 or more dies 2 may be disposed on one base island 6, specifically, may be disposed according to the requirement of the actual chip circuit design. The number of base islands and the number of bare chips arranged in one base island are not limited by the embodiment of the invention.
As shown in fig. 1 and 1a, the passive device 4 has one, and the passive device 4 is a capacitor element. In the embodiment of the present invention, the passive device 4 may include at least one of a resistive element, an inductive element and a capacitive element, and the passive device 4 is characterized by operating in the presence of a signal without applying a power source in the circuit. The inductance component is mainly an inductance component with a coil structure.
Referring to fig. 1 and 1a, in the present embodiment, the die 2 has one, and may be a power die, a memory die, a sensing die, or a radio frequency die, for example. The present embodiment does not limit the function of the die 2. In this embodiment, the number of the bare chips 2 may be 1, 2, 3, or the like. In the embodiment of the invention, the bare chip is positively arranged, so that the whole manufacturing process is simple and easy to operate because the bare chip can be directly placed on the base island.
Referring to fig. 1 and 1a, 2 first pads 3 are provided on a die 2. In some embodiments, the number of the first pads 3 may be, for example, 1, 2, 3, 4 or more, the number of the first pads 3 may be set according to the actual requirement of the circuit, and the invention does not limit the number of the first pads 3.
As shown in fig. 1 and fig. 1a, in this embodiment, the first pad 3 further includes a pin 8 and a conductive lead 9, and the pin 8 is electrically connected to the first pad through the conductive lead 9. The first bonding pad 3 is electrically connected with the passive device 4 through the conductive lead 9; the conductive lead 9 has a parabolic structure. The conductive frame 5 is at least partially multiplexed into pins 8; for example, the pin 8 may also use other conductive devices or conductive materials to implement electrical connection between electronic components in the package structure, and the embodiment of the present invention does not limit the structure and the material of the pin 8.
Above, only one implementation manner of the embodiment of the present invention is described, and as shown in fig. 2, fig. 2 is a further top view of the system-in-package structure provided by the embodiment of the present invention, a system-in-package structure 1 includes two dies 2, where one die 2 may be, for example, a power die, a memory die, a sensing die, or a radio frequency die, and the other die 2 may be, for example, a control chip for controlling the previous die 2. In an embodiment of the invention, the plurality of dies 2 may be, for example, dies that require electrical interconnection with other functions.
In some embodiments, the number of the base islands 6 may be 1, 2, 3, etc., the shape of the base islands 6 may be a polygonal or circular structure such as a square, a rectangle, etc., and 1 or more dies 2 may be disposed on one base island 6, which may be specifically disposed according to the requirement of the actual chip circuit design. The number of base islands and the number of bare chips arranged in one base island are not limited by the embodiment of the invention.
In some embodiments, as shown in fig. 2, the passive devices 4 include a capacitive element 4a and a resistive element 4b, i.e., the conductive frame 5 is multiplexed into two different functional passive devices to meet different circuit designs and circuit requirements within the chip. In this embodiment, the passive device 4 may include at least one of a resistor, an inductor, and a capacitor, for example, and the passive device 4 is characterized by operating in the presence of a signal without applying a power source in the circuit. The inductance component is mainly an inductance component with a coil structure. In this embodiment, electrically conductive frame 5 can multiplex simultaneously for passive device 4 of different functions, need not to encapsulate original passive device 4 inside the chip, simplifies the inner structure of chip, satisfies the inside circuit demand of chip simultaneously, can reach the miniaturized demand of SIP again.
The above is only one implementation manner of the embodiment of the present invention, and the implementation manner of the embodiment of the present invention may also be that the thickness of the plastic sealing layer 7 is 0.4mm to 1.5mm, and the design of the plastic sealing layer 7 with the thickness can ensure the stability and the firmness of the plastic sealing layer 7. The material of the encapsulating layer 7 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the plastic sealing layer 7 can also be various polymers or composite materials of resin and polymer.
The above is only one implementation manner of the embodiment of the present invention, and the implementation manner of the embodiment of the present invention may also be that the thickness of the conductive frame 5 is 50um to 300um, and the conductive frame 5 within the thickness range may not only play a good supporting role, but also meet the requirement of multiplexing into a passive device. The conductive frame 5 may be made of a metal having excellent conductivity, such as copper.
The above is only one implementation manner of the embodiment of the present invention, and as shown in fig. 3, fig. 3 is a top view system-in-package structure 1 of the system-in-package structure provided in the embodiment of the present invention, which includes second pads 10, where the second pads 10 are used for connecting an external circuit; the pins 8 comprise a first pin 8a and a second pin 8b, the first pin 8a is electrically connected with the passive device 4, and the second pin 8b is used for connecting an external circuit; the second pin 8b is electrically connected to the second pad 10. Wherein, the second pin 8b and the second pad 10 are exposed outside the plastic sealing layer 7, and a connection end electrically interconnected with an external device is realized. In this embodiment, the number of the second pads 10 may be, for example, 1, 2, 3, 4 or more, the number of the second pads 10 may be set according to the actual requirement of the circuit, and the number of the second pads 10 is not limited in the present invention.
In the present embodiment, the conductive frame 5 is at least partially multiplexed into the leads 8; the pin 8 may also adopt other conductive devices or conductive materials to implement electrical connection between electronic components in the package structure, and the embodiment of the present invention does not limit the structure and the material of the pin 8.
An embodiment of the present invention further provides a method for manufacturing a system-in-package structure, as shown in fig. 4, fig. 4 is a process flow diagram of the method for manufacturing a system-in-package structure according to the embodiment of the present invention; in combination with the system in package structure shown in fig. 1 and fig. 1a, the manufacturing method of the system in package structure 1 includes the following steps:
step 1: providing a carrier plate, and forming a metal layer on the carrier plate.
In step 1, a carrier is provided, and a metal layer is formed on the carrier, wherein the metal layer may be made of copper or other metal with good electrical conductivity.
Step 2: and etching the metal layer to obtain a conductive frame 5, wherein the conductive frame 5 is at least partially multiplexed into the passive device 4 and the base island 6.
In step 2, with reference to the system-in-package structure shown in fig. 1 and fig. 1a, specific contents of this step include, for example: forming a first graphical mask layer on the metal layer; the first patterned mask layer exposes the passive device 4, the conductive frame 5 and the metal layer outside the base island 6; corroding the metal layer by taking the first graphical mask layer as a mask, reserving the metal layers of the passive device 4, the conductive frame 5 and the base island 6, and removing the metal layers in the rest areas; and removing the first patterned mask layer to obtain the conductive frame 5, wherein the conductive frame 5 is at least partially multiplexed into the passive device 4 and the base island 6.
In some embodiments, the thickness of the conductive frame 5 is 50um-300um, and the conductive frame 5 within the thickness range can play a good supporting role and can meet the requirement of multiplexing as a passive device. The conductive frame 5 may be made of a metal having excellent conductivity, such as copper.
In some embodiments, the passive device 4 may comprise at least one of a resistive, an inductive, and a capacitive element, for example, and the passive device 4 may be characterized by operating in the presence of a signal without the need for a power source in the circuit. Preferably, the inductance-type element mainly refers to an inductance-type element with a coil-type structure.
And step 3: at least one die 2 is disposed on the base island 6.
In step 3, at least one die 2 may be disposed on the base island 6, specifically as required by the actual chip circuit design. In some embodiments, the number of the die 2 may be 1, 2, 3, etc., and the die 2 may be a power die, a memory die, a sensing die, or a radio frequency die, for example. The present embodiment does not limit the function of the die 2. Embodiments of the present invention are not limited to the number of dies provided in a single base island. In connection with the system-in-package structure shown in fig. 1 and 1a, one die 2 is disposed on a base island 6.
In the manufacturing method of the system-in-package structure provided by the embodiment of the invention, the bare chip is in a forward mounting structure, and the bare chip can be directly placed on the base island, so that the whole manufacturing process is simple and easy to operate.
And 4, step 4: a plurality of first bonding pads 3 are arranged on the bare chip 2, and the bare chip 2 is electrically connected with the first bonding pads 3.
In step 4, several first pads 3 may be provided on the die 2, wherein the die 2 is electrically connected with the first pads 3. In connection with the system-in-package structure shown in fig. 1 and 1a, 2 first pads 3 are provided on a die 2.
In some embodiments, the number of the first pads 3 may be, for example, 1, 2, 3, 4 or more, the number of the first pads 3 may be set according to the actual requirement of the circuit, and the invention does not limit the number of the first pads 3.
And 5: a molding layer 7 embedding the die 2, the first pad 3, the passive component 4, the conductive frame 5 and the base island 6 is formed on the carrier board.
In step 5, a molding layer 7 formed on the carrier plate embeds the bare chip 2, the first bonding pad 3, the passive device 4, the conductive frame 5 and the base island 6, and the whole device is packaged.
In some embodiments, the thickness of the plastic sealing layer 7 is 0.4mm to 1.5mm, and the plastic sealing layer 7 with the thickness can ensure the stability and firmness of the plastic sealing layer 7. The material of the encapsulating layer 7 may be, for example, epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the plastic sealing layer 7 can also be various polymers or composite materials of resin and polymer.
Step 6: and removing the carrier plate.
In step 6, after the encapsulation layer 7 embeds the bare chip 2, the first bonding pad 3, the passive device 4, the conductive frame 5 and the base island 6, the carrier board is removed, and at this time, the encapsulation layer 7 already fixedly arranges the bare chip 2, the first bonding pad 3, the passive device 4, the conductive frame 5 and the base island 6 together, and at this time, the structure of the carrier board can be removed.
And 7: and cutting to form the system-in-package structure.
In step 7, the packaging assembly in which the die 2, the first pad 3, the passive device 4, the conductive frame 5 and the base island 6 are embedded by using the plastic encapsulation layer 7 is cut, and the plastic encapsulation layer part without the embedded device is removed, so that the system-in-package structure is formed.
The method for manufacturing the system-in-package structure provided by the embodiment of the invention can realize that the conductive frame and the passive device and the base island are formed in the same process, so that the production efficiency can be improved on one hand, and the miniaturization of the system-in-package structure can be realized on the other hand.
The above is only one implementation manner of the embodiment of the present invention, and the implementation manner of the embodiment of the present invention may also be, according to the process steps in fig. 4 and in combination with the system-in-package structure shown in fig. 2, step 2: and etching the metal layer to obtain a conductive frame 5, wherein the conductive frame 5 is at least partially multiplexed into the passive device 4 and the base island 6. The specific content of this step further includes, for example: the passive device 4 obtained by etching the metal layer comprises a capacitance element 4a and a resistance element 4b, namely the conductive frame 5 is multiplexed into two passive devices with different functions so as to meet different circuit designs and circuit requirements in a chip. In this embodiment, the passive device 4 may include at least one of a resistor, an inductor, and a capacitor, for example, and the passive device 4 is characterized by operating in the presence of a signal without applying a power source in the circuit. The inductance component is mainly an inductance component with a coil structure. In this embodiment, electrically conductive frame 5 can multiplex simultaneously for passive device 4 of different functions, need not to encapsulate original passive device 4 inside the chip, simplifies the inner structure of chip, satisfies the inside circuit demand of chip simultaneously, can reach the miniaturized demand of SIP again. The number of the base islands 6 may be, for example, 1, 2, 3, or the like, and the shape of the base islands 6 may be, for example, a polygonal or circular structure such as a square or a rectangle, and may be specifically set according to the requirements of the actual chip circuit design. The number of the base islands is not limited in the embodiment of the invention.
In some embodiments, in conjunction with the system-in-package structure shown in fig. 2, step 3: at least one die 2 is disposed on the base island 6. The specific content of this step further includes, for example: two dies 2 are disposed on the base island 6. In the embodiment of the present invention, the number of the die 2 may be 1, 2, 3, or the like, and the die 2 may be a power die, a memory die, a sensing die, or a radio frequency die, for example. The present embodiment does not limit the function of the die 2. One base island 6 may have 1 or more dies 2 disposed thereon, and may be specifically configured according to the requirements of the actual chip circuit design. Embodiments of the present invention are not limited to the number of dies provided in a single base island.
The above is only one implementation manner of the embodiment of the present invention, and the implementation manner of the embodiment of the present invention may also be, according to the process steps in fig. 4 and in combination with the system-in-package structure shown in fig. 3, step 2: and etching the metal layer to obtain a conductive frame 5, wherein the conductive frame 5 is at least partially multiplexed into the passive device 4 and the base island 6. The specific content of this step further includes, for example: and etching the metal layer to obtain a pin 8, wherein the pin 8 comprises a first pin 8a and a second pin 8b, the first pin 8a is electrically connected with the passive device 4, and the second pin 8b is used for electrically connecting with an external circuit. In the present embodiment, the conductive frame 5 is at least partially multiplexed into the leads 8; the pin 8 may also adopt other conductive devices or conductive materials to implement electrical connection between electronic components in the package structure, and the embodiment of the present invention does not limit the structure and the material of the pin 8.
In some embodiments, in conjunction with the system-in-package structure shown in fig. 3, step 4: a plurality of first bonding pads 3 are arranged on the bare chip 2, and the bare chip 2 is electrically connected with the first bonding pads 3. The specific content of this step includes, for example: providing a first pad 3 on the die 2; and, a second pad 10 is provided on the second lead 8 b; the second pin 8b is electrically connected to the second pad 10. In this embodiment, the number of the second pads 10 may be 1, 2, 3, 4 or more, the number of the second pads 10 may be set according to the actual requirement of the circuit, and the invention does not limit the number of the second pads 10.
In some embodiments, in conjunction with the system-in-package structure shown in fig. 3, step 5: a molding layer 7 embedding the die 2, the first pad 3, the passive component 4, the conductive frame 5 and the base island 6 is formed on the carrier board. In some embodiments, for example, before step 5, further comprising: a conductive lead 9 is formed on the first pad 3, and the first pad 3 is electrically connected to the lead 8 through the conductive lead 9. The first bonding pad 3 is electrically connected with the passive device 4 through the conductive lead 9; the conductive lead 9 has a parabolic structure.
In some embodiments, in conjunction with the system-in-package structure shown in fig. 3, step 5: a molding layer 7 embedding the die 2, the first pad 3, the passive component 4, the conductive frame 5 and the base island 6 is formed on the carrier board. The specific content of this step further includes, for example: exposing the second lead 8b and the second pad 10. In the embodiment, the second pins 8b for connecting the external circuit and the device are formed simultaneously in the process of etching the conductive frame 5, and when the first bonding pad 3 is arranged on the bare chip 2, the second bonding pad 10 for connecting the external circuit and the device is arranged on the second pins 8 b.
The system-in-package structure and the manufacturing method thereof provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained in detail herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A system in a package structure, comprising: at least one bare chip, a plurality of first bonding pads, a conductive frame and a plastic encapsulation layer;
the conductive frame is at least partially multiplexed into a passive device and a base island;
the die is disposed on the base island, the first bonding pad is disposed on the die, and the die is electrically connected to the first bonding pad; the first bonding pad is electrically connected with the passive device;
the encapsulation layer encapsulates the die, the first pad, the passive device, the conductive frame, and the base island.
2. The system-in-package structure of claim 1, wherein the passive device is at least one of a resistive, inductive, and capacitive element.
3. The system-in-package structure of claim 1, comprising a pin; the pins comprise a first pin and a second pin, the first pin is electrically connected with the passive device, and the second pin is used for connecting an external circuit.
4. The system-in-package structure according to claim 3, comprising conductive leads, wherein the first pad is electrically connected to the first and second leads through the conductive leads, respectively.
5. The system-in-package structure according to claim 1, wherein the thickness of the plastic encapsulation layer is 0.4mm-1.5 mm.
6. The system-in-package structure of claim 1, wherein the conductive frame has a thickness of 50um-300 um.
7. A method for manufacturing a system-in-package structure, comprising:
providing a carrier plate, and forming a metal layer on the carrier plate;
etching the metal layer to obtain a conductive frame, wherein at least part of the conductive frame is multiplexed into a passive device and a base island;
disposing at least one die on the base island;
providing a number of first bonding pads on the die, the die being electrically connected to the first bonding pads;
forming a molding layer embedding the die, the first bonding pad, the passive device, the conductive frame and the base island on the carrier board;
removing the carrier plate;
and cutting to form the system-in-package structure.
8. The method of claim 7, wherein etching the metal layer to obtain a conductive frame, the conductive frame being at least partially reused as a passive device and a base island, comprises:
and etching the metal layer to obtain pins, wherein the pins comprise a first pin and a second pin, the first pin is electrically connected with the passive device, and the second pin is used for connecting an external circuit.
9. The method for manufacturing a system-in-package structure according to claim 8, wherein before forming a molding layer on the carrier board, the die, the first bonding pad, the passive device, the conductive frame and the base island, the molding layer comprises:
and arranging a conductive lead on the first bonding pad, wherein the first bonding pad is electrically connected with the first pin and the second pin through the conductive lead respectively.
10. The method for manufacturing a system-in-package structure according to claim 9, wherein the forming a molding layer on the carrier board embedding the die, the first bonding pad, the passive device, the conductive frame and the base island comprises:
exposing the second pin.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111223302.1A CN114121865A (en) | 2021-10-20 | 2021-10-20 | System-in-package structure and manufacturing method thereof |
| PCT/CN2022/099441 WO2023065695A1 (en) | 2021-10-20 | 2022-06-17 | System-in-package structure and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111223302.1A CN114121865A (en) | 2021-10-20 | 2021-10-20 | System-in-package structure and manufacturing method thereof |
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| CN202111223302.1A Pending CN114121865A (en) | 2021-10-20 | 2021-10-20 | System-in-package structure and manufacturing method thereof |
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| WO (1) | WO2023065695A1 (en) |
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|---|---|---|---|---|
| WO2023065695A1 (en) * | 2021-10-20 | 2023-04-27 | 上海闻泰信息技术有限公司 | System-in-package structure and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06104372A (en) * | 1992-09-22 | 1994-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US5444600A (en) * | 1992-12-03 | 1995-08-22 | Linear Technology Corporation | Lead frame capacitor and capacitively-coupled isolator circuit using the same |
| EP1403926A2 (en) * | 2002-09-27 | 2004-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
| US8446159B2 (en) * | 2010-06-30 | 2013-05-21 | Linear Technology Corporation | Current sensor using leadframe as sensing element |
| CN114121864A (en) * | 2021-10-20 | 2022-03-01 | 上海闻泰信息技术有限公司 | System-in-package structure and manufacturing method thereof |
| CN114121865A (en) * | 2021-10-20 | 2022-03-01 | 上海闻泰信息技术有限公司 | System-in-package structure and manufacturing method thereof |
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2021
- 2021-10-20 CN CN202111223302.1A patent/CN114121865A/en active Pending
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| WO2023065695A1 (en) * | 2021-10-20 | 2023-04-27 | 上海闻泰信息技术有限公司 | System-in-package structure and manufacturing method therefor |
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