CN114117943B - Timing Prediction Methods in the Layout Phase of Physical Designs - Google Patents

Abstract

The present invention provides a time sequence prediction method in a physical design layout stage, comprising: step 1, dividing the acquired process library, circuit netlist and layout result data into a training set and a test set, and performing the steps based on the training set and the test set respectively The circuit timing features of the training set and the circuit timing features of the test set are extracted; step 2, the circuit timing features of the training set and the Sign-Off timing results corresponding to the training set are input into the random forest model for training, and the network-based delay is obtained. prediction model. The gap between the timing prediction of the present invention and the timing result of Sign-Off is small, the accuracy of timing prediction is improved, and in the process of chip design, it can well guide the additional impact of performance and power consumption caused by timing optimization, and achieve accurate timing. timing prediction, reducing the entire chip design cycle and cost.

Description

Timing Prediction Methods in the Layout Phase of Physical Designs

technical field

The invention relates to the technical field of timing prediction, in particular to a timing prediction method in a physical design layout stage.

Background technique

In chip design, the accuracy of timing analysis is very important to guide timing optimization and ensure chip timing closure and operating performance. During the placement stage, a fast and accurate timing analysis tool can guide timing optimization during the placement stage and shorten the design cycle.

Static Timing Analysis (STA) is an important means to verify timing closure. In static timing analysis, the circuit netlist is modeled as a Directed Acyclic Graph (DAG). The input and output ports (Primary Input & Output port, PIO) and pins (Pins) in the circuit diagram correspond to the nodes of the directed acyclic graph, the internal timing arcs of the wire-net connection or the gate, and correspond to the edges of the directed acyclic graph. The delay of the timing arc, corresponding to the weight of the edge. In a directed acyclic graph, all nodes can be topologically sorted, and the arrival time (AT) of each node can be calculated by layer traversal. Then, according to the required time of the terminal node (register data terminal or output port), the required arrival time (RAT) of each node in the circuit diagram is calculated inversely. Finally, according to the difference between the arrival time of each node and the required arrival time of each node, the time slack (Slack) of each node is obtained. If the slack is negative, the delay requirement is not met, and timing optimization needs to be performed in the subsequent design. According to the directed acyclic graph, the delay of the edge belongs to the internal delay of the gate circuit, which can be divided into gate delay and wire delay. In the static timing analysis, the gate delay can be calculated by the table look-up method according to the characteristics of the components in the process library (Lib file) and the Slew value of the output load and input pin, and the line delay can be calculated according to the wiring information. The time delay model is obtained.

However, in the layout stage, there is no wiring and no specific resistance and capacitance (RC) information, and the gate delay and line delay cannot be accurately calculated. Therefore, at present, there are three main methods for timing analysis in the layout stage:

Pessimistic prediction: Due to the lack of wiring information, in order to ensure that the circuit can meet the timing requirements in the worst case, pessimistic prediction will be added to the circuit during timing analysis. In practice, traditional pessimistic forecasting methods have additional impacts on chip performance and power consumption because the worst-case scenario is rare. Practical experience shows that the gap between the predicted performance and the final tape-out performance of EDA tools based on pessimistic prediction can be as high as 30%.

Increase iterative design iterations: If the subsequent routing results cannot meet the delay requirements and the design does not converge, local corrections are required, or even return to the previous stage for redesign. Repeated iterations of this design will greatly increase the entire chip design cycle and cost.

Machine learning-based time series forecasting: In order to improve over-pessimism in forecasting, improve forecasting accuracy, and reduce design iterations, machine learning methods are introduced. This method trains a timing model by using existing design data. The resulting model can provide timing prediction for unknown circuit designs under the same process in the layout stage. For time series prediction based on machine learning, it is necessary to extract as many time series-related features as possible in the layout stage and establish a prediction model. The correlation between the prediction results and the sign-off time series results is the main basis for measuring the accuracy of the model.

SUMMARY OF THE INVENTION

The present invention provides a timing prediction method in the physical design layout stage, the purpose of which is to solve the problem of a large gap between the performance of the timing prediction of the traditional timing prediction method and the timing performance of the final Sign-Off. In this case, timing optimization cannot be well guided, resulting in additional impact on performance and power consumption. Inaccurate timing prediction will greatly increase the entire chip design cycle and cost.

In order to achieve the above object, an embodiment of the present invention provides a timing prediction method in a physical design layout stage, including:

Step 1: Divide the acquired process library, circuit netlist and its layout result data into a training set and a test set, and extract the circuit timing features of the training set and the circuit timing features of the test set based on the training set and the test set respectively;

Step 2, input the circuit timing characteristics of the training set and the Sign-Off timing results corresponding to the training set into the random forest model for training, and obtain a delay prediction model based on the wire network;

Step 3, inputting the circuit timing characteristics of the test set into the network-based delay prediction model for delay prediction, and obtaining the line network Sign-Off delay prediction result of each circuit in the test set;

Step 4, perform circuit diagram topology traversal on the wire net Sign-Off delay prediction results of each circuit in the test set, and calculate the time margin of the output pins of each wire net of each circuit;

In step 5, the critical path and the non-critical path are distinguished according to the calculated time margin, and the critical path prediction result of each circuit in the test set is obtained.

Wherein, the step 1 specifically includes:

Step 11: Divide the given process library, circuit netlist and its layout result data into a training set and a test set;

Step 12: Perform pre-wiring analysis on the data in the training set and the test set, respectively, to obtain the pre-wiring analysis result of the training set and the pre-wiring analysis result of the test set;

Step 13, according to the pre-wiring analysis result of the training set, obtain the RC network generated based on the pre-wiring analysis of the training set, and obtain the RC network generated based on the pre-wiring analysis of the test set according to the pre-wiring analysis result of the test set;

Step 14: According to the pre-wiring analysis result of the training set, combine the circuit netlist data and its layout result data and the process library data in the training set to perform circuit timing feature extraction to obtain the circuit timing features of the training set; The circuit netlist data and its layout result data and process library data in the test set are used to extract the circuit timing characteristics, and the circuit timing characteristics of the test set are obtained.

Wherein, the step 12 specifically includes:

Step 121, perform pre-wiring analysis on each circuit in the training set, including the following steps:

Step 1211: Acquire the position information of the pins in each net of each circuit in the training set, and use the minimum Steiner tree algorithm to divide the multi-terminal net according to the position information of the pins in each net of each circuit in the training set. It is divided into multiple connection relationships at both ends, and L-shaped wiring is performed on each connection relationship at both ends to obtain the pre-wiring analysis result of the training set.

Wherein, the step 12 specifically includes:

Step 122, perform pre-wiring analysis on each circuit in the test set, including the following steps:

Step 1221: Obtain the position information of pins in each net of each circuit in the test set, and use the minimum Steiner tree algorithm to divide the multi-terminal net according to the position information of the pins in each net of each circuit in the test set. It is divided into multiple connection relationships at both ends, and L-shaped wiring is performed on each connection relationship at both ends to obtain the pre-wiring analysis result of the test set.

Wherein, the step 14 specifically includes:

The circuit timing characteristics of the training set and the circuit timing characteristics of the test set include: drive strength, fan-out number, output load, gate transition tilt under nonlinear model, gate delay under nonlinear model, distance, Elmore delay, ContextElmore delay and D2M delay.

Wherein, the step 2 specifically includes:

In the network-based delay prediction model, the gate delay and the line delay are combined together for prediction. The line delay of the connection to the fan-out, the gate delay of the driving door and the line delay of the connection to a certain fan-out, the two delays are combined, which is called the line network delay. The delay prediction model is used to predict the network delay;

In the net-based delay prediction model, the output pin node of the gate is removed in the directed acyclic graph, and a net is the input pin from one input pin of the gate to one of its fan-outs, which is merged into An edge of a directed acyclic graph, the weight of the edge includes the gate delay from the input pin to the output pin in the driver and the line delay of the connection from the driver output pin to the fanout input pin.

Wherein, the step 2 specifically includes:

In the network-based delay prediction model, the gate delay has 4 different values, corresponding to the following four situations: the signal of the gate input pin is a rising edge, the signal of the gate output pin is a falling edge; the gate input pin is a rising edge. The signal of the gate output pin is the rising edge, the signal of the gate output pin is the rising edge; the signal of the gate input pin is the falling edge, the signal of the gate output pin is the rising edge; the signal of the gate input pin is the falling edge, the gate output pin is the falling edge The signal is a falling edge.

Wherein, the step 2 further includes:

The signal transition of the input pin of the line delay is consistent with the signal transition of the output pin. When the drive gate and its fan-out connection are combined as a line network, the delay time, a line network delay considers the above four cases , one network corresponds to 4 samples, and the delays in different situations are predicted respectively. The timing characteristics and Sign-Off delays in different situations are different. Therefore, the characteristics and delays corresponding to different samples are different.

Wherein, the step 4 specifically includes:

The circuit diagram topology traversal is performed according to the wire net Sign-Off delay prediction results of each circuit in the test set, and the arrival delay of the output pins of each wire net of each circuit in the test set is calculated, and then each circuit in the test set is obtained. Time slack for the output pins of each net.

Wherein, the step 5 specifically includes:

Based on the time margin of the output pins of each net of each circuit in the test set, the critical path and the non-critical path of each circuit are distinguished, and the output pins of each net of each circuit in the test set are judged in turn. Whether the time margin is negative, when the time margin of the output pin of the current net is negative, the circuit corresponding to the current net has a timing violation, and the current net is the critical path; when the time margin of the output pin of the current net is positive, the time sequence of the circuit corresponding to the current line net is normal, the current line net is a non-critical path, and the critical path prediction result of each circuit in the test set is obtained.

The above-mentioned scheme of the present invention has the following beneficial effects:

In the timing prediction method in the physical design layout stage described in the above-mentioned embodiments of the present invention, the gap between timing prediction and the timing result of Sign-Off is small, the accuracy of timing prediction is improved, and in the process of chip design, it can be well The additional impact of performance and power consumption brought about by ground guidance timing optimization, achieve accurate timing prediction, and reduce the overall chip design cycle and cost.

Description of drawings

Fig. 1 is the concrete flow chart of the present invention;

Fig. 2 is the overall flow chart of the present invention;

3 is a schematic diagram of converting the circuit netlist diagram of the present invention into a directed acyclic graph, wherein (a) is the circuit netlist diagram of the present invention; (b) is the directed acyclic graph of the present invention;

FIG. 4 is a schematic diagram of pre-wiring analysis and timing feature extraction of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, the following will be described in detail with reference to the accompanying drawings and specific embodiments.

Aiming at the existing traditional time sequence prediction method, the present invention will bring additional impact on chip performance and power consumption, greatly increase the entire chip design cycle and cost, and the gap between the predicted performance and the final tape-out performance is large. problem, provides a timing prediction method in the layout stage of the physical design.

As shown in FIG. 1 to FIG. 4 , an embodiment of the present invention provides a timing prediction method in a physical design layout stage, including: Step 1: Divide the acquired process library, circuit netlist and layout result data into a training set and test set, extract the circuit timing features of the training set and the circuit timing features of the test set based on the training set and the test set respectively; Step 2, input the circuit timing features of the training set and the corresponding Sign-Off timing results of the training set into the random forest Carry out training in the model to obtain a network-based delay prediction model; step 3, input the circuit timing characteristics of the test set into the network-based delay prediction model for delay prediction, and obtain the network Sign-Off of each circuit in the test set Time delay prediction result; Step 4, perform circuit diagram topology traversal on the wire net Sign-Off time delay prediction result of each circuit in the test set, and calculate the time margin of the output pin of each wire net of each circuit; Step 5, The critical path and the non-critical path are distinguished according to the calculated time margin, and the critical path prediction result of each circuit in the test set is obtained.

In the time sequence prediction method in the physical design layout stage described in the above-mentioned embodiment of the present invention, the difference between the time delay prediction model based on the wire network and the previous separate prediction of the Gate Delay model and the Wire Delay model is as follows: the number of models and the complexity: if To predict Gate Delay and Wire Delay separately, there are generally existing methods, but additional prediction or calculation of Wire Slew and Output Load is required, and 2-4 models need to be trained, which increases the number and complexity of the models. Prediction time and error: On a path, Gate Delay and Wire Delay alternate in stages. If Gate Delay and Wire Delay are predicted separately, the accuracy of Gate Delay and Wire Delay predicting input features is stage-by-stage dependent on each other. Increase forecast time and accumulated error. The delay prediction model based on the line network only needs to train one model, which not only simplifies the model, but also can extract the time series features of all lines and networks at one time, without the need for first-level information transmission on the path, which reduces the complexity of the model. At the same time, the accumulated error is also eliminated.

Wherein, the step 1 specifically includes: step 11, dividing the given process library, circuit netlist and its layout result data into a training set and a test set; step 12, pre-wiring the data in the training set and the test set respectively Analysis to obtain the pre-wiring analysis result of the training set and the pre-wiring analysis result of the test set; step 13, according to the pre-wiring analysis result of the training set, obtain the RC network generated based on the pre-wiring analysis of the training set, and obtain the RC network based on the pre-wiring analysis of the test set according to the pre-wiring analysis result of the test set. The RC network generated by the pre-wiring analysis of the test set; Step 14, according to the pre-wiring analysis result of the training set, combined with the circuit netlist data and its layout result data and the process library data in the training set, perform circuit timing feature extraction, and obtain the circuit timing features of the training set. ;According to the pre-wiring analysis results of the test set, combined with the circuit netlist data and its layout result data and process library data in the test set, the circuit timing characteristics are extracted, and the circuit timing characteristics of the test set are obtained.

Wherein, the step 12 specifically includes: step 121, performing pre-wiring analysis on each circuit in the training set, including the following steps: step 1211, acquiring the position information of the pins in each net of each circuit in the training set, According to the position information of the pins in each wire net of each circuit in the training set, the multi-terminal wire net is divided into multiple two-terminal connection relationships by using the minimum Steiner tree algorithm, and L-shaped wiring is performed on each two-terminal connection relationship. Get the training set pre-wiring analysis results.

Wherein, the step 12 specifically includes: step 122, performing pre-wiring analysis on each circuit in the test set, including the following steps: step 1221, acquiring position information of pins in each wire net of each circuit in the test set, According to the position information of the pins in each wire net of each circuit in the test set, the multi-terminal wire net is divided into multiple two-terminal connection relationships by using the minimum Steiner tree algorithm, and L-shaped wiring is performed on each two-terminal connection relationship. Get the test set pre-wiring analysis results.

Wherein, the step 14 specifically includes: the circuit timing characteristics of the training set and the circuit timing characteristics of the test set include: driving strength, number of fan-outs, output load, gate conversion inclination under the nonlinear model, and Gate Delay, Distance, Elmore Delay, ContextElmore Delay, and D2M Delay.

In the timing prediction method of the physical design layout stage described in the above-mentioned embodiment of the present invention, the pre-wiring analysis will firstly use the minimum Steiner tree algorithm (Minimal Steiner Tree, MST) according to the position information of the pins in the wire net to convert the input The Multi-Pin Net is divided into multiple connection relationships at both ends, and L-shaped wiring is performed for each connection relationship at both ends to obtain pre-wiring analysis results. As shown in Figure 4, the wire net n ₃ is a multi-terminal wire net, and the drive gate c ₁ has two fan-out pins d and f. First, the minimum Steiner Tree (MST) is divided for n ₃ to The red Steiner point is bounded, and three connection relationships between two ends can be obtained (r to Steiner point, Steiner point to d, Steiner point to f), and L-shaped wiring is used for each connection at both ends, and the net n is obtained. ₃ pre-wired results.

After pre-wiring, one input pin of each drive gate is combined with one of its fan-out pins, and it is regarded as a net. Table 1 shows the delay prediction model based on net. required features.

Table 1 Summary of time series feature extraction

Based on the pre-routing analysis results, combined with the circuit netlist and its layout result information and process library information, the following timing characteristics can be obtained:

Drive strength: As the drive strength of the drive gate, it can be obtained directly from the process library Lib file through the corresponding component lookup table;

Number of fan-outs: the number of fan-outs of the drive gate, that is, the number of receiving pins, provided by the circuit netlist;

Output load: The load of the output pin of the drive gate, that is, the connection capacitance to all fan-outs, can be calculated according to RCNetwork (network);

NLDM Gate Slew: Gate Slew calculated according to the NLDM model. It can be calculated by Non-Linear Delay Model (NLDM) according to the lookup table of the Lib file in the process library, through the output load and the Slew value of the input pin;

NLDM Gate Delay: The drive gate delay calculated according to the NLDM model. According to the process library, the Lib file lookup table, through the output load, and the Slew value of the input pin, it can be calculated by NLDM;

Distance: The Manhattan distance from the net driving pin to the receiving pin, calculated from the input layout coordinates;

Elmore delay: The Elmore delay from the wire net driving pin to the current receiving pin can be obtained according to the process library and pre-wiring results to obtain the RC Network, and then use the Elmore model formula to calculate;

Context Elmore delay: In addition to the current receiving pin, other receiving pins in the same input multi-terminal network, the sum of the Elmore delay. For example, in Figure 4, the context Elmore delay of pin d is the Elmore delay from r to f;

D2M delay: D2M delay from drive pin to accept pin. According to the RC Network, it can be obtained through the calculation formula of the D2M model.

Taking the wire net from the input b of the drive gate to the output pin d as an example, the corresponding eigenvalue extraction information is given in Figure 4.

Wherein, the step 2 specifically includes: in the delay prediction model based on the line network, combining the gate delay and the line delay together for prediction, from an input of the drive gate to a corresponding fan-out receiving end, through The gate delay of the driving door and the line delay of the connection to the fan-out, the gate delay of the driving door and the line delay of the connection to a certain fan-out, the two delays are combined, called the line Net delay, the net-based delay prediction model is used to predict the net delay; in the net-based delay prediction model, the output pin node of the gate is removed in the directed acyclic graph, and a net It is an edge from an input pin of a gate to an input pin of its fan-out, which is merged into a directed acyclic graph. The weight of the edge includes the gate delay from the input pin to the output pin in the driver and the driver output. Line delay of pin-to-fanout input pin connections.

Wherein, the step 2 specifically includes: in the network-based delay prediction model, the gate delay has 4 different values, corresponding to the following four situations: the signal of the gate input pin is a rising edge, and the gate output pin has a rising edge. The signal is the falling edge; the signal of the gate input pin is the rising edge, the signal of the gate output pin is the rising edge; the signal of the gate input pin is the falling edge, the signal of the gate output pin is the rising edge; the signal of the gate input pin is the rising edge; The signal is a falling edge, and the signal at the gate output pin is a falling edge.

The timing prediction method in the physical design layout stage described in the above-mentioned embodiments of the present invention is shown in FIG. 4 , and as shown in FIG. 3( a ), path 1 goes from the output end q of the FF to the input end e of the next stage FF , the entire delay of path 1 is summed alternately by Gate Delay and Wire Delay; in Figure 3(b), the delay from a to u is Gate Delay, and the delay from u to c is WireDelay, where a and u They are the input and output pins of the drive gate respectively. The fan-out receiving pin of the drive gate is c. The gate delay of the drive gate and the delay of the connection line to a certain fan-out, the two delays are combined, called is a network delay, namely Net Delay. The network-based delay prediction model is to predict the network delay.

In the time sequence prediction method in the physical design layout stage described in the above-mentioned embodiments of the present invention, in the time delay prediction model based on the wire net, the output pin node of the gate is removed in the DAG, and a wire net is an input from the gate The pin to one of its fan-out input pins is merged into a DAG edge. The weight of the q edge includes the gate delay from the input pin to the output pin in the driver and the connection from the driver output pin to the fan-out input pin. Line delay of the line. Figure 3(a) shows the circuit netlist under the network-based delay prediction model. Figure 3(b) corresponds to an example of a directed acyclic graph. The network-based delay prediction model is to predict the network delay. , the delay of each edge.

Wherein, the step 2 further includes: the signal transition of the input pin of the line delay is consistent with the signal transition of the output pin, and when the combined drive gate and its fan-out connection are used as a line network, the delay time, a line The network delay considers the above four cases. One network corresponds to 4 samples, and the delays in different situations are predicted respectively. The timing characteristics and Sign-Off delays in different situations are different. Therefore, the characteristics corresponding to different samples different from delay.

The time sequence prediction method in the physical design layout stage described in the above-mentioned embodiment of the present invention is based on the time delay prediction model of the wire network. Due to the jump of the signal during the propagation of the electrical signal, that is, the jump of the waveform, it is generally divided into two types: rise and fall. In the gate circuit, the delay from one input pin to one output pin needs to consider different situations of rising and falling. Therefore, inside the gate, the delay from its input pin to the output pin may have more than one value. That is, there are many cases of gate delay. In the timing prediction method in the physical design layout stage, the gate delay has at most 4 different values, corresponding to the following four situations:

The signal at the gate input pin is a rising edge, and the signal at the gate output pin is a falling edge;

The signal at the gate input pin is a rising edge, and the signal at the gate output pin is a rising edge;

The signal at the gate input pin is a falling edge, and the signal at the gate output pin is a rising edge;

The signal of the gate input pin is the falling edge, and the signal of the gate output pin is the falling edge;

Since the signal transition of the input pin of the line delay is consistent with the signal transition of the output pin, when the drive gate and its fan-out connection are combined as a line network, the delay time of one line network is the most. The above four situations also need to be considered, that is, a network can correspond to a maximum of 4 samples, and the delays in different situations can be predicted respectively. Since the timing features and Sign-Off delays are different in different situations, even in the same network, the corresponding features (Features) and delays (Ground Truth) of different samples are different. Taking Figure 3 as an example, the timing arc of b->d, when the input signal is a rising delay and the output signal is a falling edge, its corresponding characteristics and Sign-Off delay (Ground Truth) can be used as a data sample ; When the input signal is a falling delay and the output signal is a rising edge, its corresponding feature and Sign-Off delay (Ground Truth) are used as another data sample. Because the drive gate is an inverter, there are a total of 2 cases above, but there are no 4 cases, that is, the Net of b->d can extract 2 samples.

Wherein, the step 4 specifically includes: performing circuit diagram topology traversal according to the wire net Sign-Off delay prediction result of each circuit in the test set, and calculating the arrival delay of the output pin of each wire net of each circuit in the test set, Then, the time margin for the output pins of each net of each circuit in the test set is obtained.

Wherein, the step 5 specifically includes: distinguishing the critical path and the non-critical path of each circuit based on the time margin of the output pins of each wire net of each circuit in the test set, and sequentially judging the value of each circuit in the test set Whether the time margin of the output pin of each net is negative, when the time margin of the output pin of the current net is negative, the circuit corresponding to the current net has a timing violation, and the current net is the critical path; when the current net is the critical path; When the time margin of the output pin of the net is positive, the time sequence of the circuit corresponding to the current net is normal, the current net is a non-critical path, and the critical path prediction result of each circuit in the test set is obtained.

The timing prediction method in the physical design layout stage according to the above embodiment of the present invention, the timing prediction method in the physical design layout stage is implemented in C++17 and Pytorch 1.8.0, and is implemented in Intel Core i7 (@3.00 GHz) and 16 GB DDR4 PC for evaluation:

All training samples are combined to provide the Net-Based model for training. The timing prediction method in the physical design layout stage is carried out on the ITC'99 circuit, using the advanced 28nm process library. The data in the training set does not contain circuit designs from b17 and b22, and the data in the test set of b17 and b22 are used for model cross-validation, that is, to verify the prediction effect of our model on other unknown circuit designs under the same process. The timing ground truth of the experiment comes from the PrimeTime tool, which is hereinafter referred to as the Sign-Off result.

For comparison, the literature is reproduced: Erick C Barboza, Nishchal Shukla, Yiran Chen, et al. Machine Learning-Based Pre-Routing Timing Prediction with ReducedPessimism[C] //Proceedings of the 56th ACM/IEEE De-sign AutomationConference, 2019(106): DAC'19 feature extraction method proposed in 1-6. It can be seen that under the same model, the delay correlation degree of the line network delay prediction result of the timing prediction method in the physical design layout stage on the test set is as high as 0.99 on average, which proves that the physical design layout stage The effectiveness of temporal feature extraction for temporal prediction methods.

After the prediction result of the network delay, the topological sorting is used to obtain the arrival delay of each network output pin, and then the time margin is obtained. When the time margin of the register or output port is negative, it means that the circuit has a timing violation and is judged as a critical path.

Using the predicted delay of each net, the correlation between the time margin of the register or the output port and the Sign-Off report time margin Truth Ground is calculated. It can be seen that the time margin correlation of the timing prediction method in the physical design layout stage is as high as 0.97, which is much higher than that of the method proposed by DAC'19.

The purpose of static timing analysis is mainly to check timing violations, that is, to predict critical paths with negative Slack values, to provide a basis for subsequent timing evaluation and optimization.

In order to predict all the critical paths as much as possible, the predicted Slack is linearly corrected to increase the pessimism. After the correction, the TPR predicted by the timing prediction method in the physical design placement stage is almost close to 1. After the correction, the TNR results of the timing prediction method at the physical design placement stage decreased due to the increased pessimism, but were still about 30% higher than the DAC'19 method.

The timing prediction method in the physical design layout stage described in the above-mentioned embodiments of the present invention will not bring additional influence on chip performance and power consumption, reduce the entire chip design cycle and cost, and the predicted performance is consistent with the final tape-out. The gap between performances is small, which improves the accuracy of timing prediction, reduces design iterations, and eliminates accumulated errors while reducing model complexity.

The above are the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (9)

1. A method for predicting the time sequence of a physical design layout stage is characterized by comprising the following steps:

step 1, dividing the acquired process library, circuit netlist and layout result data thereof into a training set and a test set, and extracting circuit time sequence characteristics of the training set and circuit time sequence characteristics of the test set respectively based on the training set and the test set;

step 2, inputting the circuit time sequence characteristics of the training set and the Sign-Off time sequence results corresponding to the training set into a random forest model for training to obtain a time delay prediction model based on the wire network, wherein in the time delay prediction model based on the wire network, gate time delay and line time delay are combined together for prediction, the gate time delay of a driving gate and the line time delay of a certain fan-out connecting line are experienced from one input of the driving gate to a corresponding fan-out receiving end, the two time delays are combined and are called as wire network time delay, the time delay prediction model based on the wire network is used for predicting the wire network, in the time delay prediction model based on the wire network, the output pin nodes of the gate are removed from the directed acyclic graph, one wire network is from one input pin of the gate to one input pin of the fan-out pin and is combined into an edge of the directed acyclic graph, the edge weight comprises gate time delay from an input pin to an output pin in the driver and line time delay from the driving output pin to a fan-out input pin connection line;

step 3, inputting the circuit time sequence characteristics of the test set into a time delay prediction model based on a wire network to perform time delay prediction, and obtaining a wire network Sign-Off time delay prediction result of each circuit in the test set;

step 4, performing circuit diagram topology traversal on the wire net Sign-Off time delay prediction results of all circuits in the test set, and calculating the time margin of the output pin of each wire net of each circuit;

and 5, distinguishing a critical path from a non-critical path according to the calculated time margin to obtain a critical path prediction result of each circuit in the test set.

2. The method of claim 1, wherein the step 1 specifically comprises:

step 11, dividing a given process library, a given circuit netlist and layout result data thereof into a training set and a test set;

step 12, performing pre-wiring analysis on the data in the training set and the test set respectively to obtain a training set pre-wiring analysis result and a test set pre-wiring analysis result;

step 13, obtaining an RC network generated based on training set pre-wiring analysis according to the training set pre-wiring analysis result, and obtaining an RC network generated based on test set pre-wiring analysis according to the test set pre-wiring analysis result;

step 14, extracting circuit timing sequence characteristics by combining the circuit netlist data and the layout result data thereof in the training set and the process library data according to the pre-wiring analysis result of the training set to obtain the circuit timing sequence characteristics of the training set; and according to the test set pre-wiring analysis result, circuit timing sequence feature extraction is carried out by combining the circuit netlist data and the layout result data thereof as well as the process library data in the test set to obtain the circuit timing sequence feature of the test set.

3. The method of claim 2, wherein the step 12 specifically comprises:

step 121, performing pre-wiring analysis on each circuit in the training set, including the following steps:

step 1211, obtaining position information of pins in each net of each circuit in the training set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the training set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the training set.

4. The method of claim 3, wherein the step 12 specifically comprises:

step 122, performing pre-wiring analysis on each circuit in the test set, including the following steps:

step 1221, obtaining position information of pins in each net of each circuit in the test set, dividing the multi-terminal net into a plurality of two-terminal connection relations by adopting a minimum Steiner tree algorithm according to the position information of the pins in each net of each circuit in the test set, and performing L-type wiring on each two-terminal connection relation to obtain a pre-wiring analysis result of the test set.

5. The method of claim 4, wherein the step 14 specifically comprises:

the circuit timing characteristics of the training set and the circuit timing characteristics of the test set both include: drive strength, number of fan-outs, output load, gate transition tilt under a nonlinear model, gate delay under a nonlinear model, distance, Elmore delay, Context Elmore delay, and D2M delay.

6. The method of claim 5, wherein the step 2 specifically comprises:

in the time delay prediction model based on the wire network, the gate time delay has 4 different values, which correspond to the following four conditions: the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a falling edge; the signal of the gate input pin is a rising edge, and the signal of the gate output pin is a rising edge; the signal of the gate input pin is a falling edge, and the signal of the gate output pin is a rising edge; the signal at the gate input pin is a falling edge, and the signal at the gate output pin is a falling edge.

7. The method of claim 6, wherein the step 2 further comprises:

the signal jump of the input pin of the line delay is consistent with the signal jump of the output pin, when the combination driving gate and the fan-out connecting line of the combination driving gate are used as a line network, the time delay of one line network considers the four conditions, one line network corresponds to 4 samples, the time delay under different conditions is respectively predicted, and the time sequence characteristics and the Sign-Off time delay under different conditions are different, so the characteristics and the time delay corresponding to different samples are different.

8. The method of claim 7, wherein the step 4 specifically comprises:

and traversing the topology of the circuit diagram according to the prediction result of the line net Sign-Off time delay of each circuit in the test set, calculating the arrival time delay of the output pin of each line net of each circuit in the test set, and further obtaining the time margin of the output pin of each line net of each circuit in the test set.

9. The method of claim 8, wherein the step 5 comprises:

distinguishing a critical path and a non-critical path of each circuit based on the time margin of the output pin of each net of each circuit in the test set, sequentially judging whether the time margin of the output pin of each net of each circuit in the test set is negative, and when the time margin of the output pin of the current net is negative, a circuit corresponding to the current net generates time sequence violation, and the current net is the critical path; and when the time margin of the output pin of the current line network is positive, the time sequence of the circuit corresponding to the current line network is normal, the current line network is a non-critical path, and the critical path prediction result of each circuit in the test set is obtained.

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