CN114116553B - Data processing device, method and system - Google Patents

Abstract

The present disclosure provides a data processing apparatus, method and system, the data processing apparatus including a calculation unit, a transmission access request buffer and a command processing unit. The computing unit is configured to generate a transmission access request in response to data that needs to be transmitted; the transmission access request buffer is configured to buffer transmission access requests; the command processing unit is configured to: in response to a transmission access request buffered in the transmission access request buffer, the transmission access request is provided to the data transmission control device, whereby the data transmission control device responds to the transmission access request to transmit data to be transmitted. The data processing device can reduce the system overhead and improve the system performance.

Description

Data processing device, method and system

technical field

Embodiments of the present disclosure relate to a data processing device, a data processing method, and a data processing system.

Background technique

Direct memory access (Direct Memory Access, DMA) is a mechanism for fast data transfer in computer systems. The DMA method transfers data from one address space to another. The central processing unit (CPU) initiates the DMA transfer operation, and the transfer operation itself is directly executed and completed by the DMA controller. The DMA controller completely takes over control of the system bus from the CPU and is not dependent on the CPU. DMA transfer mainly involves four situations, but these four situations are essentially the same, and they are all transferred from a certain storage area to another storage area. These four cases include: peripheral to memory (Device to Host, D2H), memory to peripheral (H2D), memory to memory (H2H), peripheral to peripheral (D2D) (memory is considered to belong to the host side).

Contents of the invention

At least one embodiment of the present disclosure provides a data processing device, including:

a computing unit configured to generate a transfer access request in response to data to be transferred;

a transmission access request buffer configured to cache the transmission access request;

a command processing unit configured to: in response to the transmission access request buffered in the transmission access request buffer, provide the transmission access request to a data transmission control device, whereby the data transmission control device responds to the An access request is transmitted to transmit the data that needs to be transmitted.

For example, in the data processing device according to at least one embodiment of the present disclosure, the computing unit is further configured to, after generating the transmission access request, notify a central processing unit outside the data processing device.

For example, in the data processing device according to at least one embodiment of the present disclosure, the calculation unit is further configured to, after generating the transmission access request, query whether the transmission access request buffer is full, and respond to the The transmission access request buffer is not full, and the transmission access request is written into the transmission access request buffer.

For example, in the data processing apparatus according to at least one embodiment of the present disclosure, the transmission access request includes: a transmission source address, a transmission destination address, and a transmission data size.

For example, in the data processing apparatus according to at least one embodiment of the present disclosure, the transmission access request further includes a transmission status, and the transmission status includes pending transmission, transmission in progress, transmission completed, or transmission failed.

For example, the data processing device according to at least one embodiment of the present disclosure further includes: a command buffer configured to buffer operation instructions for the command processing unit; wherein the command processing unit is further configured to: When there is at least one operation instruction cached in the middle and at least one transmission access request is cached in the transmission access request buffer, the at least one transmission access request cached in the transmission access request buffer is preferentially processed.

For example, in the data processing device according to at least one embodiment of the present disclosure, the command processing unit is further configured to: after processing each operation instruction in the command buffer, query whether There is at least one transmission access request, in response to the pending transmission access request cached in the transmission access request buffer, after processing the pending transmission access request cached in the transmission access request buffer, then Return to process other operation instructions in the command buffer.

For example, in the data processing device according to at least one embodiment of the present disclosure, the transmission access request buffer is a first-in first-out buffer.

For example, in the data processing device according to at least one embodiment of the present disclosure, the command processing unit is further configured to provide the transmission access request to the data transmission control device outside the data processing device.

At least one embodiment of the present disclosure further provides a data processing system, the system comprising: any one of the above-mentioned data processing devices and the above-mentioned data transmission control device, the data transmission control device is configured to respond to the An access request is transmitted to transmit the data that needs to be transmitted.

For example, the data processing system according to at least one embodiment of the present disclosure further includes a central processing unit, wherein the computing unit is further configured to notify the central processing unit after generating the transmission access request.

For example, in the data processing system according to at least one embodiment of the present disclosure, the central processing unit is configured to continuously check the completion status of the transmission access request after receiving the notification about the transmission access request.

For example, in the data processing system according to at least one embodiment of the present disclosure, the data transmission control device includes a direct memory access device.

At least one embodiment of the present disclosure further provides a data processing method, the method including: generating a transmission access request in response to the data to be transmitted; caching the transmission access request; responding to the cached transmission access request, The transmission access request is provided to the data transmission control device; so that the data transmission control device responds to the transmission access request to transmit the data to be transmitted.

For example, the data processing method according to at least one embodiment of the present disclosure further includes: caching an operation instruction; enabling a command processing unit that executes the operation instruction and the transmission access request to process the transmission access request preferentially.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

Fig. 1 shows a schematic diagram of a computer system;

Fig. 2 shows a schematic diagram of a data processing device according to at least one embodiment of the present disclosure;

Figure 3 shows a schematic diagram of a data processing system according to at least one embodiment of the present disclosure;

Fig. 4 shows a schematic diagram of a data processing method according to at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.

The computer system may include one or more central processing units (CPUs), one or more depth computing units, such as image processors (GPUs), tensor processing units (TPUs), neural computing units (NPUs), etc. . In order to improve the overall performance of the system as much as possible, a close cooperation between the deep computing unit and the CPU is required. For example, when using a deep computing unit to continue large-scale matrix operations, frequent large-scale data transfer operations are required. At this time, using the DMA method has higher transmission efficiency.

Fig. 1 shows a kind of computer system, and this computer system comprises central processing unit (CPU) 101, depth calculation unit 100, DMA controller 103 and bus 104, central processing unit (CPU) 101, depth calculation unit 100, DMA control The devices 103 communicate with each other via the bus 104.

When the data required or generated by the depth calculation unit 100 needs to be transmitted in a DMA manner, for example, the following steps can be used.

(1) Perform data calculation in the depth calculation unit 100 according to instructions, and notify the central processing unit 101 that the data to be transmitted is ready. The data to be transmitted can be transmitted from the depth calculation unit 100 to the memory or other peripherals, or from the memory or Other peripherals are transmitted to the depth calculation unit 100 .

(2) The central processing unit 101 sends a DMA transfer access request through the application program interface (API) of the operating system according to the instruction of the application program currently running in the system. For example, the DMA transfer access request will be written into the running queue of the operating system.

(3) The run queue will write the DMA transfer access request and other requests generated during the running of the current program into the command buffer (command buffer) shared by the CPU/deep computing unit in the form of PM4 packets, for example.

(4) The command processing unit (command processor, CP) of the depth calculation unit 100 processes various packets buffered in the command buffer, thereby providing the DMA transfer access request to a DMA controller (DMA Engine).

(5) The DMA controller performs data transmission, and directly transmits the data to be transmitted from the source address to the destination address. After the DMA controller completes the data transfer, it notifies the CPU that the data transfer is complete.

The above steps (2)-(3) actually still involve the work that the CPU needs to do to a certain extent. In the case of a large amount of data transfer operations, the above steps are iterated multiple times. At this time, these steps (2)-(3) will have adverse effects on system performance.

At least one embodiment of the present disclosure provides a data processing device, which includes a calculation unit (Calculation Unit), a transmission access request buffer (Request Buffer), and a command processing unit (Command Processor). The computing unit is configured to generate a transfer access request in response to data to be transferred. The transport access buffer is configured to cache transport access requests. The command processing unit is configured to: respond to the transmission access request cached in the transmission access buffer, and provide the transmission access request to the data transmission control device, whereby the data transmission control device transmits the data to be transmitted in response to the transmission access.

At least one embodiment of the present disclosure further provides a data processing system, which includes the above-mentioned data processing device and a data transmission control device, where the data transmission control device is configured to transmit data to be transmitted in response to a transmission access request.

At least one embodiment of the present disclosure also provides a data processing method, the method including: generating a transmission access request in response to the data to be transmitted; caching the transmission access request; responding to the cached transmission access request, providing the transmission access request to the data transmission control device; causing the data transmission control device to respond to the transmission access request to transmit the data to be transmitted.

Through the data processing device, system and method of the above-mentioned embodiments of the present disclosure, when applied in a DMA mode, the CPU overhead can be further reduced, the effective bandwidth of the DMA operation can be increased, and the overall performance of the system can be improved.

The data processing device in the embodiment of the present disclosure may be, for example, a depth calculation unit, for example, the depth calculation unit may be embodied as an image processor (GPU), a tensor processing unit (TPU), a neural processing unit (NPU), etc., the present disclosure The embodiment does not limit this, and it can be realized by an integrated circuit or the like.

Fig. 2 shows a schematic diagram of a data processing device according to an embodiment of the present disclosure; Fig. 3 shows a schematic diagram of a data processing system according to an embodiment of the present disclosure, the data processing system includes, for example, the data processing device shown in Fig. 2 . For example, the data processing device is, for example, a deep calculation unit, and the data processing system is, for example, a computer system. In this system, the data processing device is a peripheral (Device) side relative to the CPU, and correspondingly, the CPU or memory is used as a host (Host) )side.

As shown in FIG. 2 , the data processing device 200 includes a command processing unit 211 , a command buffer 212 , a transmission access request buffer 213 , one or more computing units 230 , and the like. For example, the data processing device 200 may further include a storage device (not shown), such as a high bandwidth memory (HBM). For example, the storage device of the data processing device 200 may be accessed by devices other than the data processing device 200, such as a CPU or another data processing device.

FIG. 2 specifically shows two calculation units 230 as an example, while other possible calculation units are omitted. Each computing unit 230 includes a warp scheduling/distributing module, multiple computing cores (Kernels), a register file, a shared L1 cache, and the like. In order to schedule threads executing computing tasks among multiple computing units 230 , the data processing device 200 further includes a thread block scheduling unit 221 .

The data processing device can be used for calculation tasks such as matrix calculation and image rendering, and these calculation tasks can be executed in parallel through multiple threads. For example, before execution, these threads are divided into multiple thread blocks (thread blocks) in the thread block scheduling unit 221, and then these thread blocks are distributed to various computing units. All threads in a thread block are usually assigned to the same computing unit for execution. At the same time, the thread block will be split into thread warps (or thread warps for short), for example, each thread warp includes a fixed number (or less than the fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computing unit, or in different computing units.

In each computing unit, the warp scheduling/distributing module schedules and distributes the warps, so that multiple computing cores of the computing unit 230 run corresponding warps. Each computing core includes an arithmetic logic unit (ALU), a floating-point computing unit, and the like. Depending on the number of computing cores in a computing unit, multiple warps in a thread block can execute concurrently or time-sharingly. Multiple threads in each warp execute the same instruction. For example, the fetching, decoding, and issuing of instructions are all done in the warp scheduling/dispatching module. The memory execution instruction will be sent to the shared cache in the computing unit (for example, the shared L1 cache) or further sent to the unified cache for read and write operations, etc.

During the execution of the calculation task, the calculation unit 230 needs to obtain input data to be processed, and also generate result data, which can be stored in a storage device (such as HBM) of the data processing device 200 , for example. These input data or result data can be transmitted (input or output) by means of DMA, in this case the calculation unit 230 will generate a transmission access request for DMA. The transmission access request buffer 213 is used for buffering the above-mentioned transmission access requests. The computing unit 230 caches (submits) the transmission access request to the transmission access request buffer 213 for cache. For example, after the computing unit 230 generates the transmission access request, it notifies the central processing unit outside the data processing device 200, for example, through the bus.

The transmission access request buffer 213 may include multiple entries according to its own capacity, thereby storing multiple transmission access requests. For example, the transmit access request buffer 213 may be a first-in-first-out (FIFO) queue, whereby transmit access requests generated earlier can be processed first. For example, when the transmission access request buffer 213 is not full, it may receive and buffer new transmission access requests until it reaches the full state.

For example, after the calculation unit 230 generates the transmission access request, it inquires whether the transmission access request buffer 213 is full, and if the transmission access request buffer 213 is not full, writes the transmission access request into the transmission access request buffer 213, otherwise, for example, performs Wait, or discard the current transport access request.

For example, the transfer access request may include a transfer source address, a transfer destination address, and a transfer data size. The transmission source address and the transmission destination address can be the storage addresses of the storage devices in the data processing device 200 according to specific requirements, or can be the storage addresses of the system memory, or other peripherals in the computer system (such as another data processing device) The storage address and the like within are not limited by the embodiments of the present disclosure. According to the specific situation, for example, the transmission access request for the following four situations can be obtained: Peripheral to Memory (Device to Host, D2H), Memory to Peripheral (H2D), Memory to Memory (H2H), Peripheral to Peripheral (D2D). The transfer data size refers to the length of continuous transfer data when performing DMA, which may be equal to the bandwidth of the system bus (for example, 64 bits or 128 bits, etc.).

When the transmission access request cache is behind the transmission access request buffer 213, the transmission access request buffer 213 can also further record the status of each transmission access request in addition to recording the transmission source address, transmission destination address and transmission data size, for example, the status Can include: pending transfer, transfer in progress, transfer complete, or transfer failed. For example, these status information can be accessed and even modified by the command processing unit 211 or other devices that can access the transmission access request buffer 213 (such as CPU or data transmission control device). The transport access request can also include other statuses as needed.

For example, in at least one example, the command processing unit 211 may inquire whether the transmission access request buffer 213 has at least one transmission access request to be processed, and if there is a transmission access request to be processed, then submit the transmission access request to the data transmission control device (such as a DMA controller), or submit these transmission access requests to the data transmission control device in sequence, so that the data transmission control device can perform data transmission operations. The data transmission control device processes according to the specific transmission access request.

For example, after a transmission access request is processed, for example, if it is determined that the transmission is completed or fails, the transmission access request may be deleted from the transmission access request buffer 213 . This operation, for example, can be performed by the command processing unit 211, that is, query whether there is a transmission access request to be processed in the transmission access request buffer 213, obtain the status of the transmission access request still cached in the transmission access request buffer 213, and determine a certain transmission access request When the corresponding data transmission is completed or the transmission fails, the transmission access request may be deleted from the transmission access request buffer 213 .

In the embodiment of the present disclosure, the command buffer 212 in the data processing device 200 is used to cache instructions or requests from devices such as the CPU or the data processing device 200 itself, and these instructions or requests are, for example, in the form of packets (such as PM4 packets) is cached. The command buffer 212 may include multiple entries according to its own capacity, thereby saving multiple packets. Correspondingly, the command processing unit 211 is also configured to execute instructions or requests cached in the command buffer 212 , and may also communicate and interact with devices such as a CPU, for example. For example, the command buffer 212 and the transfer access request buffer 213 can be set independently of each other in the data processing device 200, or share the same physical storage device, but are logically controlled and managed separately.

For example, in at least one example, the command processing unit 211 preferentially processes the cached operation instruction in the transmission access request buffer 213 under the condition that at least one operation instruction is cached in the command buffer 212 and at least one transmission access request is cached in the transmission access request buffer 213. At least one transfer access request. That is, when the command processing unit 211 faces a transmission access request that needs to be processed and other operation instructions that need to be processed, it first processes the transmission access request, and submits the transmission access request to the data transmission control device.

Specifically, in one example, for example, after processing each operation instruction in the command buffer, the command processing unit 211 queries whether there is at least one transmission access request cached in the transmission access request buffer 213, and in the transmission access request buffer 213 When there is at least one transmission access request cached, after processing the pending transmission access requests cached in the transmission access request buffer 213 , it returns to process other operation instructions in the command buffer 212 . For example, after the command processing unit 211 provides all the transmission access requests in the transmission access request buffer 213 to the data transmission control device, it returns to the position where it left the command buffer 212 to continue processing the operation instructions in the command buffer 212 .

For example, in one example, the command processing unit 211 also performs subsequent processing on the transmission access request still buffered in the transmission access request buffer 213 in response to a message about a state change (for example, data transmission completion) of a certain transmission access request , for example, modify its status information, or delete it, etc.

The computer system shown in FIG. 3 includes a central processing unit (CPU) 201 , one or more data processing devices 200 , a storage device 202 , a data transmission control device 203 and a bus 204 . The data processing device 200 is the data processing device shown in FIG. 2 , and two data processing devices 200 are shown in the figure as an example. The two data processing devices 200 are respectively data processing device 200-1 and data processing device 200-2. The control unit performs data transmission.

In the embodiment of the present disclosure, the central processing unit 201 may be, for example, a single-core processor or a multi-core processor, may be a RISC or CISC processor, etc., for example may be an ARM processor, a RISC-V processor, etc., the present disclosure The embodiment does not limit this. The data transmission control device 203 is, for example, a DMA controller, which is provided separately or integrated in, for example, the central processing unit 201 . The storage device 202 may be a system memory or an external storage (such as a hard disk) of a computer system, for example, a semiconductor storage device, etc. Embodiments of the present disclosure do not limit the type and structure of the storage device.

The central processing unit 201 , the data processing device 200 , the storage device 202 , and the DMA controller 203 communicate with each other through the bus 204 . Embodiments of the present disclosure do not limit the type of the bus, for example, various applicable buses, such as a PCIE bus.

For example, after receiving the notification about the transmission access request, the central processing unit 201 continuously checks the completion status of the transmission access request, and notifies, for example, the application program after determining that the transmission access request is completed.

For example, the data transmission control device 203 performs a data transmission operation from the transmission source address to the transmission destination address according to the transmission access request, during the data transmission process, after the data transmission is completed, or after multiple attempts to perform data transmission and still fail Afterwards, the state of the corresponding transmission access request may be further updated, for example, a message about state change is provided to update the state of the corresponding transmission access request stored in the transmission access request buffer 213 of the data processing apparatus 200 .

An exemplary working process of a data processing device and a data processing system according to at least one embodiment of the present disclosure will be described below with reference to FIG. 2 and FIG. 3 .

During the working process, the CPU 201 sends computing tasks to one or more of the data processing devices 200 for processing according to the currently running application programs.

For example, for the data processing device 200-1 therein, during the execution of the calculation task, the calculation unit 230, for example, performs calculations according to instructions and generates a transmission access request (referred to as "the first transmission access request" herein), and then Calculation unit 230 inquires whether the transmission access request buffer 213 is full, if the transmission access request buffer 213 is not full, then writes the first transmission access request to the transmission access request buffer 213 to be processed, and the first transmission access request The status is marked as "not transferred". The first transmission access request records the corresponding transmission source address, transmission destination address and transmission data size; at the same time, the calculation unit 230 also notifies the CPU 201 that the first transmission access request is generated. After receiving the notification, the CPU 201 continuously monitors the completion status of the first transfer access request.

While the calculation unit 230 is executing the calculation task, the command processing unit 211 in the data processing device 200 is processing a plurality of operation instructions cached in the command buffer 212; Whether the request buffer 213 currently has pending transmission access requests. After the first transmission access request has been written into the transmission access request buffer 213, the command processing unit 211 accesses the first transmission access request and learns that its status is "to be transmitted", and the first transmission access request is larger than the command buffer 212. The operation instruction in has a higher priority, so the command processing unit 211 transfers to process the first transmission access request, and sends the first transmission access request to the data transmission control device 203 . Afterwards, if there are other transmission access requests in the transmission access request buffer 213, the command processing unit 211 continues to process these pending transmission access requests until all pending transmission access requests are successfully sent to the data transmission control device 203, and then , the command processing unit 211 returns to the command buffer 212, and continues to process other pending operation commands in the command buffer 212 from the position of the previously processed operation command P1.

The data transmission control device 203 performs the corresponding data transmission operation according to the transmission source address, transmission destination address and transmission data size recorded in the first transmission access request, and notifies the command processing unit 211 of the data processing device 200-1 of the first transmission The status of the access request is modified to "in transmission"; and, after the data transmission operation is completed, the data transmission control device 203 notifies the command processing unit 211 of the data processing device 200-1, and the command processing unit 211 is in the transmission access request buffer 213 Modify the status of the first transmission access request to "transmission complete", and delete the completed first transmission access request from the transmission access request buffer 213 after a predetermined time or triggered by other operations. In addition, the data transmission control device 203 can also notify the CPU 201 that the first transmission access request has been completed, so that the CPU 201 can feed back the information to the upper-layer application program.

In the above process, the data processing apparatus 200 actively initiates a transmission access request, thereby reducing system overhead and improving system performance compared with initiating a transmission access request through the CPU.

Corresponding to the above device and system, an embodiment of the present disclosure also provides a data processing method. As shown in Figure 4, the data processing method includes the following steps 301-304:

Step 301: Generate a transfer access request in response to the data to be transferred.

Step 302: Cache and transmit the access request.

Step 303: In response to the buffered transmission access request, provide the transmission access request to the data transmission control device.

Step 304: Make the data transmission control device respond to the transmission access request to transmit the data to be transmitted.

For example, the computing unit performs calculations to determine the data that needs to be transmitted, and generates a transmission access request in response to the data that needs to be transmitted. Cache transfer access requests by transfer access request buffering. The transmission access request is provided to the data transmission control means by the command processing unit in response to the transmission access request buffered in the transmission access request buffer. The data to be transmitted is transmitted by the data transmission control device in response to the transmission access request.

For example, the data processing method according to at least one embodiment of the present disclosure further includes: caching operation instructions; enabling the command processing unit that executes the operation instructions and transmits access requests to process the transmission access requests preferentially.

For other possible operation steps or selections of the method, reference may be made to the operations described above in conjunction with FIG. 2 and FIG. 3 , which will not be repeated here.

In the data processing method of this embodiment, for example, a data processing device can initiate a transmission access request, thereby reducing system overhead and improving system performance.

For this disclosure, the following points need to be explained:

(1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above descriptions are only exemplary implementations of the present disclosure, and are not intended to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims (15)

1. A data processing device, comprising: a computing unit configured to generate a transfer access request in response to data to be transferred; a transmission access request buffer configured to cache the transmission access request; a command processing unit configured to: in response to the transmission access request buffered in the transmission access request buffer, provide the transmission access request to a data transmission control device, whereby the data transmission control device responds to the The transfer access request directly transfers the data to be transferred from the source address to the destination address in a direct memory access manner. 2. The data processing device according to claim 1, wherein the calculation unit is further configured to notify a central processing unit external to the data processing device after generating the transmission access request. 3. The data processing device according to claim 1, wherein the calculation unit is further configured to, after generating the transmission access request, query whether the transmission access request buffer is full, and respond to the transmission access request If the buffer is not full, write the transmission access request into the transmission access request buffer. 4. The data processing apparatus according to any one of claims 1-3, wherein the transmission access request includes: a transmission source address, a transmission destination address and a transmission data size. 5. A data processing apparatus according to claim 4, wherein said transfer access request further comprises a transfer status, The transmission status includes pending transmission, transmission in progress, transmission complete or transmission failure. 6. The data processing device according to any one of claims 1-3, further comprising: a command buffer configured to buffer operation instructions for the command processing unit; Wherein, the command processing unit is further configured to: when at least one operation instruction is cached in the command buffer and at least one transmission access request is cached in the transmission access request buffer, the cached operation instruction in the transmission access request buffer is preferentially processed. The at least one transport access request for . 7. The data processing device according to claim 1, wherein the command processing unit is further configured to: after processing each operation instruction in the command buffer, query whether there is at least one cached in the transfer access request buffer The transmission access request, in response to the pending transmission access request buffered in the transmission access request buffer, after processing the at least one transmission access request buffered in the transmission access request buffer, return to process the command buffer other operating instructions. 8. The data processing apparatus according to claim 1, wherein said transmission access request buffer is a first-in first-out buffer. 9. The data processing apparatus according to claim 1, wherein said command processing unit is further configured to provide said transmission access request to said data transmission control means outside said data processing apparatus. 10. A data processing system comprising: The data processing device according to any one of claims 1, 3-9; The data transmission control device is configured to transmit the data to be transmitted in response to the transmission access request. 11. The data processing system according to claim 10, further comprising a central processing unit, wherein said computing unit is further configured to notify said central processing unit after generating said transmission access request. 12. The data processing system according to claim 11, wherein the central processing unit is configured to continuously check the completion status of the transfer access request after receiving the notification about the transfer access request. 13. A data processing system according to any one of claims 10-12, wherein said data transfer control means comprises direct memory access means. 14. A data processing method comprising: Generate transfer access requests in response to data that needs to be transferred; caching said transmission access request; providing said transmission access request to a data transmission control device in response to said cached transmission access request; The data transmission control device directly transmits the data to be transmitted from the source address to the destination address in a direct memory access manner in response to the transmission access request. 15. The data processing method according to claim 14, further comprising: Cache operation instructions; Making the command processing unit that executes the operation instruction and the transmission access request preferentially process the transmission access request.

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