CN114116359B - PCIe chip signal testing device and method - Google Patents

Abstract

The invention relates to the field of server technology, and specifically provides a PCIe chip signal testing device and method, which includes: a first PCIe chip and a second PCIe chip. The clock signal line of the first PCIe chip is connected to a consistency testing fixture to connect the first PCIe chip The clock signal of the chip is synchronized to the clock module of the consistency test fixture; the consistency test fixture is connected to the receiving port of the second PCIe chip, and sends a test signal of specified duration to the second PCIe chip based on the clock signal of the clock module to The second PCIe chip is caused to upgrade preconfigured parameters based on the test signal. By reusing the consistency test fixture, the present invention achieves the effect of providing test signals for the PCIe chip to be tested. There is no need to design an additional hardware structure on the test board to provide test signals for the PCIe chip to be tested, thereby improving the usability of the entire test system. .

Description

A PCIe chip signal testing device and method

Technical field

The invention belongs to the field of server technology, and specifically relates to a PCIe chip signal testing device and method.

Background technique

During the PCIe signal TX test, when the PCIe controller is in the polling.compliance state machine, the chip TX automatically upgrades the test configuration (preset value) by sending a 100MHZ and >1ms signal to the chip RX. After the test is completed, the 100MHz signal is re-sent to continue the upgrade. Test configuration parameters. Repeat the previous test for all chip preset configuration parameters.

In the existing PCIe chip testing process, there are two main methods. The first is to directly design the device on the development board to provide the 100M signal for the chip RX. The second is to directly control the TX switching output signal preset through internal commands of the chip.

The first design method increases the difficulty of board design and requires additional components. There is a certain risk in whether the added components meet the requirements of the PCIe Association. The second method requires support from the chip's internal logic control unit, and some PCIe chips cannot support it.

Contents of the invention

In view of the above-mentioned deficiencies in the prior art, the present invention provides a PCIe chip signal testing device and method to solve the above-mentioned technical problems.

The invention provides a PCIe chip signal testing device, which includes: a first PCIe chip and a second PCIe chip. The clock signal line of the first PCIe chip is connected to a consistency testing fixture to synchronize the clock signal of the first PCIe chip to consistency. The clock module of the test fixture; the consistency test fixture is connected to the receiving port of the second PCIe chip, and sends a test signal of specified duration to the second PCIe chip based on the clock signal of the clock module, so that the second PCIe chip is based on The test signal upgrades preconfigured parameters.

Further, the first PCIe chip and the second PCIe chip are both arranged on the PCIe board card.

Further, the clock signal line of the first PCIe chip is connected to a standard PCIe port, and the standard PCIe port is connected to the conformance test fixture.

Further, the first PCIe chip is connected to multiple standard PCIe ports for testing complete functions through a clock divider.

Further, the conformance test fixture includes a clock module, a radio frequency connector and a controller. The clock module and the radio frequency connector are both connected to the controller; the radio frequency connector is connected to the SMA connector of the receiving port of the second PCIe chip. ; Based on the clock signal of the clock module, the controller controls the radio frequency connector to send a test signal to the SMA connector according to the preset duration.

Further, the radio frequency connector is connected to the SMA connector through a radio frequency to microwave connection cable.

Further, the input pin of the controller is connected to a control button, and the control button sends a potential signal to the controller, so that the controller controls the radio frequency connector to send a test signal.

Further, the sending port of the second PCIe chip is connected to an oscilloscope or bit error meter through an SMA connector.

The invention also provides a PCIe chip signal testing method, which includes:

Receive the clock signal sent by the first PCIe chip, and correct the clock module according to the clock signal;

Receive the level signal generated by the control button, and read the locally stored duration according to the level signal;

A control instruction is sent to the radio frequency connector, where the control instruction includes a signal frequency and a duration, so that the radio frequency connector sends a test signal that conforms to the signal frequency and duration to the receiving port of the second PCIe chip.

Further, the method also includes:

The SMA connector of the receiving port of the second PCIe chip receives the test signal sent by the RF connector through the RF to microwave connection cable;

The port physical layer of the second PCIe chip enters the test state based on the short-circuit resistance guidance signal of the oscilloscope, and the oscilloscope is connected to the SMA connector of the transmit port of the second PCIe chip;

In the test state, the preconfigured parameters of the sending port are automatically updated according to the test signal received by the receiving port.

The beneficial effect of the present invention is that the PCIe chip signal testing device and method provided by the present invention achieve the effect of providing test signals for the PCIe chip to be tested by multiplexing the consistency test fixture, without the need for additional design on the test board. The test PCIe chip provides the hardware structure of the test signal, which improves the usability of the entire test system.

In addition, the design principle of the invention is reliable, the structure is simple, and it has very broad application prospects.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can also be obtained based on these drawings without exerting creative work.

Figure 1 is a schematic structural diagram of a device according to an embodiment of the present application.

Figure 2 is an exemplary flow chart of a method according to an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of the present invention.

It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. . Thus, features defined by "first," "second," etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise stated, "plurality" means two or more.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

Please refer to Figure 1. An embodiment of the present invention provides a PCIe chip signal testing device, which includes:

The first PCIe chip and the second PCIe chip. The clock signal line of the first PCIe chip is connected to the conformance test fixture to synchronize the clock signal of the first PCIe chip to the clock module of the conformance test fixture; the conformance test fixture is connected to the second PCIe chip. The receiving port of the PCIe chip sends a test signal of specified duration to the second PCIe chip based on the clock signal of the clock module, so that the second PCIe chip upgrades the preconfigured parameters based on the test signal.

The first PCIe chip and the second PCIe chip are both arranged on the PCIe board card. A development board designed based on PCIe SW chip. The first PCIe chip (SW_A) is used to test the complete function and connect to external PCIe slots, etc., which can expand the actual PCIe function. The second PCIe chip (SW_B) is only used to test the TX/RXSI performance and parameters of the PCIe SW chip to complete the PCIesignal compliance test.

Among them, the clock signal line of the first PCIe chip is connected to a standard PCIe port, and the standard PCIe port is connected to a compliance test fixture (CLBCard). The first PCIe chip connects multiple standard PCIe ports for testing complete functionality through a clock divider (CLK Buffer). In addition to the standard PCIe ports connected to the compliance test fixture, other standard PCIe ports are used to connect other test fixtures to test various functions of the first PCIe chip.

The conformance test fixture includes a clock module (CLK), a radio frequency connector (TP1SMP) and a controller (SW). The clock module and the radio frequency connector are both connected to the controller; the radio frequency connector is connected to the receive port (RX) of the second PCIe chip. SMA connector (SMA connector is a widely used small threaded coaxial connector. It has the characteristics of wide frequency band, excellent performance, high reliability and long life. SMA connector is suitable for microwave equipment and digital communication systems. Connect RF cables or microstrip lines to the RF loop.); Based on the clock signal of the clock module, the controller controls the RF connector to send a test signal to the SMA connector according to the preset duration. In this embodiment, the test signal has a duration greater than 1ms of 100MHz signal. The RF connector is connected to the SMA connector through a RF to microwave connection cable (SMP To SMA Cable). The input pin of the controller is connected to a control button, and the control button sends a potential signal to the controller, so that the controller controls the RF connector to send a test signal; that is, pressing the control button sends a test signal, and each press sends the test signal once. In other embodiments of the present invention, there is no need to control the button, and the cycle of sending signals can be set in the controller, for example, a test signal is sent every 15 seconds. In addition, the transmit port (TX) of the second PCIe chip is connected to an oscilloscope or bit error meter through an SMA connector.

When performing the test, connect SW_B TX SMA to the oscilloscope. The oscilloscope automatically guides the PHY (port physical layer) of SW_B to enter the polling.complaince PCIe signal test state machine through the short-circuit resistor. By pressing the button on the CLB, the signal can be provided for SW_BRX , RX automatically upgrades the PCIe TX preset after receiving the signal, realizing switching and testing of different PCIe TXPreset settings.

Please refer to Figure 2. Another embodiment of the present invention provides a PCIe chip signal testing method.

The controller of the conformance test fixture performs the following steps:

S1. Receive the clock signal sent by the first PCIe chip, and correct the clock module according to the clock signal;

S2. Receive the level signal generated by the control button, and read the locally stored duration according to the level signal;

S3. Send a control instruction to the radio frequency connector, where the control instruction includes signal frequency and duration, so that the radio frequency connector sends a test signal that conforms to the signal frequency and duration to the receiving port of the second PCIe chip.

Based on the test signal, the test steps of the second PCIe chip are as follows:

S1. The port physical layer of the second PCIe chip enters the test state based on the short-circuit resistance guidance signal of the oscilloscope, and the oscilloscope is connected to the SMA connector of the transmission port of the second PCIe chip;

S2. The SMA connector of the receiving port of the second PCIe chip receives the test signal sent by the RF connector through the RF to microwave connection cable;

S3. In the test state, the preconfigured parameters of the sending port are automatically upgraded according to the test signal received by the receiving port.

In the present invention, two identical PCIe chips are installed on a development board, one chip is used for testing functions and the other chip is used for testing signals. By connecting the chip with the test function to the PCIe standard CLB fixture, the board-level design is reduced, and there is no need to design a solution to provide the chip with a 100MHZ signal on the test board. By reusing fixtures, the availability of the entire system is improved.

Although the present invention has been described in detail with reference to the accompanying drawings in conjunction with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the invention, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the invention, and these modifications or substitutions should be within the scope of the invention/any Those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention, and they should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (7)

1. A PCIe chip signal testing device, characterized in that it includes: a first PCIe chip and a second PCIe chip, the clock signal line of the first PCIe chip is connected to a consistency test fixture to synchronize the clock signal of the first PCIe chip to the clock module of the conformance test fixture; the conformance test fixture is connected to the receiving port of the second PCIe chip, and sends a test signal of specified duration to the second PCIe chip based on the clock signal of the clock module, so that the second PCIe chip The PCIe chip upgrades preconfigured parameters based on the test signal; the conformance test fixture includes a clock module, a radio frequency connector and a controller, the clock module and the radio frequency connector are both connected to the controller; the radio frequency connector is connected to the second The SMA connector of the receiving port of the PCIe chip; based on the clock signal of the clock module, the controller controls the radio frequency connector to send a test signal to the SMA connector according to the preset duration; the input pin of the controller is connected A control button sends a potential signal to the controller, so that the controller controls the radio frequency connector to send a test signal. 2. The device according to claim 1, wherein the first PCIe chip and the second PCIe chip are both disposed on the PCIe card. 3. The device according to claim 1, wherein the clock signal line of the first PCIe chip is connected to a standard PCIe port, and the standard PCIe port is connected to a conformance test fixture. 4. The device according to claim 3, wherein the first PCIe chip is connected to a plurality of standard PCIe ports for testing complete functions through a clock divider. 5. The device according to claim 1, wherein the radio frequency connector is connected to the SMA connector through a radio frequency to microwave connection cable. 6. The device according to claim 1, wherein the sending port of the second PCIe chip is connected to an oscilloscope or a bit error meter through an SMA connector. 7. A PCIe chip signal testing method, characterized by including: The conformance test fixture receives the clock signal sent by the first PCIe chip and corrects the clock module according to the clock signal; the conformance test fixture includes a clock module, a radio frequency connector and a controller, and the clock module and the radio frequency connector are connected to all The controller; the RF connector is connected to the SMA connector of the receiving port of the second PCIe chip; the controller is based on the clock signal of the clock module and controls the RF connector to send data to the SMA connector according to a preset duration. Test signal; the controller receives the level signal generated by the control button, and reads the duration of local storage according to the level signal; the controller sends a control instruction to the radio frequency connector, the control instruction includes the signal frequency and The duration is such that the radio frequency connector sends a test signal that conforms to the signal frequency and duration to the receiving port of the second PCIe chip.