CN114115415B - Low dropout linear voltage stabilizing circuit - Google Patents
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- CN114115415B CN114115415B CN202111317312.1A CN202111317312A CN114115415B CN 114115415 B CN114115415 B CN 114115415B CN 202111317312 A CN202111317312 A CN 202111317312A CN 114115415 B CN114115415 B CN 114115415B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The embodiment of the invention discloses a low dropout linear voltage stabilizing circuit. The low dropout linear voltage stabilizing circuit comprises an amplifying unit, an output unit, a feedback unit and a reference voltage generating unit; the amplifying unit comprises a first input end, a second input end and an output end; the first input end of the amplifying unit is connected with the output end of the reference voltage generating unit, the second input end of the amplifying unit is connected with the output end of the feedback unit, the input end of the feedback unit is connected with the output end of the output unit, and the input end of the output unit is connected with the output end of the amplifying unit; the reference voltage generating unit includes a first current source, a second current source, a first transistor, and at least two second and third transistors. Compared with the prior art, the technical scheme of the embodiment of the invention has the advantages of simple circuit structure, small circuit consumption area, little influence of temperature and process angle on the reference voltage, and capability of adjusting the temperature characteristic according to requirements.
Description
Technical Field
The embodiment of the invention relates to the technical field of voltage regulators, in particular to a low dropout linear voltage regulator circuit.
Background
The low dropout linear voltage regulator circuit has the advantages of small area, low power consumption, simple scheme and the like, and is widely applied to electronic systems. When the low dropout linear voltage regulator circuit is designed, in order to further reduce current and remove voltage division feedback, a load is directly used as a feedback branch circuit, and in order to realize the method, the reference voltage of the circuit needs to reach an output value.
In the prior art, reference current is loaded on two NMOS tubes connected by diodes, and the generated reference voltage is 2Vthn, so that the defect that the reference voltage is greatly influenced by a process angle and temperature due to the superposition of two threshold values is overcome; the second method is to load a reference current on a resistor, and has the disadvantages that a 72M resistor is needed to realize 0.72V under the condition of a small current of 10nA, the circuit structure is complex, and the consumed area is very large.
Disclosure of Invention
The invention provides a low dropout linear voltage stabilizing circuit, which aims to realize that the reference voltage meets the requirement and the temperature characteristic can be adjusted to be positive temperature, negative temperature or zero temperature according to the requirement.
The embodiment of the invention provides a low dropout linear voltage stabilizing circuit, which comprises an amplifying unit, an output unit, a feedback unit and a reference voltage generating unit;
the amplifying unit comprises a first input end, a second input end and an output end; a first input end of the amplifying unit is connected with an output end of the reference voltage generating unit, a second input end of the amplifying unit is connected with an output end of the feedback unit, an input end of the feedback unit is connected with an output end of the output unit, and an input end of the output unit is connected with an output end of the amplifying unit;
the reference voltage generating unit includes a first current source, a second current source, a first transistor, and at least two second and third transistors; the first current source is connected between a first power supply and a first pole of the first transistor, and at least two second transistors are sequentially connected in series and connected between a second pole of the first transistor and a second power supply; the first pole of the first second transistor is connected with the second pole of the first transistor, the second pole of the last second transistor is connected with the second power supply, and the grid electrode of the first transistor and the grid electrode of each second transistor are connected with the first pole of the first transistor; the substrate of the first transistor and the substrate of each second transistor are connected with the second pole of the last second transistor;
the second current source is connected between a first pole of the third transistor and the first power supply, a gate and a second pole of the third transistor are both connected to a second pole of the first transistor, and the first pole of the third transistor is used as an output end of the reference voltage generation unit.
Optionally, the reference voltage generating unit includes three of the second transistors;
a first electrode and a grid electrode of the first transistor are connected with a first end of the first current source, and a second end of the first current source is connected with the first power supply;
the first pole of the first second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the first pole of the second transistor, and the second pole of the second transistor is connected with the second power supply.
Optionally, the first transistor and the second transistor are N-type transistors, and the third transistor is a P-type transistor.
Optionally, the sizes of the second transistors are the same or different.
Optionally, the voltage of the second pole of the first transistor is independent of a process corner and is a positive temperature coefficient voltage.
Optionally, the amplifying unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a third current source;
the fourth transistor is connected with the grid electrode of the fifth transistor and is used as a first input end of the amplifying unit; a first pole of the fourth transistor is connected with a second pole of the fifth transistor, and a second pole of the fourth transistor is connected with a second pole of the eighth transistor and serves as an output end of the amplifying unit; a first electrode of the fifth transistor is connected with a first end of the third current source;
the sixth transistor is connected with the gate of the seventh transistor and serves as a second input end of the amplifying unit; a first pole of the sixth transistor is connected to the second pole of the seventh transistor, a second pole of the sixth transistor is connected to the second pole of the ninth transistor, and a first pole of the seventh transistor is connected to the first terminal of the third current source;
a gate of the eighth transistor is connected to a gate of the ninth transistor and a second pole of the ninth transistor, and a first pole of the eighth transistor and a first pole of the ninth transistor are connected to the first power supply; a second terminal of the third current source is connected to the second power supply.
Optionally, the current of the third current source is greater than 3 times the current of the first current source and the current of the second current source.
Optionally, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are N-type transistors;
the eighth transistor and the ninth transistor are P-type transistors.
Optionally, the feedback unit includes a capacitor, a first pole of the capacitor is connected to a second pole of the fourth transistor, and the second pole of the capacitor is connected to the output end of the low dropout linear voltage regulator circuit and the gate of the sixth transistor.
Optionally, the output unit comprises a tenth transistor; a first pole of the tenth transistor is connected to the first power supply, a gate of the tenth transistor is connected to the output terminal of the amplifying unit, and a second pole of the tenth transistor is connected to the output terminal of the low dropout linear voltage regulator circuit.
In the prior art, reference current is loaded on two NMOS tubes connected by diodes to generate reference voltage, and the two thresholds are superposed to enable the reference voltage to be greatly influenced by a process angle and temperature; the reference current is loaded on the resistor, and 72M of resistor is needed to realize 0.72V under the condition of 10nA of small current, so that the circuit area is very large. According to the technical scheme of the embodiment, the voltage with the threshold value eliminated can be obtained by subtracting the whole voltage of the reference voltage generating unit from the voltage of the first transistor, the voltage is irrelevant to a process corner and is at a positive temperature, and then the voltage is superposed with the threshold voltage of the third transistor to obtain the reference voltage output by the low-dropout linear voltage regulator circuit. The technical scheme of this embodiment has solved two threshold voltage superposes and has made reference voltage receive the problem that technology angle and temperature influence, and the circuit of this embodiment need not to use resistance, has solved and has realized that low-voltage needs big resistance to lead to the big problem of circuit area, and the circuit structure of this embodiment is simple, and area consumption is little, and reference voltage receives temperature and technology angle influence very little, and its temperature characteristic can be adjusted according to the demand.
Drawings
FIG. 1 is a block diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a structure of another low dropout linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a structure of another low dropout linear voltage regulator circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a block diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present invention. Referring to fig. 1-2, the low dropout linear voltage regulator circuit includes an amplifying unit 103, an output unit 104, a feedback unit 102, and a reference voltage generating unit 101;
the amplifying unit 103 includes a first input terminal FA, a second input terminal FB, and an output terminal VOUT; a first input terminal FA of the amplifying unit 103 is connected with the output terminal of the reference voltage generating unit 101, a second input terminal FB of the amplifying unit 103 is connected with the output terminal FB of the feedback unit 102, an input terminal FC of the feedback unit 102 is connected with the output terminal of the output unit 104, and an input terminal of the output unit 104 is connected with the output terminal VOUT of the amplifying unit 103;
the reference voltage generating unit 101 includes a first current source IREF3, a second current source IREF2, a first transistor NM1, and at least two second and third transistors PM1; a first current source IREF3 connected between a first power source VDD and a first pole of the first transistor NM1, at least two second transistors connected in series in sequence and connected between a second pole of the first transistor NM1 and a second power source VSS; a first pole of the first second transistor NM2 is connected to a second pole of the first transistor NM1, a second pole of the last second transistor NM4 is connected to the second power source VSS, and a gate of the first transistor NM1 and gates of the second transistors are connected to the first pole of the first transistor NM 1; the substrate of the first transistor NM1 and the substrates of the second transistors are connected to the second pole of the last second transistor NM 4;
the second current source IREF2 is connected between the first pole of the third transistor PM1 and the first power source VDD, the gate and the second pole of the third transistor PM1 are both connected to the second pole of the first transistor NM1, and the first pole of the third transistor PM1 is used as the output terminal of the reference voltage generating unit 101.
Specifically, when the low dropout linear voltage regulator circuit operates, the voltage of the first pole of the first transistor NM1 is VG, the voltage of the second pole of the last second transistor NM4 is VSS, and the voltage VGs minus VSS is the overall voltage VGs0 of the reference voltage generating unit 101, that is, VGs0= VG-VSS. Since the first pole of the first second transistor NM2 is connected to the second pole of the first transistor NM1 and is equipotential, the voltage of the second pole of the first transistor NM1 is VB, and the voltage VGs1 of the first transistor NM1, i.e., VGs1= VG-VB, is obtained by subtracting VB from VG. The difference between the voltage VGS0 and the voltage VGS1 is used to obtain the voltage VB of the second pole of the first transistor NM1 after the threshold is eliminated, that is, VB = (VGS 0-VGS 1) + VSS.
With continued reference to fig. 2, optionally, the voltage VB of the second pole of the first transistor NM1 is independent of the process corner and is a positive temperature coefficient voltage.
The process corner is that due to manufacturing process variations, characteristics of different transistors are different except for different threshold voltages, and other parameters are different, a voltage VB of the second pole of the first transistor NM1 is unrelated to the process corner, the voltage VB is a positive temperature coefficient voltage, and the higher the temperature, the higher the voltage, the lower the temperature, and the lower the voltage. The level value of the voltage VB is not changed in order to control the on-current of the third transistor PM1 to be not changed, thereby supplying a constant current to the amplifying unit 103.
Because the grid electrode and the second electrode of the third transistor PM1 are both connected with the second electrode of the first transistor NM1, the grid electrode and the second electrode of the third transistor PM1 are electrically connected, equivalently in a diode connection mode, the grid electrode voltage of the third transistor PM1 is equal to the voltage VB after the threshold value is eliminated, and the negative temperature voltage VTHP is obtained by subtracting the first electrode voltage VD from the grid electrode voltage VB of the third transistor PM1, wherein VB-VD = VTHP; and finally, superposing the VB voltage with the negative temperature voltage VTHP to obtain the reference voltage VREF output by the low-dropout linear voltage stabilizing circuit, wherein VREF = VD = VB-VTHP. The negative temperature voltage VTHP is a threshold voltage of the third transistor PM1, and the negative temperature voltage, i.e., the voltage decreases as the temperature increases. A positive, negative or zero temperature voltage may be obtained by adjusting the size of the third transistor PM 1.
It should be noted that the voltage of the first power supply VDD input may be a positive power supply voltage, and the voltage of the second power supply VSS input may be a negative power supply voltage.
In the prior art, reference current is loaded on two NMOS tubes connected by diodes to generate reference voltage, and the two thresholds are superposed to enable the reference voltage to be greatly influenced by a process angle and temperature; the reference current is loaded on the resistor, 72M of resistor is needed to realize 0.72V under the condition of 10nA of small current, and the circuit area is very large. According to the technical scheme of the embodiment, the voltage with the threshold value eliminated can be obtained by subtracting the whole voltage of the reference voltage generating unit from the voltage of the first transistor, the voltage is irrelevant to a process corner and is at a positive temperature, and then the voltage is superposed with the threshold voltage of the third transistor to obtain the reference voltage output by the low-dropout linear voltage regulator circuit. The technical scheme of this embodiment has solved two threshold voltage superposes and has made reference voltage receive the problem that technology angle and temperature influence, and the circuit of this embodiment need not to use resistance, has solved and has realized that low-voltage needs big resistance to lead to the big problem of circuit area, and the circuit structure of this embodiment is simple, and area consumption is little, and reference voltage receives temperature and technology angle influence very little, and its temperature characteristic can be adjusted according to the demand.
With continued reference to fig. 2, optionally, the reference voltage generating unit 101 comprises three second transistors;
a first pole and a gate of the first transistor NM1 are connected to a first terminal of a first current source IREF3, and a second terminal of the first current source IREF3 is connected to a first power supply VDD;
a first pole of the first second transistor NM2 is connected to a second pole of the first transistor NM1, a second pole of the latter second transistor NM3 is connected to a first pole of the former second transistor NM2, and a second pole of the last second transistor NM4 is connected to the second power source VSS.
The three second transistors of the reference voltage generating unit 101 have a voltage limiting function, and are used for limiting the output voltage of the output terminal of the low dropout linear voltage regulator circuit, so as to prevent the output voltage from being unstable due to an excessive voltage. Specifically, a first pole of the first second transistor NM2 is connected to a second pole of the first transistor NM1 as a first end of the voltage limiting unit, a second pole of the last second transistor NM4 is connected to a second end of the voltage limiting unit, gates of the three second transistors are electrically connected to each other, a substrate of each second transistor is connected to a second pole of the last second transistor NM4, each second transistor is equivalent to a diode, when the voltage of the output end of the low dropout linear voltage stabilizing circuit is too large, the transistors are turned on, so that the voltage output by the output end of the low dropout linear voltage stabilizing circuit flows to the second power supply VSS, the voltage output by the low dropout linear voltage stabilizing circuit is limited, and instability of the output voltage caused by the too large voltage is prevented. Wherein, the positive temperature coefficient can be adjusted according to NM3 and NM4 in series.
With continued reference to fig. 2, optionally, the first transistor NM1, the second transistors NM2 to NM4 are N-type transistors, and the third transistor PM1 is a P-type transistor.
The PMOS is used as an upper tube, and the NMOS is used as a lower tube, so that the device is convenient. The transconductance of a PMOS transistor is smaller than that of an N-channel MOS transistor. In addition, the absolute value of the threshold voltage of the PMOS transistor is generally high, and a high operating voltage is required. Therefore, the first transistor NM1 and the second transistors NM2 to NM4 may be N-type MOS transistors, and the third transistor PM1 may be a P-type MOS transistor.
Optionally, the sizes of the second transistors are the same or different.
The sizes of the second transistors are the same, so that the process difficulty can be reduced, and the two same transistors have the same performance. When the sizes of the second transistors are different, positive temperature, negative temperature or zero temperature voltage can be obtained by adjusting the sizes of the transistors.
Fig. 3 is a schematic structural diagram of another low dropout linear voltage regulating circuit according to an embodiment of the present invention, and referring to fig. 3, optionally, the amplifying unit 103 includes a fourth transistor NM5, a fifth transistor NM6, a sixth transistor NM7, a seventh transistor NM8, an eighth transistor PM2, a ninth transistor PM3, and a third current source IREF1;
the fourth transistor NM5 is connected to a gate of the fifth transistor NM6 and serves as a first input terminal FA of the amplifying unit 103; a first pole of the fourth transistor NM5 is connected to a second pole of the fifth transistor NM6, and a second pole of the fourth transistor NM5 is connected to a second pole of the eighth transistor PM2, and serves as an output terminal VOUT of the amplifying unit 103; a first pole of the fifth transistor NM6 is connected to a first terminal of the third current source IREF1;
the sixth transistor NM7 is connected to the gate of the seventh transistor NM8 and serves as the second input terminal FB of the amplifying unit 103; a first pole of the sixth transistor NM7 is connected to a second pole of the seventh transistor NM8, a second pole of the sixth transistor NM7 is connected to a second pole of the ninth transistor PM3, and a first pole of the seventh transistor NM8 is connected to a first terminal of the third current source IREF1;
a gate of the eighth transistor PM2 is connected to a gate of the ninth transistor PM3 and a second pole of the ninth transistor PM3, and a first pole of the eighth transistor PM2 and a first pole of the ninth transistor PM3 are connected to the first power supply VDD; a second terminal of the third current source IREF1 is connected to the second power source VSS.
The first pair of transistors in the amplification unit 103 is composed of a fourth transistor NM5 and a fifth transistor NM6, and the second pair of transistors is composed of a sixth transistor NM7 and a seventh transistor NM 8. When the low dropout linear voltage regulator circuit operates, the fourth transistor NM5, in which the first pair of transistors are electrically connected to the output terminal of the reference voltage generating unit 101, operates in a saturation region, and the fifth transistor NM6 operates in a linear region, so that the equivalent output impedance of the fourth transistor NM5 and the output terminal of the reference voltage generating unit 101 is large. On this basis, the occupied area of the fourth transistor NM5, in which the first transistor pair is electrically connected to the output terminal of the reference voltage generation unit 101, is smaller than that of the large resistor, so that the occupied area of the low dropout linear voltage regulator circuit is reduced, the application range of the low dropout linear voltage regulator circuit is increased, an equivalent large impedance can be provided, and no additional current bias or voltage bias is required, thereby not increasing additional power consumption.
With continued reference to FIG. 3, optionally, the current of third current source IREF1 is greater than 3 times the current of first current source IREF3 and the current of second current source IREF 2.
Illustratively, the current consumed to generate the reference voltage VREF is only 10nA, the second current source IREF2 and the first current source IREF3 each consume a current of 5nA, and the third current source IREF1 consumes a current of 25nA.
With continued reference to fig. 3, optionally, the fourth transistor NM5, the fifth transistor NM6, the sixth transistor NM7, and the seventh transistor NM8 are N-type transistors; the eighth transistor PM2 and the ninth transistor PM3 are P-type transistors.
The channel lengths and widths of the fourth and fifth transistors NM5 and NM6 may be equal, and the channel lengths and widths of the sixth and seventh transistors NM7 and NM8 may be equal. In the process of manufacturing the transistors, the transistors in the input pair transistors in the amplifying unit 103 can be equivalent to two same N-type transistors, which not only can reduce the process difficulty, but also the two same transistors have the same performance, when the first power supply VDD and the second power supply VSS are respectively applied to the first pole and the second pole of the symmetrical tube, one transistor can work in a saturation region and the other transistor works in a linear region, so that the compensation loop in the low-dropout linear voltage regulator circuit has a very large equivalent output impedance.
Note that, since the fourth transistor NM5 and the fifth transistor NM6 constitute an output pair transistor, the fourth transistor NM5 and the fifth transistor NM6 need to be the same, that is, the fourth transistor NM5, the fifth transistor NM6, the sixth transistor NM7, and the seventh transistor NM8 may be the same and N-type transistors.
Fig. 4 is a schematic structural diagram of another low dropout linear voltage regulating circuit provided by an embodiment of the present invention, and with continued reference to fig. 4, optionally, the feedback unit 102 includes a capacitor C1, a first pole of the capacitor C1 is connected to the second pole FB of the fourth transistor NM5, and a second pole of the capacitor C1 is connected to the output terminal VDIG of the low dropout linear voltage regulating circuit and the gate FB of the sixth transistor NM 7.
Due to the characteristic of low power consumption of the low dropout linear voltage stabilizing circuit, the phase margin and the bandwidth are difficult to balance. Therefore, the capacitor C1 is adopted to compensate the phase margin and increase the bandwidth, and meanwhile, the occupied area of elements increased when the phase margin and the bandwidth are compensated is reduced, the compensation effect is improved, and the application range of the low dropout linear voltage regulator circuit is further improved.
With continued reference to fig. 4, optionally, the output unit 104 includes a tenth transistor PM4; a first pole of the tenth transistor PM4 is connected to the first power supply VDD, a gate of the tenth transistor PM4 is connected to the output terminal of the amplifying unit 103, and a second pole of the tenth transistor PM4 is connected to the output terminal VDIG of the low dropout linear voltage regulator circuit.
The amplifying unit 103 and the output unit 104 form a feedback loop, and the voltage drop of the transistor is controlled by the feedback loop, so that the low-dropout linear voltage regulator circuit outputs a stable voltage. The tenth transistor PM4 may be a P-type transistor, and the first pole of the tenth transistor PM4 may be a drain and the second pole of the tenth transistor PM4 may be a source.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. The low dropout linear voltage stabilizing circuit is characterized by comprising an amplifying unit, an output unit, a feedback unit and a reference voltage generating unit;
the amplifying unit comprises a first input end, a second input end and an output end; a first input end of the amplifying unit is connected with an output end of the reference voltage generating unit, a second input end of the amplifying unit is connected with an output end of the feedback unit, an input end of the feedback unit is connected with an output end of the output unit, and an input end of the output unit is connected with an output end of the amplifying unit;
the reference voltage generating unit includes a first current source, a second current source, a first transistor, and at least two second and third transistors; the first current source is connected between a first power supply and a first pole of the first transistor, and at least two second transistors are sequentially connected in series and connected between a second pole of the first transistor and a second power supply; the first pole of the first second transistor is connected with the second pole of the first transistor, the second pole of the last second transistor is connected with the second power supply, and the grid electrode of the first transistor and the grid electrode of each second transistor are connected with the first pole of the first transistor; the substrate of the first transistor and the substrates of the second transistors are connected with the second pole of the last second transistor;
the second current source is connected between a first pole of the third transistor and the first power supply, a gate and a second pole of the third transistor are both connected to a second pole of the first transistor, and the first pole of the third transistor is used as an output end of the reference voltage generation unit.
2. The low dropout linear voltage regulator circuit of claim 1, wherein said reference voltage generating unit comprises three of said second transistors;
a first electrode and a grid electrode of the first transistor are connected with a first end of the first current source, and a second end of the first current source is connected with the first power supply;
the first pole of the first second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the first pole of the second transistor, and the second pole of the second transistor is connected with the second power supply.
3. The low dropout linear voltage regulator circuit of claim 2, wherein said first transistor and said second transistor are N-type transistors and said third transistor is P-type transistor.
4. The low dropout linear voltage regulator circuit of claim 2 wherein each of said second transistors is the same size or different sizes.
5. The low dropout linear voltage regulator circuit of claim 2, wherein the voltage of the second pole of the first transistor is independent of process corner and is a positive temperature coefficient voltage.
6. The low dropout linear voltage regulator circuit of claim 1, wherein said amplifying unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a third current source;
the fourth transistor is connected with the grid electrode of the fifth transistor and is used as a first input end of the amplifying unit; a first pole of the fourth transistor is connected with a second pole of the fifth transistor, and a second pole of the fourth transistor is connected with a second pole of the eighth transistor and serves as an output end of the amplifying unit; a first pole of the fifth transistor is connected with a first end of the third current source;
the sixth transistor is connected with the gate of the seventh transistor and serves as a second input end of the amplifying unit; a first pole of the sixth transistor is connected to the second pole of the seventh transistor, a second pole of the sixth transistor is connected to the second pole of the ninth transistor, and a first pole of the seventh transistor is connected to the first terminal of the third current source;
a gate of the eighth transistor is connected to a gate of the ninth transistor and a second pole of the ninth transistor, and a first pole of the eighth transistor and a first pole of the ninth transistor are connected to the first power supply; a second terminal of the third current source is connected to the second power supply.
7. The low dropout linear voltage regulator circuit of claim 6 wherein the current of said third current source is greater than 3 times the current of said first current source and the current of said second current source.
8. The low dropout linear voltage regulator circuit of claim 6, wherein said fourth transistor, said fifth transistor, said sixth transistor, said seventh transistor are N-type transistors;
the eighth transistor and the ninth transistor are P-type transistors.
9. The low dropout linear voltage regulator circuit of claim 6, wherein the feedback unit comprises a capacitor, a first pole of the capacitor is connected to a second pole of the fourth transistor, and a second pole of the capacitor is connected to the output of the low dropout linear voltage regulator circuit and the gate of the sixth transistor.
10. The low dropout linear voltage regulator circuit of claim 1, wherein said output unit comprises a tenth transistor; a first pole of the tenth transistor is connected to the first power supply, a gate of the tenth transistor is connected to the output terminal of the amplifying unit, and a second pole of the tenth transistor is connected to the output terminal of the low dropout linear voltage regulator circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| KR101585958B1 (en) * | 2008-12-29 | 2016-01-18 | 주식회사 동부하이텍 | Reference voltage generation circuit |
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