CN114095047B - Signal processing circuit, chip and receiver - Google Patents

Abstract

An embodiment of the present application provides a signal processing circuit, including an amplitude processing circuit for converting the amplitude component in the signal into an amplitude quantized signal; a phase processing circuit for converting the phase component in the signal into a phase quantized signal The demodulator is electrically connected to the amplitude processing circuit and the phase processing circuit, and is used to synthesize and map the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, and the demodulated signal includes the signal of the original data. The embodiment of the present application also provides a chip and a receiver. Therefore, the signal processing circuit and electronic equipment provided by the embodiment of the present application can reduce the complexity and power consumption of the receiver circuit, and at the same time, when the amplitude processing circuit is enabled separately, it can realize The low power consumption wake-up mechanism further reduces the average power consumption of the receiver.

Description

Signal processing circuit, chip and receiver

technical field

The present application relates to the technical field of wireless communication, in particular to a signal processing circuit, chip and receiver.

Background technique

With the rapid development of wireless communication, wireless sensor networks have also been widely used. Wireless sensor networks include multiple wireless sensor nodes, and the wireless sensor nodes are usually powered by batteries. Therefore, the wireless sensor nodes Higher requirements for low power consumption. The wireless sensor node includes a wireless receiver, and the wireless receiver is used to receive and demodulate the wireless signals transmitted between each node. However, the existing wireless receiver has complex circuit structure and high power consumption, which is not conducive to large-scale Large-scale and large-scale applications in wireless sensor networks.

Contents of the invention

In view of the above problems, the embodiment of the present application provides a signal processing circuit and a receiver, by setting the amplitude processing circuit and the phase processing circuit, the wireless signal based on the polar coordinate form is decoupled from the two aspects of amplitude and phase, and respectively Signal processing, realizing a low-power wake-up mechanism, thereby reducing the complexity and power consumption of the receiver circuit.

The first aspect of the embodiments of the present application provides a signal processing circuit, including:

An amplitude processing circuit, configured to convert the amplitude component in the wireless signal into an amplitude quantized signal, the amplitude component being used to indicate the amplitude information in the wireless signal;

a phase processing circuit, configured to convert a phase component in the wireless signal into a phase quantized signal, and the phase component is used to indicate phase information in the wireless signal;

The demodulator is electrically connected to the amplitude processing circuit and the phase processing circuit, and is used to synthesize and map the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, and the demodulated signal includes the wireless signal of the original data.

In some possible implementation manners, the signal processing circuit further includes a first amplifier, the first amplifier is electrically connected to the amplitude processing circuit and the phase processing circuit, and the first amplifier is used to convert the signal After being amplified, it is output to the amplitude processing circuit and the phase processing circuit.

In some possible implementation manners, the amplitude processing circuit includes:

a detector, configured to detect amplitude information of the signal, and output an envelope signal according to the amplitude information, and the envelope signal is used to indicate a signal peak value of the signal;

a first filter, electrically connected to the detector, for receiving the envelope signal, and for filtering the envelope signal to obtain a first filtered signal;

A second amplifier, electrically connected to the first filter, for receiving the first filtered signal, and for amplifying the first filtered signal to obtain a first amplified signal;

a comparator, electrically connected to the second amplifier, for receiving the first amplified signal, and for converting the first amplified signal into an amplitude quantized signal.

In some possible implementation manners, the phase processing circuit includes:

a phase detector, configured to detect a phase difference between the phase of the signal and a reference signal, to obtain a phase difference signal;

a third amplifier, electrically connected to the phase detector, for receiving the phase difference signal, and for amplifying the phase difference signal to obtain a second amplified signal;

a second filter, electrically connected to the third amplifier, for receiving the second amplified signal, and for filtering the second amplified signal to obtain a second filtered signal;

a first oscillator, electrically connected to the second filter and the phase detector, for receiving the second filtered signal, and for outputting a reference signal to the phase detector according to the second filtered signal;

An analog-to-digital converter, electrically connected to the second filter, for converting the second filtered signal into a phase quantized signal.

In some possible implementation manners, the phase processing circuit further includes a frequency tracking circuit and a frequency calibration circuit;

The frequency tracking circuit is electrically connected to the second filter and the first oscillator for compensating the carrier frequency drift of the signal;

The frequency calibration circuit is electrically connected to the first oscillator and the phase detector for calibrating the frequency of the reference signal.

In some possible implementation manners, the signal processing circuit further includes a gain control circuit, the gain control circuit is electrically connected to the second amplifier, the first filter, and the third amplifier, and is configured to The first filtered signal adjusts the amplification gains of the second amplifier and the third amplifier.

In some possible implementation manners, the gain control circuit includes a second oscillator, a counter, a control circuit, and a resistor array;

The second oscillator is electrically connected to the first filter, and is used to output an oscillating signal according to the first filtered signal, and the oscillating signal is used to indicate the amplitude information of the first filtered signal;

The counter is electrically connected to the second oscillator, and is used to receive the oscillating signal, calculate the frequency of the oscillating signal, and output a frequency signal, the frequency signal is used to indicate the frequency information of the oscillating signal, and then indicating amplitude information of the first filtered signal;

The control circuit is electrically connected to the counter, the resistor array, the second amplifier and the third amplifier, and is used to receive the frequency signal, calculate the received power of the signal according to the frequency signal, and adjusting the resistance value of the resistor array, the amplification gain of the second amplifier, and the amplification gain of the third amplifier by receiving power;

The resistor array is electrically connected to the comparator, and the resistor array adjusts the threshold voltage of the comparator according to its resistance value.

In some possible implementation manners, the demodulator outputs a wake-up signal to the phase processing circuit based on the amplitude quantization signal matching a preset sequence, and the wake-up signal is used to start the phase processing circuit.

The second aspect of the embodiment of the present application provides a chip, including:

The signal processing circuit according to any one of the above; and a matching circuit, electrically connected to an antenna and the signal processing circuit, for matching the input impedance of the antenna and the signal processing circuit.

A third aspect of the embodiments of the present application provides a receiver, including the chip as described above.

Therefore, the signal processing circuit and the receiver provided in the embodiment of the present application, by setting the amplitude processing circuit and the phase processing circuit, decouple and separate the wireless data based on the polar coordinate form from the two aspects of amplitude and phase, and perform signal processing respectively And demodulation, thereby reducing the complexity and power consumption of the receiver circuit. At the same time, when the amplitude processing circuit is enabled separately, the low power consumption wake-up mechanism can be realized without changing the signal modulation mode, and the receiver’s power consumption can be further reduced. average power consumption.

Description of drawings

FIG. 1 is an application scenario diagram of a receiver provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of a chip provided by an embodiment of the present application.

FIG. 3 is a schematic structural diagram of the amplitude processing circuit and the phase processing circuit in FIG. 2 .

FIG. 4 is a circuit diagram of the gain control circuit in FIG. 3 .

FIG. 5 is a constellation diagram of a wireless signal received by the signal processing circuit in FIG. 2 .

FIG. 6 is a signal schematic diagram of processing wireless signals by the signal processing circuit in FIG. 2 .

Description of main component symbols

Antenna 10

Matching Circuit 20

The first amplifier 30

Amplitude processing circuit 40

Phase processing circuit 50

Gain Control Circuit 60

Demodulator 70

Signal processing circuit 100

Detector 101

First Filter 102

Second Amplifier 103

Comparator 104

Crossover 105

External clock source 106

Phase Detector 201

The third amplifier 202

Second Filter 203

Analog-to-Digital Converter 204

Frequency Tracking Circuit 205

First Oscillator 206

Frequency Calibration Circuit 207

Second Oscillator 301

Counter 302

Control Circuit 303

Resistor Array 304

Chip 200

Receiver 300

Wireless Devices 400

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

In the embodiment of the present application, terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. For example, the first application, the second application, etc. are used to distinguish different applications, rather than to describe the specific order of applications, and the features defined as "first" and "second" may explicitly or implicitly include one or More of this feature.

Please refer to FIG. 1. FIG. 1 shows an application scene diagram of a receiver 300 provided by an embodiment of the present application. As shown in FIG. 1, the receiver 300 can be used to receive a wireless signal sent by a wireless device 400, and The wireless signal is demodulated to recover the data of the wireless signal. The wireless signal can be expressed in polar coordinate form, for example, wireless signal S=A*e ^jθ , where A is the amplitude component of the wireless signal S, and in the polar coordinate system, the distance from the pole to the coordinate point of the wireless signal is Modulo representation, θ is the phase component of the wireless signal S, expressed in the polar coordinate system by the angle between the pole and the wireless signal line and the horizontal axis; the amplitude component A is used to indicate the wireless signal S The amplitude information of the phase component θ is used to indicate the phase information of the wireless signal S.

In some embodiments, the wireless device 400 may be an electronic device capable of sending radio and wireless signals, such as a base station, a radio station, and a terminal device.

Please refer to FIG. 2 , which is a schematic diagram of a chip 200 provided by an embodiment of the present application. The chip 200 can be set in the receiver 300 .

As shown in Figure 2, the chip 200 may include a matching circuit 20 and a signal processing circuit 100, the matching circuit 20 is electrically connected to an antenna 10, the antenna 10 is used to receive wireless signals, and transmit the wireless signals To the matching circuit 20, the matching circuit 20 is used to match the impedance of the antenna 10 and the input end of the signal processing circuit 100, so as to reduce the reflected wave and radiation interference of the wireless signal, and improve the The transmission efficiency of wireless signals.

It should be noted that the antenna 10 may be integrated on the chip 200 or independently arranged on the receiver 300 , and the application does not limit the positional relationship of the antenna 10 .

In some embodiments, the antenna 10 can be a monopole antenna, a planar inverted F-shaped antenna (Planar InvertedF-shaped Antenna, PIFA), a multi-branch antenna, etc., and the matching circuit 20 can be an L-shaped matching circuit, a T Type matching circuit, π-type matching circuit or other capacitors, inductors, and combinations of capacitors and inductors.

In this embodiment, the signal processing circuit 100 may include a first amplifier 30, an amplitude processing circuit 40, a phase processing circuit 50, and a demodulator 70, wherein the first amplifier 30 is electrically connected to the matching circuit 20 for receiving Through the wireless signal output by the matching circuit 20, the wireless signal is amplified.

In some embodiments, the first amplifier 30 can be a low-noise amplifier, and the first amplifier 30 has a low noise figure, and can perform low-noise amplification on the wireless signal to improve the signal-to-noise of the wireless signal ratio, which facilitates subsequent signal processing of the wireless signal.

The amplitude processing circuit 40 is electrically connected to the first amplifier 30, and the amplitude processing circuit 40 is used to receive the amplitude component of the wireless signal, demodulate and quantize the amplitude component of the wireless signal, and convert the amplitude component of the wireless signal to The amplitude component is converted into an amplitude quantized signal; the phase processing circuit 50 is electrically connected to the first amplifier 30, and the phase processing circuit 50 is used to receive the phase component of the wireless signal and perform a phase analysis of the wireless signal The component is demodulated and quantized, and the phase component is converted into a phase quantized signal; the demodulator 70 is electrically connected to the amplitude processing circuit 40 and the phase processing circuit 50, and the demodulator 70 is used to receive The amplitude quantized signal and the phase quantized signal are mapped and synthesized to obtain a demodulated signal. The mapping synthesis refers to matching the amplitude quantized signal and the phase quantized signal with a preset matching table to obtain the amplitude information and the phase information corresponding to the wireless signal, and then combining the amplitude information with the The phase information is combined to obtain the demodulated signal, so as to obtain data of the wireless signal.

In some embodiments, the signal processing circuit 100 includes a low power consumption mode and a normal power consumption mode, when the signal processing circuit 100 works in the low power consumption mode, the phase processing circuit 50 is turned off, and the The demodulator 70 only receives the amplitude quantized signal, and determines whether to open the phase processing circuit according to the received amplitude quantized signal. Specifically, the demodulator 70 can compare the amplitude quantized signal with a preset sequence , if the amplitude quantization signal is consistent with the preset sequence, the demodulator 70 may output a wake-up signal to the phase processing circuit 50, the wake-up signal is used to start the phase processing circuit 50, the The signal processing circuit 100 enters the normal power consumption mode, and the amplitude processing circuit 40, the phase processing circuit 50, and the demodulator 70 all start to work; if the amplitude quantization signal is inconsistent with the preset sequence, the decoding Modulator 70 continues to receive the amplitude quantized signal.

It should be noted that the preset sequence can be configured in advance, and the preset sequence can be a specific binary sequence, and the present invention does not impose any limitation on the configuration method and data format of the preset sequence.

Please refer to FIG. 3 , which is a schematic structural diagram of the amplitude processing circuit 40 and the phase processing circuit 50 in FIG. 2 . The amplitude processing circuit 40 may include a detector 101, a first filter 102, a second amplifier 103, a comparator 104, and a frequency divider 105, and the detector 101 is used to receive the amplified signal from the first amplifier 30. wireless signal, and is used to detect the amplitude information of the wireless signal, the detector 101 outputs an envelope signal according to the amplitude information, and the envelope signal can indicate the signal peak value of the wireless signal; at the same time, the detector 101 may perform down-conversion on the envelope signal. The down-conversion refers to converting the high-frequency signal into a lower-frequency signal by removing most of the carrier frequency in the high-frequency signal, thereby improving the sensitivity to the wireless signal. The efficiency of signal processing.

It can be understood that the detector 101 has the function of realizing the down-conversion of the wireless signal and detecting the amplitude information of the wireless signal, and does not need to install other electronic modules, which simplifies the circuit structure of the signal processing circuit 100 and reduces the frequency of the signal. Power consumption of processing circuit 100 .

The first filter 102 is electrically connected to the detector 101, and the first filter 102 is used to filter the down-converted envelope signal to filter out residual spurious signals in the envelope signal and the carrier harmonic signal to obtain a first filtered signal to further improve the signal-to-noise ratio of the envelope signal.

In some embodiments, the first filter 102 may be a low-pass filter.

The second amplifier 103 is electrically connected to the first filter 102, the second amplifier 103 is used to amplify the first filtered signal, the comparator 104 is electrically connected to the second amplifier 103, and the comparator 104 is used for comparing the voltage value of the first filter signal with a threshold signal, and outputting an amplitude quantization signal according to the comparison result. It can be understood that the comparator 104 may serve as an analog-to-digital converter, converting the analog first filtered signal into a digital amplitude quantized signal through quantization, and the amplitude quantized signal may indicate amplitude information of the amplitude component of the wireless signal.

In some embodiments, the second amplifier 103 may be a variable gain amplifier.

The frequency divider 105 is electrically connected to the comparator 104 and the external clock source 106, the frequency divider 105 is used to receive the clock signal provided by the external clock source 106, and adjust the comparator 104 according to the frequency of the clock signal working frequency. Specifically, the frequency divider 105 can be configured to have a preset frequency division coefficient, and the frequency divider 105 can convert the frequency of the clock signal provided by the external clock source 106 into The operating frequency of the comparator 104 .

The phase processing circuit 50 may include a phase detector 201, a third amplifier 202, a second filter 203, an analog-to-digital converter 204, a frequency tracking circuit 205, a first oscillator 206, and a frequency calibration circuit 207, wherein the phase detector 201 is electrically connected to the first amplifier 30, and the phase detector 201 is used to receive the wireless signal output by the first amplifier 30, down-convert the wireless signal, and calculate the wireless signal phase difference with a reference signal to output a phase difference signal.

It can be understood that the phase detector 201 has the functions of realizing down-conversion of the wireless signal and calculating the phase difference between the wireless signal and a reference signal, without setting other electronic modules (for example, additional frequency synthesizers such as phase-locked loops) To generate the local oscillator signal, the circuit structure of the signal processing circuit 100 is simplified, and the energy efficiency of the phase processing circuit 50 is improved at the same time.

The third amplifier 202 is electrically connected to the phase detector 201, the third amplifier 202 is used to amplify the phase difference signal, the second filter 203 is electrically connected to the third amplifier 202, The second filter 203 is used to filter the amplified phase difference signal and output a second filtered signal.

In some embodiments, the third amplifier 202 may be a variable gain amplifier, the second filter 203 may be a loop low-pass filter, and the second filter 203 is used to adjust the amplified phase The difference signal is band-limited filtered.

The first oscillator 206 is electrically connected to the second filter 203, and the first oscillator 206 is used to output a reference phase signal to the phase detector 201 according to the second filtered signal. In some embodiments, the first oscillator 206 may be a voltage-controlled oscillator, and the first oscillator 206 may control the frequency of the output reference phase signal according to the voltage of the second filtered signal, and the reference The frequency of the phase signal is f=v*Kvco, where v is the voltage value of the second filtered signal, and Kvco is the voltage-controlled gain of the first oscillator 206 .

It can be understood that the phase detector 201, the third amplifier 202, the second filter 203, and the first oscillator 206 form a phase tracking loop, and it has the characteristics of closed-loop control. The phase of the reference signal is dynamically adjusted, so as to improve the working stability of the phase processing circuit 50 when the phase of the wireless signal fluctuates.

The analog-to-digital converter 204 is electrically connected to the second filter 203 and the external clock source 106, and the analog-to-digital converter 204 is used to quantize the analog second filtered signal and convert the second The filtered signal is converted to a phase quantized signal.

In some embodiments, the analog-to-digital converter 204 may be a successive approximation analog-to-digital converter.

In this embodiment, the phase processing circuit 50 further includes a frequency tracking circuit 205 and a frequency calibration circuit 207, the frequency tracking circuit 205 is electrically connected to the first oscillator 206 and the second filter 203, the The frequency tracking circuit 205 is used to compensate the low-frequency frequency of the wireless signal when the carrier frequency of the wireless signal drifts at a low frequency; the frequency calibration circuit 207 is electrically connected to the phase detector 201 and the first oscillator 206. The frequency calibration circuit 207 is configured to calibrate the frequency of the reference signal output by the first oscillator 206.

The demodulator 70 is electrically connected to the comparator 104 and the analog-to-digital converter 204, and the demodulator 70 is used to receive the amplitude quantization signal output by the comparator 104 and the analog-to-digital converter 204 The output phase quantized signal is used to map and synthesize the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, where the demodulated signal includes the data of the wireless signal.

It can be understood that the signal processing circuit 100 may only enable the first amplifier 30, the amplitude processing circuit 40 and the demodulator 70 to implement continuous listening and detection of the wireless signal, at this time the The signal processing circuit 100 is in the low power consumption mode, and in the low power consumption mode, the signal processing circuit 100 can receive and quantize the amplitude information in the wireless signal, and output the amplitude quantized signal, so The demodulator 70 can output the enable signal to enable the phase processing circuit 50 by comparing the amplitude quantization signal with the preset sequence, and then receive and process the amplitude information and phase information of the wireless signal . Therefore, the signal processing circuit 100 does not need an independent wake-up response circuit, can further reduce the power consumption level, and is suitable for wireless sensor networks that work with a duty cycle.

In this embodiment, the signal processing circuit 100 further includes a gain control circuit 60, the gain control circuit 60 is electrically connected to the first filter 102, the second amplifier 103 and the third amplifier 202, so The gain control circuit 60 is configured to adjust the amplification gains of the second amplifier 103 and the third amplifier 202 according to the voltage value of the first filtered signal output by the first filter 102 . Specifically, when the power of the wireless signal received by the first amplifier 30 changes, the voltage value of the first filtered signal will also change accordingly, and the gain control circuit 60 may The signal output power at the receiving end of the first amplifier 30 is calculated from the voltage value of a filtered signal, so as to adjust the amplification gains of the second amplifier 103 and the third amplifier 202 according to the calculation result.

It can be understood that when the power of the wireless signal changes, the gain control circuit 60 can ensure that the quantization threshold of the comparator 104 is appropriate, and keep the loop bandwidth of the phase processing circuit 50 stable, thereby minimizing the bit error rate , expanding the dynamic operating range of the signal processing circuit 100, and improving the dynamic response performance of the signal processing circuit 100, and the gain control circuit 60 can only work in the data frame header stage of the wireless signal, and the power consumption lower.

Please refer to FIG. 4 , which shows a circuit diagram of the gain control circuit 60 in FIG. 3 . As shown in FIG. 4 , the gain control circuit 60 includes a second oscillator 301 , a counter 302 , a control circuit 303 and a resistor array 304 .

The second oscillator 301 is electrically connected to the first filter 102, the second oscillator 301 is used to receive the first filtered signal, and output an oscillating signal according to the voltage value of the first filtered signal, The frequency of the oscillating signal is associated with the voltage value of the first filtered signal. It can be understood that the voltage value of the first filtered signal is the envelope information of the first filtered signal, that is, the frequency of the oscillation signal can be used to indicate the envelope information of the wireless signal.

The counter 302 is electrically connected to the second oscillator 301, the counter 302 is used to receive the oscillating signal, and is used to calculate the frequency of the oscillating signal, and output a frequency signal, the frequency signal is used to indicate the The frequency information of the oscillating signal further indicates the amplitude information of the first filtered signal. Specifically, the counter 302 can calculate the frequency of the oscillating signal by counting the pulses of the oscillating signal within a unit time.

The control circuit 303 is electrically connected to the counter 302, the resistor array 304, the second amplifier 103 and the third amplifier 202, and the control circuit 303 is used to receive the frequency signal and calculate the frequency signal according to the frequency signal. The received power of the wireless signal is adjusted, and the resistance value of the resistor array 304, the amplification gain of the second amplifier 103 and the amplification gain of the third amplifier 202 are adjusted according to the received power. Specifically, a preset matching code table can be set in the control circuit 303, and the control circuit 303 can map the frequency of the frequency signal to the received power of the first amplifier 30 according to the matching code table, so that Calculate the received power of the wireless signal according to the frequency of the frequency signal. The control circuit 303 can adjust the amplification gains of the second amplifier 103 and the third amplifier 202 according to the received power. For example, when the control circuit 303 calculates that the received power is lower than a preset threshold , the control circuit 303 can increase the amplification gain of the second amplifier 103 and the third amplifier 202 to ensure that the loop unit of the phase tracking loop is stable, so as to better demodulate the wireless signal .

The resistor array 304 is electrically connected to the comparator 104, the resistor array 304 can be composed of several resistors connected in series or in parallel, and the threshold voltage of the comparator 104 is adjusted according to the total resistance value thereof, for example, When the control circuit 303 calculates that the received power is lower than a preset threshold, the control circuit 303 can change the resistance value of the resistor array 304, thereby reducing the threshold voltage of the comparator 104 to ensure that the comparator 104 to quantify the accuracy of the decision.

Please refer to FIG. 5 , which shows a constellation diagram of the wireless signal received by the signal processing circuit 100 in FIG. 2 . As shown in Figure 5, the wireless signal can be a star hexadecimal quadrature amplitude modulation signal (Star-16Quadrature Amplitude Modulation, Star-16 QAM), and the Star-16 QAM signal includes 16 different symbols in total , each symbol is represented by four binary digits, where the highest digit represents the magnitude bit of the symbol, and the lower three digits represent the phase bit of the symbol. For example, the amplitude bit of the symbol 0111 is 1, and the phase bit is 011. On the constellation diagram, the amplitude bit corresponds to the modulus between the symbol coordinate point and the coordinate origin, and the phase bit corresponds to the connection line between the symbol and the coordinate origin and The angle between the horizontal axis of the coordinate system.

It should be noted that the above-mentioned amplitude bits and phase bits have been encoded, and according to the different encoding methods, the actual amplitude value and the actual phase value represented by the amplitude bits and phase bits are also different. limited.

It can be understood that the Star-16 QAM symbol can be regarded as the sum of a differential eight-phase phase shift keying (Differential8Phase Shift Keying, D8PSK) symbol and an amplitude modulation (Amplitude Modulation, AM) symbol, wherein the D8PSK symbol corresponds to the Star-16 QAM symbol. The phase bits of 16 QAM symbols, and the D8PSK symbols can represent eight different phases, the AM signal corresponds to the amplitude bits of the Star-16 QAM symbols, and the AM symbols can represent two different amplitudes, for example, Star-16 QAM Symbol 0111 can be regarded as the sum of D8PSK symbol 011 and AM symbol 1.

Taking three consecutive Star-16 QAM symbols 0001, 0111, and 1110 as an example, the working process of the signal processing circuit 100 will be introduced below.

Please refer to FIG. 6 . FIG. 6 is a signal schematic diagram of processing wireless signals by the signal processing circuit 100 in FIG. 2 .

After the wireless signal is amplified by the first amplifier 30, the waveform of the first amplified signal is obtained as shown in the curve L1. The first amplified signal includes three continuous bands, corresponding to symbols 0001, 0111 and 1110 respectively.

In the amplitude domain, the detector 101 receives the first amplified signal, and through detection by the detector 101, filtering by the first filter 102, and amplification by the second amplifier 103, the waveform of the second amplified signal is obtained as shown in curve L2 It can be understood that the amplitude bit corresponding to symbol 0001 and symbol 0111 in the three consecutive bands of the second amplified signal is 1, the amplitude bit corresponding to symbol 1110 is 0, and the amplitude value corresponding to amplitude bit 0 is smaller than that corresponding to amplitude bit 1 Amplitude value. The comparator 104 compares the second amplified signal with the threshold voltage, thereby quantizing the second analog amplified signal into a digital amplitude quantized signal, and completing the analog-to-digital conversion in the amplitude domain. The signal waveform output by the comparator is shown in curve L3 .

In the phase domain, the phase detector 201 receives the first amplified signal, and through the amplification by the third amplifier 202 and the filtering by the second filter 203, the waveform of the second filtered signal is obtained as shown in the curve L5. It can be understood that the first The second filtered signal consists of three consecutive bands corresponding to the phase values of symbols 0001, 0111 and 1110, respectively. The phase bit of the initial reference signal is 000. Referring to the constellation diagram shown in Figure 3, the counterclockwise direction is positive, the phase difference between the symbol 0001 and the reference signal is 0, the phase difference between the symbol 0111 and the reference signal is +2, and the symbol 1110 The phase difference with the reference signal is -3, corresponding to three consecutive voltage values 0, +2, -3 in the second filtered signal. The analog-to-digital converter 204 performs analog-to-digital conversion on the second filtered signal, so as to obtain a digital phase quantized signal, and completes the analog-to-digital conversion in the phase domain.

The demodulator 70 receives the amplitude quantized signal output by the comparator 104 and the phase quantized signal output by the analog-to-digital converter 204, and synthesizes the amplitude quantized signal and the phase quantized signal. Call out the original symbols as 0001, 0111 and 1110, and complete the demodulation process.

Therefore, the signal processing circuit and the receiver provided in the embodiment of the present application, by setting the amplitude processing circuit and the phase processing circuit, decouple and separate the wireless data based on the polar coordinate form from the two aspects of amplitude and phase, and perform signal processing respectively And demodulation, thereby reducing the complexity and power consumption of the receiver circuit. At the same time, when the amplitude processing circuit is enabled separately, the average power consumption of the receiver can be further reduced without changing the signal modulation mode.

Those of ordinary skill in the art should recognize that the above implementations are only used to illustrate the present application, and are not used as a limitation to the present application. Alterations and variations are within the scope of the claims of this application.

Claims (10)

1. A signal processing circuit, characterized in that, the signal processing circuit comprises: An amplitude processing circuit, configured to receive a wireless signal output by the wireless device, and convert the amplitude component in the wireless signal into an amplitude quantized signal, the amplitude component being used to indicate the amplitude information in the wireless signal; a phase processing circuit, configured to receive the wireless signal output by the wireless device, and convert a phase component in the wireless signal into a phase quantized signal based on a closed-loop controlled phase tracking loop, where the phase component is used to indicate the phase information in the wireless signal; The demodulator is electrically connected to the amplitude processing circuit and the phase processing circuit, and is used for synthesizing and mapping the amplitude quantized signal and the phase quantized signal to demodulate the wireless signal. 2. The signal processing circuit according to claim 1, wherein the signal processing circuit further comprises a first amplifier, the first amplifier is electrically connected to the amplitude processing circuit and the phase processing circuit, the The first amplifier is used to amplify the wireless signal and output it to the amplitude processing circuit and the phase processing circuit. 3. The signal processing circuit according to any one of claims 1-2, wherein the amplitude processing circuit comprises: a detector, configured to detect amplitude information of the wireless signal, and output an envelope signal according to the amplitude information, and the envelope signal is used to indicate a signal peak value of the wireless signal; a first filter, electrically connected to the detector, for receiving the envelope signal, and for filtering the envelope signal to obtain a first filtered signal; A second amplifier, electrically connected to the first filter, for receiving the first filtered signal, and for amplifying the first filtered signal to obtain a first amplified signal; a comparator, electrically connected to the second amplifier, for receiving the first amplified signal, and for converting the first amplified signal into an amplitude quantized signal. 4. The signal processing circuit according to claim 3, wherein the phase processing circuit comprises: a phase detector, configured to detect the phase difference between the phase of the wireless signal and the reference signal, to obtain a phase difference signal; a third amplifier, electrically connected to the phase detector, for receiving the phase difference signal, and for amplifying the phase difference signal to obtain a second amplified signal; a second filter, electrically connected to the third amplifier, for receiving the second amplified signal, and for filtering the second amplified signal to obtain a second filtered signal; a first oscillator, electrically connected to the second filter and the phase detector, for receiving the second filtered signal, and for outputting a reference signal to the phase detector according to the second filtered signal; An analog-to-digital converter, electrically connected to the second filter, for converting the second filtered signal into a phase quantized signal. 5. The signal processing circuit according to claim 4, wherein the phase processing circuit further comprises a frequency tracking circuit and a frequency calibration circuit; The frequency tracking circuit is electrically connected to the second filter and the first oscillator for compensating the carrier frequency drift of the wireless signal; The frequency calibration circuit is electrically connected to the first oscillator and the phase detector for calibrating the frequency of the reference signal. 6. The signal processing circuit according to claim 4, wherein the signal processing circuit further comprises a gain control circuit, and the gain control circuit is electrically connected to the second amplifier, the first filter and the The third amplifier is configured to adjust the amplification gains of the second amplifier and the third amplifier according to the first filtered signal. 7. The signal processing circuit according to claim 6, wherein the gain control circuit comprises a second oscillator, a counter, a control circuit, and a resistor array; The second oscillator is electrically connected to the first filter, and is used to output an oscillating signal according to the first filtered signal, and the oscillating signal is used to indicate the amplitude information of the first filtered signal; The counter is electrically connected to the second oscillator, and is used to receive the oscillating signal, calculate the frequency of the oscillating signal, and output a frequency signal, the frequency signal is used to indicate the frequency information of the oscillating signal, and then indicating amplitude information of the first filtered signal; The control circuit is electrically connected to the counter, the resistor array, the second amplifier, and the third amplifier, and is used to receive the frequency signal, calculate the received power of the wireless signal according to the frequency signal, and calculate the received power of the wireless signal according to the frequency signal. adjusting the resistance value of the resistance array, the amplification gain of the second amplifier, and the amplification gain of the third amplifier by adjusting the received power; The resistor array is electrically connected to the comparator, and the resistor array adjusts the threshold voltage of the comparator according to its resistance value. 8. The signal processing circuit according to claim 1, wherein the demodulator outputs an enabling signal to the phase processing circuit based on the amplitude quantization signal matching a preset sequence, and the enabling signal Used to start the phase processing circuit. 9. A chip, characterized in that the chip comprises: The signal processing circuit according to any one of claims 1-8; and The matching circuit is electrically connected to the antenna and the signal processing circuit, and is used to match the input impedance of the antenna and the signal processing circuit. 10. A receiver, characterized in that the receiver comprises the chip according to claim 9.

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