CN114095021B - A resistance mismatch calibration method and circuit for a resistance-type digital-to-analog converter - Google Patents

Abstract

The present invention proposes a resistance mismatch calibration method and circuit for a resistance type digital-to-analog converter, which uses a calibration logic module to control the digital input of the digital-to-analog converter so that the digital-to-analog converter generates several specific output voltages, stores these voltages with a self-zeroing comparator and compares them, and then the calibration logic adjusts the resistance value to be adjusted according to the comparison result, thereby reducing the mismatch between the resistors. The method and circuit of the present invention can improve the accuracy of the digital-to-analog converter. The calibration method of the present invention and the corresponding circuit can reduce the mismatch of the resistance between the binary sub-digital-to-analog converter and the thermometer code sub-digital-to-analog converter when calibrating the resistor, thereby improving the accuracy of the entire digital-to-analog converter.

Description

A resistance mismatch calibration method and circuit for a resistance-type digital-to-analog converter

Technical Field

The invention belongs to the field of digital-to-analog converters, and in particular relates to a resistance mismatch calibration method and circuit for a resistance-type digital-to-analog converter.

Background Art

Digital-to-analog converters are widely used in the fields of communications, sensors, and test instruments. The difficulty in designing high-precision and high-speed digital-to-analog converters lies in the fact that high precision and high speed are two contradictory indicators. In order to achieve high precision, large-sized devices are used to reduce the mismatch generated during the processing, and then the parasitic capacitance of large-sized devices will cause the speed to decrease. Therefore, one way to achieve high precision and high speed at the same time is to use small-sized devices to meet the speed requirements, and reduce the mismatch between devices through automatic calibration to achieve high precision.

Summary of the invention

In view of the above problems, the present invention proposes a resistance mismatch calibration method and circuit for a resistance-type digital-to-analog converter, which are used to reduce the resistance mismatch in the resistance-type digital-to-analog converter, thereby improving its accuracy.

On the one hand, the present invention provides a resistance mismatch calibration method for a resistance type digital-to-analog converter, wherein the resistance type digital-to-analog converter is composed of a binary sub-digital-to-analog converter of a low-bit D[N-1:0] bit and an M-bit thermometer code sub-digital-to-analog converter of a high-bit D[M+N-1:N]; the output of the digital-to-analog converter is connected to the left side of a capacitor C1, the right side of the capacitor C1 is connected to the reverse input end of an amplifier, the voltage of the positive input end of the amplifier is V _cm , the output of the amplifier is connected to a calibration logic, the output of the calibration logic is connected to the digital-to-analog converter, and controls the input signals D[M+N-1:N] and THM[i:2 ^M -1] of the digital-to-analog converter, the switch S1 is connected in parallel with the amplifier, and the calibration comprises the following steps:

Step 1: Set the calibration logic configuration CAL_EN=1, set the calibration logic internal register record=0, i=0;

Step 2: The calibration logic configuration switch S1 is turned on, and the digital-to-analog converter input is configured to be D[M+N-1:N]=0, D[N-1:0]=1, and D_CAL=1;

Step 3: Configure switch S1 to be disconnected. After switch S1 is disconnected, configure D[N-1:0]=0, D_CAL=0, and configure the input of the binary-to-thermometer decoder & selector to THM[i]=1, THM[1:i-1]=0, THM[i:2 ^M -1]=0;

Step 4: Detect the logic output of the amplifier, if it is high, record = record + 1, if it is low and record>0, record = record-1;

Step 5: Repeat steps 2 to 4 for a total of 4 times. If record>2, reduce the resistance R _i ; if record<2, increase the resistance R _i ; if record＝2, keep the resistance R _i unchanged; reset record to 0, i＝i+1, and proceed to the next step;

Step 6: Repeat steps 2 to 5 to traverse the resistances from i=1 to i=2 ^M -1. After the traversal is completed, the calibration is terminated and CAL_EN=0 and D_CAL=0 are configured.

Furthermore, a switch-controlled resistor array is used to adjust the resistance R _i .

On the other hand, the present invention proposes a resistance mismatch calibration circuit for a resistance-type digital-to-analog converter, wherein the output of the digital-to-analog converter is connected to the left side of a capacitor C1, the right side of the capacitor C1 is connected to the reverse input terminal of an amplifier, the voltage of the positive input terminal of the amplifier is V _cm , the output of the amplifier is connected to a calibration logic, the output of the calibration logic is connected to the digital-to-analog converter, and controls the input signals D[M+N-1:N] and THM[i:2 ^M -1] of the digital-to-analog converter, the switch S1 is connected in parallel with the amplifier, and the calibration circuit calibrates the resistance mismatch using the above calibration method when in use.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a circuit block diagram of a resistive digital-to-analog converter;

FIG. 2 is a block diagram of a resistance mismatch calibration circuit for a resistance-type digital-to-analog converter.

DETAILED DESCRIPTION

The present invention proposes a resistance mismatch calibration method for a resistance-type digital-to-analog converter. The method utilizes the characteristics of the digital-to-analog converter structure, as shown in FIG1 as a typical resistance-type digital-to-analog converter. The digital-to-analog converter is composed of a binary sub-digital-to-analog converter 1 of a low-bit D[N-1:0] bit and an M-bit thermometer code sub-digital-to-analog converter 2 of a high-bit D[M+N-1:N]. When the binary-to-thermometer decoder & selector is in normal operation (CAL_EN=0), its function is to convert the input D[M+N-1:N] into a 1:2 ^M -1 thermometer code. When the digital-to-analog converter switches from a low bit to a high bit, the resistance mismatch will cause an error in the output voltage of the digital-to-analog converter. The method of the present invention can calibrate the mismatch between the output resistance of the low-bit sub-digital-to-analog converter and the unit resistance of the high-bit thermometer code.

FIG2 shows a calibration circuit, wherein the amplifier is any conventional circuit. The output of the DAC is connected to the left side of capacitor C1, the right side of capacitor C1 is connected to the inverting input terminal of the amplifier, the voltage of the positive input terminal of the amplifier is V _cm , the output of the amplifier is connected to the calibration logic, the output of the calibration logic is connected to the DAC, and controls the input signal D[M+N-1:N] and THM[i:2 ^M -1] of the DAC. The switch S1 is connected in parallel with the amplifier.

The direction of the resistor mismatch is obtained through the calibration logic and the amplifier, so that the resistor value is adjusted to reduce the mismatch. During the calibration process, the calibration logic output CAL_EN is set to 1, and the digital-to-analog converter will receive the digital signal sent from the calibration logic.

During calibration, first, switch S1 is turned on, and the DAC input is configured as D[M+N-1:N]=0, D[N-1:0]=1, and D_CAL=1. At this time, the DAC output voltage is Due to the negative feedback loop, the input voltage of the amplifier is V _cm , and the voltage difference on capacitor C1 is V _OUT1 -V _cm . Then switch S1 is disconnected, and D[N-1:0]=0, D_CAL=0 are configured, and the input of the binary-to-thermometer decoder & selector is configured as THM[i]=1, THM[1:i-1]=0, THM[i:2 ^M -1]=0, where i=1,2,…,2 ^M -1. Since switch S1 is disconnected, the negative feedback loop of the amplifier is disconnected, so the voltage difference on capacitor C1 will remain unchanged. At this time, the output voltage of the digital-to-analog converter becomes Then the input voltage of the amplifier's reverse input terminal becomes V _cm +V _OUT2 -V _OUT1 , and the voltage difference between the positive and negative ends of the amplifier is So if If the value of is greater than 0, the amplifier outputs a high voltage (logic 1); if the value is less than 0, the amplifier outputs a low voltage (logic 0).

The calibration logic will make a judgment based on the output value of the amplifier to adjust the size of the resistor R _i in the thermometer code sub-DAC. If the amplifier outputs logic 1, it means that the resistor R _i is too large and the resistor R _i needs to be reduced; if the amplifier outputs logic 0, it means that the resistor R _i is too small and the resistor R _i needs to be increased. The resistor R _i can be adjusted using a switch-controlled resistor array.

According to the above method, i=1 to i= ^2M -1 resistors are calibrated at a time, and after calibration, the resistance in the thermometer code sub-DAC will be equal to the output resistance of the binary sub-DAC, so that when the low-order N bits are switched to the high-order M bits, the output voltage will not be nonlinear due to the resistance mismatch caused by the manufacturing process.

The specific steps of calibration of the present invention are:

Step 1: Configure the calibration logic CAL_EN=1, and set the calibration logic internal register record=0, i=0.

Step 2: The calibration logic configuration switch S1 is turned on, and the digital-to-analog converter input is configured to be D[M+N-1:N]=0, D[N-1:0]=1, and D_CAL=1.

Step 3: Configure switch S1 to be disconnected. After the switch is disconnected, configure D[N-1:0]=0, D_CAL=0, and configure the input of the binary-to-thermometer decoder & selector to THM[i]=1, THM[1:i-1]=0, THM[i:2 ^M -1]=0.

Step 4: Detect the logic output of the amplifier. If it is high, record = record + 1. If it is low and record > 0, record = record - 1.

Step 5: Repeat steps 2 to 4 for a total of 4 times. If record>2, reduce the resistance R _i ; if record<2, increase the resistance R _i ; if record＝2, keep the resistance R _i unchanged, reset record to 0, i＝i+1, and proceed to the next step.

Step 6: Repeat steps 2 to 5 to traverse the resistors from i = 1 to i = 2 ^M -1. After the traversal is completed, the calibration ends and CAL_EN = 0 and D_CAL = 0 are configured.

This embodiment is only a preferred specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (3)

1. A resistance mismatch calibration method for a resistance type digital-to-analog converter, wherein the resistance type digital-to-analog converter is composed of a binary sub-digital-to-analog converter of a low-bit D[N-1:0] bit and an M-bit thermometer code sub-digital-to-analog converter of a high-bit D[M+N-1:N]; the output of the digital-to-analog converter is connected to the left side of a capacitor C1, the right side of the capacitor C1 is connected to the reverse input terminal of an amplifier, the voltage of the positive input terminal of the amplifier is V _cm , the output of the amplifier is connected to a calibration logic, the output of the calibration logic is connected to the digital-to-analog converter, and controls the input signals D[M+N-1:N] and THM[i:2 ^M -1] of the digital-to-analog converter, the switch S1 is connected in parallel with the amplifier, and the calibration comprises the following steps: Step 1: Set the calibration logic configuration CAL_EN=1, set the calibration logic internal register record=0, i=0; Step 2: The calibration logic configuration switch S1 is turned on, and the digital-to-analog converter input is configured to be D[M+N-1:N]=0, D[N-1:0]=1, and D_CAL=1; Step 3: Configure switch S1 to be disconnected. After switch S1 is disconnected, configure D[N-1:0]=0, D_CAL=0, and configure the input of the binary-to-thermometer decoder & selector to THM[i]=1, THM[1:i-1]=0, THM[i:2 ^M -1]=0; Step 4: Detect the logic output of the amplifier, if it is high, record = record + 1, if it is low and record>0, record = record-1; Step 5: Repeat steps 2 to 4 for a total of 4 times. If record>2, reduce the resistance R _i ; if record<2, increase the resistance R _i ; if record＝2, keep the resistance R _i unchanged; reset record to 0, i＝i+1, and proceed to the next step; Step 6: Repeat steps 2 to 5 to traverse the resistances from i=1 to i=2 ^M -1. After the traversal is completed, the calibration is terminated and CAL_EN=0 and D_CAL=0 are configured. 2 . The resistance mismatch calibration method of a resistance-type digital-to-analog converter according to claim 1 , wherein the resistor R _i is adjusted using a switch-controlled resistor array. 3. A resistance mismatch calibration circuit for a resistive digital-to-analog converter, characterized in that: the output of the digital-to-analog converter is connected to the left side of a capacitor C1, the right side of the capacitor C1 is connected to the reverse input terminal of an amplifier, the voltage of the positive input terminal of the amplifier is V _cm , the output of the amplifier is connected to a calibration logic, the output of the calibration logic is connected to the digital-to-analog converter and controls the input signals D[M+N-1:N] and THM[i:2 ^M -1] of the digital-to-analog converter, the switch S1 is connected in parallel with the amplifier, and the calibration circuit calibrates the resistance mismatch by using the method described in any one of claims 1 to 2 when in use.