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CN114093763B - 半导体的制作方法 - Google Patents

半导体的制作方法 Download PDF

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CN114093763B
CN114093763B CN202111397145.6A CN202111397145A CN114093763B CN 114093763 B CN114093763 B CN 114093763B CN 202111397145 A CN202111397145 A CN 202111397145A CN 114093763 B CN114093763 B CN 114093763B
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layer
dielectric layer
etching
deposition
opening
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CN114093763A (zh
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谢岩
刘选军
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Integrated Circuit Co ltd
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Abstract

本发明提供一种半导体的制作方法，包括：提供衬底，在衬底上依次形成第一介质层、第二介质层和第三介质层，第三介质层具有初始开口；形成第一沉积层，第一沉积层至少覆盖初始开口的侧壁表面；刻蚀第一开口正下方的第二介质层，至暴露出第二介质层的侧壁；形成第二沉积层，第二沉积层至少覆盖第一开口的侧壁和暴露出的第二介质层的侧壁；刻蚀第二开口正下方的第一介质层至暴露出衬底；刻蚀衬底，形成沟槽。本发明将沉积与刻蚀工艺分离，形成第一沉积层，以缩小待刻蚀的第二介质层的宽度；形成第二沉积层，以缩小待刻蚀的第一介质层的宽度，逐层传递以缩小最终形成的沟槽的关键尺寸；以较低成本形成小尺寸的深沟槽隔离(DTI)，提升了成像质量。

Description

半导体的制作方法
技术领域
本发明属于集成电路制造技术领域，具体涉及一种半导体的制作方法。
背景技术
图像传感器广泛地用于数字静态相机、蜂窝式电话、安全摄像机以及医学、汽车及其它应用中。由于对更高解析度、更低电力消耗、增大动态范围等的不断增加的需求，图像传感器的装置架构已持续快速地发展。这些需求也已促进了图像传感器在这些装置中的进一步小型化及集成。
图像传感器包含多个光敏元件，来自外部场景的图像光入射于图像传感器上，使得每一光敏元件吸收一部分入射图像光。图像传感器中所包含的光敏元件(例如光电二极管)各自在吸收图像光之后产生图像电荷。所产生的图像电荷量与图像光的强度成比例。所产生的图像电荷可用于表示外部场景的图像。
图像传感器通过在光敏元件之间加入深沟槽隔离(DTI)，避免相邻光敏元件之间的串扰，提高图像传感器的电子隔离功能，从而提高成像的质量，而通过做更小尺寸的深沟槽隔离(DTI)工艺可以提高图像传感器成像的质量，同时相同面积可以做更多光敏元件，从而提高像素。图像传感器的小型化可致使邻近光敏元件之间的距离减小，因此对深沟槽隔离(DTI)的小尺寸提出迫切需求。
但是做小尺寸的深沟槽隔离，亦即减小深沟槽隔离(DTI)的关键尺寸(CD)，需要更昂贵的光刻胶和更精确的工艺控制，对成本增加很大，需要找到一种更合适的制作方法。
发明内容
本发明的目的在于以较低成本形成小尺寸的深沟槽隔离(DTI)半导体器件，提升半导体器件的成像质量。
本发明提供一种半导体的制作方法，包括：
提供衬底，在所述衬底上依次形成第一介质层、第二介质层和第三介质层，所述第三介质层具有初始开口；
形成第一沉积层，所述第一沉积层至少覆盖所述初始开口的侧壁表面，以形成具有第一开口的第一掩膜层；
以所述第一掩膜层为掩膜进行第一次刻蚀，去除所述第一开口正下方的所述第二介质层至暴露出所述第二介质层的侧壁；
形成第二沉积层，所述第二沉积层至少覆盖所述第一开口的侧壁和暴露出的所述第二介质层的侧壁，以形成具有第二开口的第二掩膜层；
以所述第二掩膜层为掩膜进行第二次刻蚀，去除所述第二开口正下方的第一介质层至暴露出所述衬底；
去除所述第二掩膜层，以具有所述第二开口的所述第一介质层为掩膜刻蚀所述衬底，形成沟槽。
进一步的，形成所述第一掩膜层、进行所述第一次刻蚀、形成所述第二掩膜层以及进行所述第二次刻蚀的步骤均在同一蚀刻机台中完成。进一步的，形成所述第一沉积层的工艺参数：沉积气体包括C4F8，源功率：800～1200W，偏置电压：250～400V，沉积气体的流量100～500sccm。
进一步的，所述初始开口的侧壁上形成的所述第一沉积层的厚度大于等于200nm。
进一步的，刻蚀所述第一开口正下方的第二介质层的工艺参数：刻蚀气体包括CF4，源功率：600～800W，偏置电压：250～400V。
进一步的，形成所述第二沉积层的工艺为：沉积气体包括C4F8，源功率：800～1200W，偏置电压：250～400V，沉积气体的流量200～600sccm。
进一步的，刻蚀所述第二开口正下方的所述第一介质层的工艺参数：刻蚀气体包括CO、O2，Ar2，源功率：800～1500W，偏置电压：200～400V。
进一步的，去除所述第二掩膜层包括：所述第二沉积层、所述第一沉积层和所述第三介质层均使用O2等离子体灰化或者剥离液浸泡去除，所述第二介质层采用草酸湿法刻蚀去除。
进一步的，刻蚀所述衬底采用刻蚀和钝化交替进行，刻蚀气体包括SF6，钝化气体包括C4F8。
进一步的，刻蚀所述衬底的工艺中，所述钝化工艺参数包括：钝化气体C4F8，钝化时间10-30s，电源功率450-600W，C4F8流量10-20sccm，压力3-10mtor，温度30-50℃，偏置电压：60～100V；所述刻蚀工艺参数具体包括：刻蚀气体SF6，刻蚀时间30-50s，电源功率300-400W，SF6流量30-50sccm，压力3-10mtor，温度30-50℃。
进一步的，所述第一介质层为底部抗反射层，所述第二介质层为低温氧化层，所述第三介质层为光阻层。
与现有技术相比，本发明具有如下有益效果：
本发明提供一种半导体的制作方法，包括：提供衬底，在所述衬底上依次形成第一介质层、第二介质层和第三介质层，所述第三介质层具有初始开口；形成第一沉积层，所述第一沉积层至少覆盖所述初始开口的侧壁表面，以形成具有第一开口的第一掩膜层；以所述第一掩膜层为掩膜进行第一次刻蚀，去除所述第一开口正下方的所述第二介质层至暴露出所述第二介质层的侧壁；形成第二沉积层，所述第二沉积层至少覆盖所述第一开口的侧壁和暴露出的所述第二介质层的侧壁，以形成具有第二开口的第二掩膜层；以所述第二掩膜层为掩膜进行第二次刻蚀，去除所述第二开口正下方的第一介质层至暴露出所述衬底；去除所述第二掩膜层，以具有所述第二开口的所述第一介质层为掩膜刻蚀所述衬底，形成沟槽。
本发明将沉积与刻蚀工艺分离，形成第一沉积层，以缩小待刻蚀的第二介质层的宽度；形成第二沉积层，以缩小待刻蚀的第一介质层的宽度，逐层传递用于缩小最终形成的沟槽的关键尺寸(CD)；亦即在第一介质层、第二介质层和第三介质层三层结构中通过插入两步沉积工艺来有效缩小沟槽的关键尺寸(CD)。以较低成本形成小尺寸的深沟槽隔离(DTI)，相同面积可以做更多光敏元件，从而提高像素，提升成像质量。
附图说明
图1为本发明实施例的一种半导体的制作方法流程示意图。
图2为本发明实施例的制作方法中形成第三介质层后的示意图。
图3为本发明实施例的制作方法中形成第一沉积层后的示意图。
图4为本发明实施例的制作方法中刻蚀第二介质层后的示意图。
图5为本发明实施例的制作方法中形成第二沉积层后的示意图。
图6为本发明实施例的制作方法中刻蚀第一介质层后的示意图。
图7为本发明实施例的制作方法中去除第二介质层和第三介质层后的示意图。
图8为本发明实施例的制作方法中刻蚀衬底后的示意图。
图9为本发明实施例的制作方法中去除第一介质层后的示意图。
其中，附图标记如下：
11-衬底；12-氧化层；13-第一介质层；14-第二介质层；15-第三介质层；16-第一沉积层；17-第二沉积层。
具体实施方式
基于上述研究，本发明实施例提供了一种半导体的制作方法。以下结合附图和具体实施例对本发明进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需要说明的是，附图均采用非常简化的形式且使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明实施例提供了一种半导体的制作方法，如图1所示，包括：
S1、提供衬底，在所述衬底上依次形成第一介质层、第二介质层和第三介质层，所述第三介质层具有初始开口；
S2、形成第一沉积层，所述第一沉积层至少覆盖所述初始开口的侧壁表面，以形成具有第一开口的第一掩膜层；
S3、以所述第一掩膜层为掩膜进行第一次刻蚀，去除所述第一开口正下方的所述第二介质层至暴露出所述第二介质层的侧壁；
S4、形成第二沉积层，所述第二沉积层至少覆盖所述第一开口的侧壁和暴露出的所述第二介质层的侧壁，以形成具有第二开口的第二掩膜层；
S5、以所述第二掩膜层为掩膜进行第二次刻蚀，去除所述第二开口正下方的第一介质层至暴露出所述衬底；
S6、去除所述第二掩膜层，以具有所述第二开口的所述第一介质层为掩膜刻蚀所述衬底，形成沟槽。
下面结合图2至图9详细介绍本发明实施例的半导体的制作方法的各步骤。
如图2所示，步骤S1中，提供衬底11，衬底11上可形成有氧化层12，在所述氧化层12上依次形成第一介质层13、第二介质层14和第三介质层15，所述第三介质层15具有初始开口K0，所述初始开口K0暴露出第二介质层14。初始开口K0的数量根据实际需要设置，初始开口K0在垂直于衬底的截面上的截面宽度为D0，初始开口K0的截面宽度D0为光刻机能制作出的最小宽度。
在一实施例中，第一介质层13例如为底部抗反射层(BARC，Bottom Anti-Reflective Coating)；第二介质层14例如为低温氧化层(LTO，Low Temperature Oxide)、氮化硅层、碳化硅层、氮化钛层、氮化钽层、氧化钛层以及氧化钽层中的一种或两种以上组合。第三介质层15例如为光阻层，由曝光、显影步骤而被图案化，形成具有既定形状的图案，形成贯穿光阻层的初始开口K0。第一介质层13例如为底部抗反射层，可以在图案化光阻层时降低光反射。可替换性的，第三介质层15还可为多晶硅层、氧化硅层、氮化硅层和碳化硅层中的一种或两种以上组合。可通过化学气相沉积形成该第三介质层15。通过在第三介质层15上形成光阻层，再采用带有图形的掩模版对所述光阻层进行曝光、显影等，以形成图形化光阻层，该图形化光阻层中的图形定义出初始开口K0；然后以所述图形化光阻层为掩膜，采用刻蚀工艺图形化所述第三介质层15，形成贯穿所述第三介质层15的初始开口K0，之后去除图形化光阻层。
在另一实施例中，第一介质层13例如为氧化硅层、第二介质层14例如为氮化硅层，第三介质层15例如为氧化硅层，构成ONO(氧化硅层-氮化硅层-氧化硅层)叠层结构；第一介质层13、第二介质层14、第三介质层15还可以是其他任意材料的组合。
如图3和图4所示，步骤S2中，形成第一沉积层16，所述第一沉积层16至少覆盖所述初始开口K0的侧壁表面，以形成具有第一开口K1的第一掩膜层，具有第一开口K1的第一沉积层16以及图形化的第三介质层共同构成第一掩膜层；第一开口K1在垂直于衬底11的截面上的截面宽度为D1，宽度D1亦即第一开口K1的两侧壁上的第一沉积层16的间距，应当理解待刻蚀的第二介质层14后续被刻蚀后在垂直于衬底的截面上的刻蚀开口截面宽度也为D1。本步骤通过在初始开口K0中形成第一沉积层16以缩小待刻蚀的第二介质层14的宽度D1，用于缩小最终形成的沟槽的关键尺寸(CD)。第一沉积层16还可覆盖初始开口K0暴露出的第二介质层14的表面。
第一沉积层16可通过沉积工艺形成，沉积气体包括C4F8，源功率：800～1200W，偏置电压：250～400V。使包含C4F8的沉积气体从气体源流入等离子体处理腔室。在一个示例中，该沉积气体是由纯净的C4F8组成的，沉积气体的流量：100～500sccm。将该沉积气体转化为沉积等离子体，提供该沉积约30秒。然后停止沉积该沉积层，保持90～150毫托(mtorr)的压强。优选地，提供沉积至少20秒。更优选地，提供沉积至少25秒。最优选地，提供沉积至少30秒。优选地，侧壁上的第一沉积层至少200nm厚。更优选地，侧壁上的第一沉积层至少300nm厚。
如图4所示，步骤S3中，以所述第一掩膜层为掩膜进行第一次刻蚀，去除所述第一开口K1正下方的所述第二介质层14至暴露出所述第二介质层14的侧壁。具体刻蚀第一开口K1正下方的第二介质层14，至暴露出所述第一介质层13。刻蚀气体包括CF4，源功率：600～800W，偏置电压：250～400V。
如图5和图6所示，步骤S4中，形成第二沉积层17，所述第二沉积层17至少覆盖第一开口K1的侧壁和暴露出的第二介质层14的侧壁，以形成具有第二开口K2的第二掩膜层；具体的，第二介质层14、第三介质层15、第一沉积层16和第二沉积层17共同构成第二掩膜层。本步骤通过形成第二沉积层17，以缩小待刻蚀的第一介质层13的宽度D2，用于缩小最终形成的沟槽的关键尺寸(CD)。该宽度D2具体指待刻蚀的第一介质层13后续被刻蚀后在垂直于衬底的截面上刻蚀开口的截面宽度，宽度D2也为第二开口K2的截面宽度，宽度D2亦即第二开口K2的两侧壁上的第二沉积层17的间距。第二沉积层17可通过沉积工艺形成，沉积气体包括C4F8，源功率：800～1200W，偏置电压：250～400V。
如图6和图7所示，步骤S5中，以所述第二掩膜层为掩膜进行第二次刻蚀，去除所述第二开口K2正下方的第一介质层13至暴露出所述衬底11。具体刻蚀第二开口K2正下方的第一介质层13和氧化层12，至暴露出所述衬底11。刻蚀气体包括CO、O2，Ar2，源功率：800～1500W，偏置电压：200～400V。
本实施例中形成所述第一掩膜层、进行所述第一次刻蚀、形成所述第二掩膜层以及进行所述第二次刻蚀的步骤均在同一蚀刻机台中完成，也称为原位刻蚀，避免了现有工艺中形成掩膜层与刻蚀分别在不同机台，转移机台引起的步骤增加以及工序时长增加等问题。
继续如图6和图7所示，步骤S6中，去除所述第二掩膜层，以具有所述第二开口K2的所述第一介质层13为掩膜刻蚀所述衬底11，形成沟槽V。去除所述第二掩膜层具体去除第二介质层14、第三介质层15、第一沉积层16和第二沉积层17。可使用O2等离子体灰化或者剥离液浸泡去除第二沉积层17、第一沉积层16和第三介质层15。第一沉积层16和第二沉积层17均是C4F8形成的有机聚合物，O2等离子体灰化或者剥离液浸泡都能去除该有机聚合物。所述O2等离子体灰化工艺参数为：处理时间60-120s，电源功率300-400W，O2流量300-500sccm，压力10-30mt，温度30-50℃。所述剥离液，可以选择NMP剥离液浸泡120-240s。N-甲基吡咯烷酮，英文名称N-Methyl pyrrolidone，即NMP，是重要的化工原料，是一种选择性强和稳定性好的极性溶剂。第二介质层14可采用湿法刻蚀去除，示例性的，采用草酸湿法刻蚀去除第二介质层14，湿法刻蚀时间20-50s，草酸浓度2-10wt％。
如图8和图9所示，以具有所述第二开口K2的所述第一介质层13为掩膜刻蚀所述衬底11，形成沟槽V。在垂直于衬底的截面上，沟槽V的截面宽度为D，沟槽V的截面宽度为D近似等于第二开口K2的截面宽度D2，在刻蚀过程中由少许侧向刻蚀导致二者的偏差。沟槽V的截面宽度为D可作为沟槽的关键尺寸。刻蚀衬底11可采用Bosch工艺，刻蚀气体包括SF6，钝化气体包括C4F8。Bosch工艺是指在集成电路制造中为了阻止或减弱侧向刻蚀，设法在刻蚀的侧向边壁沉积一层刻蚀薄膜的工艺。首先采用氟基活性基团进行硅的刻蚀，然后进行侧壁钝化，刻蚀和钝化两步工艺交替进行。通过交替转换刻蚀气体与钝化气体实现刻蚀与边壁钝化。C4F8在等离子体中能够形成氟化碳类高分子聚合物，沉积在硅表面能够阻止氟离子与硅的反应。刻蚀与钝化每5～10s转换一个周期。在短时间的各向同性刻蚀之后即将刚刚刻蚀过的硅表面钝化。在深度方向由于有离子的物理溅射轰击，钝化膜可以保留下来，这样下一个周期的刻蚀就不会发生侧向刻蚀。通过这种周期性“刻蚀-钝化-刻蚀”，刻蚀只沿着深度方向进行，最终形成沟槽V，该沟槽例如为深沟槽，在深沟槽中填充隔离层，形成深沟槽隔离(DPI)。沟槽V的深度至少为500nm。更优选地，沟槽V的深度至少为1000nm。优选地，沟槽V的深度与宽度的纵横比至少为5：1。更优选地，沟槽V的纵横比至少为10：1。
刻蚀衬底11形成沟槽V的工艺中，示例性的，沉积(钝化)工艺参数具体包括：沉积气体C4F8，沉积时间10-30s，电源功率450-600W，C4F8流量10-20sccm，压力3-10mtor，温度30-50℃，偏置电压：60～100V。Bosch工艺中C4F8主要用来形成侧壁保护聚合物，保护侧壁不被损伤。刻蚀工艺参数具体包括：刻蚀气体SF6，刻蚀时间30-50s，电源功率300-400W，SF6流量30-50sccm，压力3-10mtor，温度30-50℃。
如图9所示，去除第一介质层13，可通过干法刻蚀工艺去除。刻蚀气体包括CO、O2，Ar2，源功率：800～1500W，偏置电压：200～400V。至此在衬底中形成小尺寸的深沟槽隔离(DTI)半导体器件，该半导体器件可用作图像传感器以及其他需要沟槽隔离的器件。相同面积可以做更多光敏元件，从而提高像素，提升半导体器件的成像质量。
综上所述，本发明提供一种半导体的制作方法，包括：提供衬底，在衬底上依次形成第一介质层、第二介质层和第三介质层，第三介质层具有初始开口；形成第一沉积层，第一沉积层至少覆盖初始开口的侧壁表面；刻蚀第一开口正下方的第二介质层，至暴露出第二介质层的侧壁；形成第二沉积层，第二沉积层至少覆盖第一开口的侧壁和暴露出的第二介质层的侧壁；刻蚀第二开口正下方的第一介质层至暴露出衬底；刻蚀衬底，形成沟槽。本发明将沉积与刻蚀工艺分离，形成第一沉积层，以缩小待刻蚀的第二介质层的宽度；形成第二沉积层，以缩小待刻蚀的第一介质层的宽度，逐层传递以缩小最终形成的沟槽的关键尺寸；以较低成本形成小尺寸的深沟槽隔离(DTI)，提升了成像质量。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的方法而言，由于与实施例公开的器件相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (10)

1.一种半导体的制作方法，其特征在于，包括：
提供衬底，在所述衬底上依次形成第一介质层、第二介质层和第三介质层，所述第三介质层具有初始开口；
形成第一沉积层，所述第一沉积层至少覆盖所述初始开口的侧壁表面，以形成具有第一开口的第一掩膜层；
以所述第一掩膜层为掩膜进行第一次刻蚀，去除所述第一开口正下方的所述第二介质层至暴露出所述第二介质层的侧壁；
形成第二沉积层，所述第二沉积层至少覆盖所述第一开口的侧壁和暴露出的所述第二介质层的侧壁，以形成具有第二开口的第二掩膜层；
以所述第二掩膜层为掩膜进行第二次刻蚀，去除所述第二开口正下方的第一介质层至暴露出所述衬底；
去除所述第二掩膜层，以具有所述第二开口的所述第一介质层为掩膜刻蚀所述衬底，形成沟槽; 其中，去除所述第二掩膜层包括：所述第二沉积层、所述第一沉积层和所述第三介质层均使用O2等离子体灰化或者剥离液浸泡去除，所述第二介质层采用草酸湿法刻蚀去除。
2.如权利要求1所述的半导体的制作方法，其特征在于，
形成所述第一掩膜层、进行所述第一次刻蚀、形成所述第二掩膜层以及进行所述第二次刻蚀的步骤均在同一蚀刻机台中完成。
3.如权利要求1所述的半导体的制作方法，其特征在于，形成所述第一沉积层的工艺参数：沉积气体包括C4F8，源功率：800~1200W，偏置电压：250~400V，沉积气体的流量100~500sccm。
4.如权利要求1所述的半导体的制作方法，其特征在于，所述初始开口的侧壁上形成的所述第一沉积层的厚度大于等于200nm。
5.如权利要求1所述的半导体的制作方法，其特征在于，刻蚀所述第一开口正下方的第二介质层的工艺参数：刻蚀气体包括CF4，源功率：600~800W，偏置电压：250~400V。
6.如权利要求1所述的半导体的制作方法，其特征在于，形成所述第二沉积层的工艺为：沉积气体包括C4F8，源功率：800~1200W，偏置电压：250~400V，沉积气体的流量200~600sccm。
7.如权利要求1所述的半导体的制作方法，其特征在于，刻蚀所述第二开口正下方的所述第一介质层的工艺参数：刻蚀气体包括CO、O2，Ar2，源功率：800~1500W ，偏置电压：200~400V。
8.如权利要求1所述的半导体的制作方法，其特征在于，刻蚀所述衬底采用刻蚀和钝化交替进行，刻蚀气体包括SF6，钝化气体包括C4F8。
9.如权利要求8所述的半导体的制作方法，其特征在于，刻蚀所述衬底的工艺中，所述钝化工艺参数包括：钝化气体C4F8，钝化时间10-30s，电源功率450-600W，C4F8流量10-20sccm，压力3-10mtor，温度30-50℃，偏置电压：60~100V；所述刻蚀工艺参数具体包括：刻蚀气体SF6，刻蚀时间30-50s，电源功率300-400W，SF6流量30-50sccm，压力3-10mtor，温度30-50℃。
10.如权利要求1-9任意一项所述的半导体的制作方法，其特征在于，
所述第一介质层为底部抗反射层，所述第二介质层为低温氧化层，所述第三介质层为光阻层。
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CN112466900A (zh) * 2020-12-23 2021-03-09 上海集成电路装备材料产业创新中心有限公司 图像传感器及其深沟槽的制作方法

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US9257282B2 (en) * 2014-05-02 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US10535558B2 (en) * 2016-02-09 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
CN107910339B (zh) * 2017-10-26 2021-01-29 上海集成电路研发中心有限公司 一种背照式图形传感器的制造方法
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* Cited by examiner, † Cited by third party
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CN112466900A (zh) * 2020-12-23 2021-03-09 上海集成电路装备材料产业创新中心有限公司 图像传感器及其深沟槽的制作方法

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