CN114068670A

CN114068670A - Semiconductor structure and method of forming the same

Info

Publication number: CN114068670A
Application number: CN202110422809.3A
Authority: CN
Inventors: 陈柏安
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2020-07-29
Filing date: 2021-04-19
Publication date: 2022-02-18
Anticipated expiration: 2041-04-19
Also published as: TW202205388A; TWI746094B; CN114068670B

Abstract

The present invention provides a semiconductor structure and a method for forming the same. The method includes: sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A patterned hard mask layer is formed on the semiconductor layer. The patterned hard mask layer is used as an etching mask, and the semiconductor layer and the epitaxial layer are etched, so that the epitaxial layer has grooves. Remove the patterned hardmask layer. A first electrode dielectric layer is formed on the sidewall and bottom surface of the groove and on the semiconductor layer, so that the first electrode dielectric layer has a groove. A first electrode is formed in the trench. A pair of second electrodes are formed on the first electrodes so that the pair of second electrodes are disposed corresponding to each other along the horizontal direction. A third electrode is formed on the pair of second electrodes.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to a semiconductor structure and a method for forming the same, and more particularly, to a semiconductor structure including a mask electrode disposed in a horizontal direction and a method for forming the same.

Background

Due to the existence of the trench structure in the trench metal-oxide-semiconductor field effect transistor (trench MOSFET), the trench MOSFET has a smaller unit cell length (unit cell pitch) and a lower gate-drain capacitance (Cgd), so that the on-resistance (Ron) and the switching loss (switching loss) can be effectively reduced. However, as user demands increase, transistors are expected to have smaller size, faster response speed and lower switching loss, and the size of the transistors needs to be reduced, even though the gate-drain charge (Qgd) or the gate-drain capacitance cannot be effectively reduced, so that the switching speed is not significantly improved.

Therefore, Shielded Gate Trench (SGT) MOSFETs have been developed. The SGT-MOSFET has a source electrode as a shielding electrode (shielding electrode), that is, a source shielding structure disposed therein. Therefore, the SGT-MOSFET can be based on a charge balance technique to achieve lower on-resistance and better switching performance.

However, existing semiconductor structures and methods of forming them have been developed to meet their intended use, but they have not yet been completely satisfactory in every aspect. Accordingly, there are still some problems to be overcome with respect to semiconductor structures that can be used as SGT-MOSFETs after further processing and methods of forming the same.

Disclosure of Invention

In view of the above problems, the present invention provides a shielding structure (shielding structure) by providing a plurality of electrodes as shielding electrodes (shielding electrodes). In particular, a pair of electrodes horizontally disposed, that is, a separated spacer electrode (separated spacer electrode) structure in the horizontal direction is further included in the plurality of electrodes disposed, so that the electric field and the electric charge in the semiconductor structure are more uniform to obtain more excellent electrical characteristics.

According to some embodiments, a method of forming a semiconductor structure is provided. The method for forming the semiconductor structure comprises the following steps: an epitaxial layer and a semiconductor layer are sequentially formed on a substrate. A patterned hard mask layer is formed on the semiconductor layer. And using the patterned hard mask layer as an etching mask, and etching the semiconductor layer and the epitaxial layer to enable the epitaxial layer to be provided with a groove. The patterned hard mask layer is removed. A first electrode dielectric layer is formed on the side wall and the bottom surface of the groove and on the semiconductor layer, so that the first electrode dielectric layer is provided with a groove. A first electrode is formed in the trench. A pair of second electrodes is formed on the first electrode such that the pair of second electrodes are disposed corresponding to each other along a horizontal direction. Forming a third electrode on the pair of second electrodes.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: the semiconductor device comprises a substrate, an epitaxial layer, a semiconductor layer, a first electrode dielectric layer, a first electrode, a second electrode and a third electrode. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type. The epitaxial layer is arranged on the substrate and is provided with a groove. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is disposed on the epitaxial layer. The first electrode dielectric layer is arranged on the side wall and the bottom surface of the groove and is arranged on the semiconductor layer. The first electrode dielectric layer has a trench. The first electrode is disposed in the trench. The pair of second electrodes is disposed on the first electrode. The pair of second electrodes correspond to each other along the horizontal direction. And a third electrode disposed on the pair of second electrodes.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices, and in order to make the features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.

FIGS. 1-12 are schematic cross-sectional views illustrating the formation of a semiconductor structure at various stages, in accordance with some embodiments of the present invention; and

fig. 13-18 are cross-sectional views illustrating an SGT-MOSFET formed in various stages as one embodiment of the invention, based on the semiconductor structure shown in fig. 12, in accordance with some embodiments of the invention.

Reference numerals:

1: semiconductor structure

100: substrate

200: epitaxial layer

210: groove

300: semiconductor layer

310: first doped region

320: second doped region

330: contact plug

400: patterned hard mask layer

500: first electrode dielectric layer

510: second electrode dielectric layer

520: third electrode dielectric layer

600: a first electrode

700: second electrode

710: electrode material layer

800: third electrode

900: interlayer dielectric layer

910: metal layer

CT: contact via

D1: in the vertical direction

D2: in the horizontal direction

OP: opening of the container

S1, S2: distance between each other

T: groove

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different elements of the provided semiconductor structures. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

In this context, the respective directions are not limited to three axes like an x-axis, a y-axis and a z-axis of a rectangular coordinate system, and can be explained in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For convenience of explanation, hereinafter, the y-axis direction is referred to as a vertical direction D1 and the x-axis direction is referred to as a horizontal direction D2 when viewed in a cross-sectional view.

Fig. 1-12 are cross-sectional views illustrating the formation of a semiconductor structure 1 at various stages, in accordance with some embodiments of the present invention.

Referring to fig. 1, an epitaxial layer 200 and a semiconductor layer 300 are sequentially formed on a substrate 100. The epitaxial layer 200 may be disposed on the substrate 100. The semiconductor layer 300 may be disposed on the epitaxial layer 200. The substrate 100, the epitaxial layer 200, and the semiconductor layer 300 may be individually extended. The substrate 100, the epitaxial layer 200, and the semiconductor layer 300 may be parallel to each other.

The substrate 100 may be a bulk semiconductor (bulk) or a semiconductor-on-insulator (SOI) substrate. The substrate 100 may be a wafer, such as a silicon wafer. Generally, an soi substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or similar material, which is provided on a silicon or glass substrate. Other substrate types include, for example, multi-layer or gradient substrates.

The substrate 100 may be an elemental semiconductor comprising silicon (silicon), germanium (germanium); the substrate 100 may also be a compound semiconductor, which includes: for example, but not limited to, silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide); the substrate 100 may also be an alloy semiconductor, which includes: for example, but not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or any combination thereof.

Epitaxial layer 200 may comprise silicon, germanium, silicon and germanium, a group III-V compound, or combinations thereof. The epitaxial layer 200 may be formed by an epitaxial growth (epitaxial growth) process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic chemical vapor deposition (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), Remote Plasma Chemical Vapor Deposition (RPCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Liquid Phase Epitaxy (LPE), chloride Vapor Phase Epitaxy (VPE), or the like.

In some embodiments, the substrate 100 and the epitaxial layer 200 have a first conductivity type, and the semiconductor layer 300 has a second conductivity type different from the first conductivity type. For example, if the substrate 100 and the epitaxial layer 200 have the first conductivity type of N type, the semiconductor layer 300 has the second conductivity type of P type; on the contrary, if the substrate 100 and the epitaxial layer 200 have the first conductivity type of P-type, the semiconductor layer 300 has the second conductivity type of N-type. The first conductive type and the second conductive type can be adjusted according to requirements, and meanwhile, the doping concentration, the doping depth and the size of the doped region can also be adjusted according to requirements. In some embodiments, the substrate 100 and the epitaxial layer 200 have N-type conductivity; and the semiconductor layer 300 has a P-type conductivity type. In some embodiments, the semiconductor layer 300 may be formed after the third electrode is formed.

Referring to fig. 2, a patterned hard mask layer 400 is formed on the semiconductor layer 300. The patterned hard mask layer 400 includes an opening OP. The opening OP of the patterned hard mask layer 400 exposes a portion of the upper surface of the semiconductor layer 300.

The patterned hard mask layer 400 may comprise an oxide, a nitride, or a combination thereof. In some embodiments, the oxide layer may comprise: for example, an oxide or other suitable oxide with Tetraethoxysilane (TEOS) as a precursor. The nitride may comprise (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or other suitable nitrides. It is understood that the hard mask material can be suitably matched according to the process conditions, and thus the embodiment of the invention is not limited thereto.

In some embodiments, the patterned hard mask layer 400 is an oxide. In some embodiments, the step of forming the patterned hard mask layer 400 on the semiconductor layer 300 may further comprise: an oxide layer is deposited as a hard mask layer on the semiconductor layer 300, a photoresist layer is formed on the oxide layer, and the photoresist layer is exposed as required to obtain a patterned photoresist layer. Then, the patterned photoresist layer is used as an etching mask, and the oxide layer is etched to form a patterned oxide layer. Then, the patterned photoresist layer is removed to obtain a patterned hard mask layer 400 on the semiconductor layer 300. The oxide layer may be deposited by Chemical Vapor Deposition (CVD), or other suitable process. The photoresist layer may be removed using ashing (ashing) and/or wet etching (wet strip) processes.

Referring to fig. 3, the semiconductor layer 300 and the epitaxial layer 200 are etched using the patterned hard mask layer 400 as an etch mask, so that the epitaxial layer 200 has a recess 210. In one embodiment, the portion of the semiconductor layer 300 corresponding to the opening OP is removed such that the etched semiconductor layer 300 is penetrated. Further, the portion of the epitaxial layer 200 corresponding to the opening OP is removed, but the etched epitaxial layer 200 is not penetrated, so that the epitaxial layer 200 can have the groove 210. In one embodiment, the semiconductor layer 300 is disposed on the epitaxial layer 200, but not on the recess 210. In one embodiment, the semiconductor layer 300 shields a portion of the upper surface of the epitaxial layer 200. The removed portion of the semiconductor layer 300 corresponding to the opening OP exposes another portion of the upper surface of the epitaxial layer 200, so that the epitaxial layer 200 has the recess 210.

The recess 210 may correspond to the opening OP of the patterned hard mask layer 400. The groove 210 may be located below the opening OP. The groove 210 may be recessed toward the substrate 100. In the epitaxial layer 200, the bottom surface of the recess 210 is closest to the substrate 100. It should be understood that the depth of the etched epitaxial layer 200, i.e., the depth of the recess 210, may be adjusted. Herein, by adjusting the depth of the recess 210, the relative depth of the first electrode, the second electrode and the third electrode, which are subsequently disposed in the recess 210, disposed in the subsequently formed SGT-MOSFET can be adjusted. Therefore, the invention can increase the number of the shielding electrodes and the depth of the shielding electrodes in addition to the depth of the drift region by arranging the shielding electrodes and adjusting the depth of the shielding electrodes, and can also enable the shielding electrodes to be simultaneously arranged in the vertical direction and the horizontal direction, thereby further improving the charge balance effect, enabling the charge to be distributed more uniformly and achieving the purpose of reducing the on-resistance.

Referring to fig. 4, the patterned hard mask layer 400 is removed. The patterned hard mask layer 400 may be removed by performing an etching process or other suitable process. The etching process may include dry etching, wet etching, or other suitable etching methods. The dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, Reactive Ion Etching (RIE). The wet etching may include, but is not limited to, removing at least a portion of the structure to be removed using an acidic solution, a basic solution, or a solvent. Furthermore, the etching process may also be a pure chemical etch, a pure physical etch, or any combination thereof.

Referring to fig. 5, a first electrode dielectric layer 500 is formed on the sidewalls and bottom surface of the recess 210 of the epitaxial layer 200 and on the semiconductor layer 300, such that the first electrode dielectric layer 500 has a trench T. The first electrode dielectric layer 500 may be silicon dioxide, silicon oxynitride, or any other suitable oxide layer material, or combinations thereof.

The first electrode dielectric layer 500 may be formed by CVD or thermal oxidation. The CVD may be Low Pressure Chemical Vapor Deposition (LPCVD), Low Temperature Chemical Vapor Deposition (LTCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), PECVD, Atomic Layer Deposition (ALD) of ALD, or other suitable CVD processes.

In some embodiments, the first electrode dielectric layer 500 is conformally formed on the epitaxial layer 200 and the semiconductor layer 300. Specifically, the first electrode dielectric layer 500 is disposed on the top surface and sidewalls of the semiconductor layer 300, and on the sidewalls and bottom surface of the recess 210 of the epitaxial layer 200. In some embodiments, the trench T has a substantially flat bottom surface, and the bottom surface of the trench T is substantially parallel to the bottom surface of the recess 210.

Referring to fig. 6 and 7, a first electrode 600 is formed in the trench T. In detail, in one embodiment, as shown in fig. 6, a conductive material is filled in the trench T of the first electrode dielectric layer 500 to form the first electrode 600. The conductive material serves as an electrode material forming the first electrode 600. The conductive material may comprise amorphous silicon, polysilicon, a metal nitride, a conductive metal oxide, or other suitable material. In some embodiments, the conductive material used to form the first electrode 600 may be polysilicon. The method for filling the conductive material comprises the following steps: CVD, sputtering, resistive heating evaporation, e-beam evaporation, or any other suitable deposition process, but is not limited thereto. In addition, after the conductive material is filled, a Chemical Mechanical Polishing (CMP) process may be further performed to make the top surface of the first electrode 600 substantially coplanar with the top surface of the first electrode dielectric layer 500.

As shown in fig. 7, the first electrode 600 is etched back such that the top surface of the first electrode 600 is lower than the top surface of the first electrode dielectric layer 500. The top surface of the first electrode 600 and the sidewall of the first electrode dielectric layer 500 form a shape similar to the trench T. Here, since the second electrode and the third electrode are further formed later, the depth of etching back the first electrode 600 may depend on the shape and the number of the second electrode and the third electrode formed later. That is, the thickness of the first electrode 600 and the thickness of the first electrode dielectric layer 500 may be adjusted according to the shape and number of the second electrode and the third electrode to be formed later. In one embodiment, if a larger number and/or a larger size or a special shape of the second electrode is required to be formed, the first electrode 600 is etched back to a deeper depth, i.e. the first electrode 600 has a smaller thickness.

Referring to fig. 8 to 10, a pair of second electrodes 700 are formed on the first electrode 600 such that the pair of second electrodes 700 are disposed corresponding to each other along the horizontal direction D2. That is, the substrate 100, the epitaxial layer 200, and the semiconductor layer 300 are disposed along the vertical direction D1, while the pair of second electrodes 700 are disposed along the horizontal direction D2, as is well known in the art. In other words, one second electrode 700 of the pair of second electrodes 700 and the other second electrode 700 of the pair of second electrodes 700 face each other. In one embodiment, one of the pair of second electrodes 700 may be disposed on one side surface of the trench T, and the other of the pair of second electrodes 700 may be disposed on the other side surface of the trench T, that is, on the opposite side surface, such that the pair of second electrodes 700 are disposed corresponding to each other along the horizontal direction D2. In detail, in one embodiment, as shown in fig. 8, a second electrode dielectric layer 510 is conformally formed on the first electrode 600. A second electrode dielectric layer 510 is disposed between the first electrode 600 and a subsequently formed second electrode. The top surface of the second electrode dielectric layer 510 and the sidewalls of the first electrode dielectric layer 500 form a trench-like shape. In one embodiment, the second electrode dielectric layer 510 is formed only on the first electrode dielectric layer 500 in the groove 210. In one embodiment, the second electrode dielectric layer 510 may be conformally formed on both the first electrode dielectric layer 500 and the first electrode 600. In some embodiments, the second electrode dielectric layer 510 and the first electrode dielectric layer 500 may be formed of the same or different materials. In some embodiments, the second electrode dielectric layer 510 may be silicon oxide, silicon oxynitride, a low-k dielectric material, or any other suitable dielectric material, or a combination thereof. In some embodiments, the second electrode dielectric layer 510 may include an oxide. In some embodiments, the second electrode dielectric layer 510 may be formed in the same or different process as the first electrode dielectric layer 500.

As shown in fig. 9, a conductive material is filled in the trench T and disposed on the second electrode dielectric layer 510 to conformably form an electrode material layer 710 on the second electrode dielectric layer 510. The electrode material layer 710 may have a trench. The conductive material serves as an electrode material forming the second electrode 700. In some embodiments, the conductive material used to form the second electrode 700 may be the same or different from the conductive material used to form the first electrode 600. In some embodiments, the second electrode 700 and the first electrode 600 may be formed in the same or different processes. In some embodiments, the conductive material used to form the second electrode 700 may be polysilicon.

As shown in fig. 10, the electrode material layer 710 is etched to expose a portion of the upper surface of the second electrode dielectric layer 510 to form the pair of second electrodes 700 having a gap therebetween. The minimum spacing of the gap between the pair of second electrodes 700 may substantially correspond to the thickness of the conformably formed electrode material layer 710. In one embodiment, the shape of the pair of second electrodes 700 depends on the way the etching is performed, such as: etching time, etching kind, etching selectivity, etching rate, but not limited thereto. For example, when performing anisotropic etching, the pair of second electrodes 700 may have a shape that is narrow at the top and wide at the bottom. That is, the spacing S1 of the gap close to the substrate is smaller than the spacing S2 of the gap far from the substrate 100. In one embodiment, the pair of second electrodes 700 may have a shape similar to a spacer.

In one embodiment, the steps of forming the second electrode 700 as described in fig. 8-10 may be repeated to form more than one pair of second electrodes 700 of a desired number to further adjust the electrical characteristics of the subsequently formed SGT-MOSFET.

Referring to fig. 11 and 12, a third electrode 800 is formed on the pair of second electrodes 700 to obtain the semiconductor structure 1 according to an embodiment of the present invention. In detail, in one embodiment, as shown in fig. 11, a third electrode dielectric layer 520 is conformally formed on the pair of second electrodes 700. The third electrode dielectric layer 520 is disposed between the pair of second electrodes 700 and the third electrode 800. In one embodiment, the third electrode dielectric layer 520 has a uniform thickness, so that a third electrode subsequently formed on the third electrode dielectric layer 520 may have a shape corresponding to the pair of second electrodes 700. In this case, the third electrode 800 may have a portion of the third electrode 800 may extend into the gap between the pair of second electrodes 700, except that the third electrode 800 may have a shape corresponding to the pair of second electrodes 700. Even more, a portion of the third electrode 800 may be in contact with the second electrode dielectric layer 510, that is, the third electrode 800 may be in contact with a portion of the upper surface of the second electrode dielectric layer 510 that is not covered by the pair of second electrodes 700 and the third electrode dielectric layer 520. In one embodiment, the third electrode dielectric layer 520 is formed only on the pair of second electrodes 700, and thus the third electrode dielectric layer 520 may expose a portion of the upper surface of the second electrode dielectric layer 510.

In one embodiment, the third electrode dielectric layer 520 may be simultaneously formed on the second electrode dielectric layer 510 and the pair of second electrodes 700. In one embodiment, the third electrode dielectric layer 520 may have a non-uniform thickness, and thus the third electrode 800 subsequently formed on the third electrode dielectric layer 520 may not have a shape corresponding to the pair of second electrodes 700. In addition, in one embodiment, the entire third electrode 800 is farther from the substrate 100 than the pair of second electrodes 700.

In some embodiments, the third electrode dielectric layer 520, the second electrode dielectric layer 510 and the first electrode dielectric layer 500 may be formed of the same or different materials. In some embodiments, the third electrode dielectric layer 520 may be silicon oxide, silicon oxynitride, a low-k dielectric material, or any other suitable dielectric material, or a combination thereof.

In some embodiments, the third electrode dielectric layer 520 may comprise an oxide. In some embodiments, the third electrode dielectric layer 520, the second electrode dielectric layer 510 and the first electrode dielectric layer 500 may be formed by the same or different processes.

Referring to fig. 12, a conductive material is filled in the trench T to form a third electrode 800. A conductive material is used as an electrode material for forming the third electrode 800. In some embodiments, the conductive material used to form the third electrode 800 may be the same or different from the conductive material used to form the second electrode 700 and the conductive material used to form the first electrode 700. In some embodiments, the third electrode 800 and the second electrode 700 and the first electrode 600 may be formed by the same or different processes. In some embodiments, the conductive material used to form the third electrode 800 may be polysilicon.

In an embodiment, after filling the trench T with the conductive material, a planarization process may be further performed to planarize the conductive material until the upper surface of the first electrode dielectric layer 500 is exposed to form the third electrode 800, so as to obtain the semiconductor structure 1 including the first electrode 600, the pair of second electrodes 700, and the third electrode 800 according to an embodiment of the present invention. The planarization process described above may include the use of, for example: a CMP process is performed.

Referring to fig. 13 to 18, the semiconductor structure of the present invention may form an SGT-MOSFET of one of the embodiments of the present invention by performing further processes.

As shown in fig. 13, a first doped region 310 is formed on the surface of the semiconductor layer 300 away from the substrate 100. The manner of forming the first doped region 310 includes: for example, but not limited to, ion implantation (ion implantation) or diffusion (diffusion) processes. In addition, the implanted dopants may also be activated by a Rapid Thermal Annealing (RTA) process.

As shown in fig. 14, an interlayer dielectric (interlayer dielectric) layer 900 is formed on the third electrode 800, the first electrode dielectric layer 500 and the semiconductor layer 300. In some embodiments, the interlayer dielectric layer 900 and the third electrode dielectric layer 520 may be formed of the same material. In some embodiments, the interlayer dielectric layer 900 and the third electrode dielectric layer 520 may be formed in the same or different processes.

As shown in fig. 15, contact vias CT are formed. The contact via CT may penetrate the first doped region 310 and the first electrode dielectric layer 500 and the interlayer dielectric layer 900. The contact via CT does not penetrate the semiconductor layer 300. The contact via CT exposes a portion of the semiconductor layer 300 disposed on the epitaxial layer 200.

As shown in fig. 16, a second doped region 320 is formed below the contact via CT and in the semiconductor layer 300. The first doped region 310 and the second doped region 320 have different conductivity types. As shown in fig. 17, via material is filled into the contact via CT to form a contact plug 330. In some embodiments, the via material may comprise a metallic material, a conductive material, or other suitable material. As shown in fig. 18, a metal layer 910 is formed on the interlayer dielectric layer 900, and the metal layer 910 and the contact plug 330 are in contact with each other, so as to obtain an SGT-MOSFET according to one embodiment of the present invention.

In some embodiments, the substrate 100, the epitaxial layer 200, and the first doped region 310 have a first conductivity type. The doping concentration of the first doping region 310 may be higher than the doping concentrations of the substrate 100 and the epitaxial layer 200. The semiconductor layer 300 and the second doped region 320 have a second conductivity type different from the first conductivity type. The doping concentration of the second doping region 320 may be higher than that of the semiconductor layer 300. Specifically, when the substrate 100 and the epitaxial layer 200 are N-type and the semiconductor layer 300 is P-type, the first doped region 310 may be a heavily doped N + type and the second doped region 320 may be a heavily doped P + type.

In particular, the SGT-MOSFETs can be classified into left and right split gate (left and right split gate) SGT-MOSFETs and up and down split gate (up and down split gate) SGT-MOSFETs. When the upper and lower separated gate type SGT-MOSFET is to be formed, the method for forming the semiconductor structure can simultaneously form a pair of shielding electrodes which correspond to each other in the horizontal direction in the same step, and simply add more shielding structures according to the requirement to increase the charge balance effect under the condition of changing only a few steps so as to further improve the electrical characteristics of the SGT-MOSFET.

In some embodiments of the present invention, a semiconductor structure may include a first electrode 600, a pair of second electrodes 700 disposed in a horizontal direction, and a third electrode 800. The first electrode 600 and the pair of second electrodes 700 may be used together as a source electrode of a shielding electrode (shielding electrode), so that the SGT-MOSFET according to one embodiment of the present invention may have a plurality of shielding electrodes. By further arranging the pair of second electrodes 700, the capacitance between the gate and the drain is changed to improve the electrical performance of the SGT-MOSFET.

In summary, according to some embodiments of the present invention, the electrical performance is further improved by disposing a plurality of source shielding structures simultaneously. For example, gate-drain capacitance, on-resistance, and switching losses can be reduced.

In addition, since the invention adjusts the process of arranging the source shielding structure, the forming method of the invention can be widely applied to the improvement of various transistors, and is a forming method capable of forming a pair of shielding electrodes which are horizontally arranged and similar to the shape of the gap object in a single step. Therefore, the purposes of simplifying the process and improving the electrical characteristics of the transistor can be achieved.

Although the embodiments of the present invention and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the process, machine, manufacture, composition of matter, means, methods and steps described in the specification as presently perceived by one of ordinary skill in the art may be utilized in accordance with the present application as a basis for designing or modifying other structures for carrying out the same functions or achieving the same results as those achieved by the present application. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the present embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising:

forming an epitaxial layer and a semiconductor layer on a substrate in sequence;

forming a patterned hard mask layer on the semiconductor layer;

using the patterned hard mask layer as an etching mask, and etching the semiconductor layer and the epitaxial layer, so that the epitaxial layer has a groove;

removing the patterned hard mask layer;

forming a first electrode dielectric layer on the sidewall and bottom surface of the groove and on the semiconductor layer, so that the first electrode dielectric layer has a trench;

forming a first electrode in the trench;

forming a pair of second electrodes on the first electrodes such that the pair of second electrodes are disposed corresponding to each other along the horizontal direction; and

A third electrode is formed on the pair of second electrodes.

2. The method of claim 1, wherein the step of forming the pair of second electrodes on the first electrode further comprises:

forming a second electrode dielectric layer on the first electrode;

forming an electrode material layer on the second electrode dielectric layer; and

The electrode material layer is etched to expose a portion of an upper surface of the second electrode dielectric layer to form the pair of second electrodes with a gap therebetween.

3. The method of claim 1, wherein the step of forming the third electrode on the pair of second electrodes further comprises:

A portion of the third electrode is extended into a gap between the pair of second electrodes.

4. The method of claim 1, wherein before the step of forming the third electrode on the pair of second electrodes:

A third electrode dielectric layer is formed on the pair of second electrodes.

5. forming method according to claim 4, is characterized in that:

The third electrode dielectric layer has a shape corresponding to the pair of second electrodes, and the third electrode dielectric layer exposes a portion of an upper surface of the second electrode dielectric layer.

6. The forming method of claim 1, further comprising:

forming a first doped region on the semiconductor layer;

forming an interlayer dielectric layer on the first electrode dielectric layer;

forming a contact via that exposes a portion of the semiconductor layer disposed on the epitaxial layer;

forming a second doped region under the contact via and in the semiconductor layer;

filling a via material in the contact via to form a contact plug; and

A metal layer is formed on the interlayer dielectric layer so that the metal layer and the contact plug are in contact with each other.

7. The forming method according to claim 6, wherein:

The substrate, the epitaxial layer, and the first doped region have a first conductivity type, and the semiconductor layer and the second doped region have a different conductivity type than the first conductivity type. the second conductivity type.

8. A semiconductor structure, characterized in that it comprises:

a substrate having a first conductivity type;

an epitaxial layer, having the first conductivity type, disposed on the substrate, and having a groove;

a semiconductor layer having a second conductivity type different from the first conductivity type, disposed on the epitaxial layer;

a first electrode dielectric layer, disposed on the sidewall and bottom surface of the groove and on the semiconductor layer, and having a groove;

a first electrode, disposed in the groove;

a pair of second electrodes disposed on the first electrodes, the pair of second electrodes corresponding to each other along the horizontal direction; and

A third electrode is disposed on the pair of second electrodes.

9. The semiconductor structure of claim 8, further comprising:

a second electrode dielectric layer disposed between the first electrode and the pair of second electrodes; and

A third electrode dielectric layer is disposed between the pair of second electrodes and the third electrode.

10. The semiconductor structure of claim 8, wherein a portion of the third electrode extends into a gap between the pair of second electrodes.

11. The semiconductor structure of claim 8, wherein a portion of the third electrode is in contact with the second electrode dielectric layer.

12. The semiconductor structure of claim 8, wherein the shape of a portion of the third electrode corresponds to the shape of the pair of second electrodes.

13. The semiconductor structure of claim 8, further comprising:

a first doped region with the first conductivity type disposed on the semiconductor layer;

an interlayer dielectric layer disposed on the first electrode dielectric layer;

a contact plug, penetrating the interlayer dielectric layer, the first electrode dielectric layer, and the first doped region, and not penetrating the semiconductor layer;

a second doped region, having the second conductivity type, disposed on the semiconductor layer and in contact with the contact plug; and

A metal layer is disposed on the interlayer dielectric layer and is in contact with the contact plug.