CN114068407B - Method for controlling the aperture size of via holes on TFT substrate - Google Patents
Method for controlling the aperture size of via holes on TFT substrate Download PDFInfo
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- CN114068407B CN114068407B CN202111306783.2A CN202111306783A CN114068407B CN 114068407 B CN114068407 B CN 114068407B CN 202111306783 A CN202111306783 A CN 202111306783A CN 114068407 B CN114068407 B CN 114068407B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
The invention relates to a method for controlling the aperture size of a via hole on a TFT substrate, wherein the via hole penetrates through an interlayer insulating layer and a grid insulating layer, and the method comprises the steps of depositing an amphoteric metal layer mask on the interlayer insulating layer; the method comprises the steps of carrying out first dry etching on an amphoteric metal layer mask to obtain a pattern of a via hole, carrying out second dry etching on a TFT substrate to form the via hole, and carrying out alkaline solution wet etching on the amphoteric metal layer mask. The method provided by the invention avoids the back phenomenon, and effectively enhances the control of the pore size, thereby controlling CD LOSS and ensuring the lap resistance and the electrical property of the product.
Description
Technical Field
The invention relates to the technical field of display screens, in particular to a method for controlling the aperture size of a via hole on a TFT substrate.
Background
At present, in the field of displays, both in the liquid crystal display technology and in the active matrix organic light emitting diode display technology, the application in the display needs a thin film transistor (Thin Film Transistor, TFT) technology as a back plate driving technology, in the liquid crystal display screen, the control of the liquid crystal display is realized through the control of the TFT on the liquid crystal molecular matrix of a specific pixel, and in the active matrix organic light emitting diode display screen, the pixel display is realized through the independent control of the TFT on the light emitting diode of the specific pixel.
Low Temperature Polysilicon (LTPS) technology is a new generation of TFT fabrication technology. In the manufacture of a TFT substrate by applying LTPS technology, the preparation of a via hole needs to etch a gate insulating layer (GI) and an interlayer Insulating Layer (ILD), the ILD includes ILD1 and ILD2, the GI is a SiO x/SiNx structure, the ILD1 is a SiN x structure, the ILD2 is a SiN x/SiOx structure, and in the etching process, parameters such as morphology and etching deviation (CD Loss) of the via hole are difficult to control due to the change of a film material, so that the etching of the via hole is one of the difficulties of LTPS technology. In the etching process, the change of the aperture size of the via hole can influence the electrical characteristics of the TFT, so that the display effect, reliability and yield of the product are directly influenced.
In the conventional TFT substrate, a Photoresist (PR) is generally used as a mask for dry etching by using CF 4、C4F8、C2HF5 or other fluorine-containing gas ionization, but due to the thickness, gradient angle and etching uniformity of the PR, the PR may generate a back phenomenon, i.e. the aperture becomes large, and the CD LOSS cannot be effectively controlled, so that the lap resistance and the electrical characteristics are affected.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a method for controlling the aperture size of a via hole on a TFT substrate, which avoids the back-off phenomenon by depositing an amphoteric metal layer mask on an ILD2, and the aperture size is only related to the size of the hole in imaging, thereby effectively enhancing the control of the aperture size, controlling CD LOSS and ensuring the lap resistance and the electrical property of the product.
A method of controlling a size of a via aperture on a TFT substrate, the via penetrating an interlayer insulating layer and a gate insulating layer, the method comprising:
S1, depositing an amphoteric metal layer mask on the interlayer insulating layer;
s2, performing first dry etching on the amphoteric metal layer mask to obtain the pattern of the via hole;
S3, performing second dry etching on the TFT substrate to form the via hole;
And S4, performing alkaline solution wet etching on the amphoteric metal layer mask.
Further, the amphoteric metal is any one of aluminum and zinc. Preferably, the amphoteric metal is aluminum.
Further, the amphoteric metal layer mask is deposited on the second interlayer insulating layer, and the thickness of the amphoteric metal layer mask is 30-80nm.
Further, the amphoteric metal layer mask is formed by adopting a physical vapor deposition method, wherein the physical vapor deposition method meets the conditions that the argon flow is 100-130sccm, the pressure is 0.3-0.4Pa, the power is 40-50KW, and the temperature is 100-120 ℃.
Further, in step S2, the etching gas used in the first dry etching includes Cl 2 and BCl 3, where the pressure is 1-4pa, the Cl 2 flow is 500-1000sccm, and the BCl 3 flow is 50-300sccm.
Further, in step S3, the etching gas used in the second dry etching includes CF 4 and O 2, where the flow rate of CF 4 is 300-600sccm, the flow rate of O 2 is 50-200sccm, and the chamber pressure is 1-2Pa.
Further, in the second dry etching process, the amphoteric metal layer mask at the via hole reacts with F -、O2 - to generate fluoride and oxide which are attached to the side wall of the via hole.
Further, the pH value of the alkaline solution is 10-12, the wet etching time is 3-5min, and the etching temperature is 50-60 ℃.
Further, the method further comprises the steps of coating photoresist on the amphoteric metal layer mask, exposing the photoresist and developing to obtain the patterns of the through holes between the step S1 and the step S2.
Further, the method further comprises the step of removing photoresist by using a stripping liquid after the first dry etching of the amphoteric metal layer mask is completed in the step S2 and the step S3, so that a film layer structure taking the amphoteric metal layer as the mask is obtained.
Compared with the prior art, the technical scheme has the advantages that the amphoteric nonmetallic layer mask is used for replacing photoresist, the aperture size is only related to the size of a hole in imaging, substances generated by the reaction of the amphoteric nonmetallic layer mask and etching gas in the etching process can protect the side wall of the via hole, the retreating phenomenon is avoided, the control of the aperture size is effectively enhanced, and therefore CD LOSS is controlled, and the lap resistance and the electrical property of a product are ensured.
Drawings
The invention is further illustrated by the accompanying drawings, which are not to be construed as limiting the invention in any way.
FIG. 1 is a flow chart of a method for controlling the size of a via hole on a TFT substrate according to the present invention;
fig. 2 is a schematic structural diagram of a TFT substrate according to an embodiment.
The reference numerals comprise a 1-glass substrate, a 2-active layer, a 3-gate insulating layer, a 31-SiO x gate insulating layer, a 32-SiN x gate insulating layer, a 4-interlayer insulating layer, a 41-first interlayer insulating layer, a 42-second interlayer insulating layer, a 421-SiO x second interlayer insulating layer, a 422-SiN x second interlayer insulating layer, a 5-aluminum layer mask and a 6-photoresist.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a method for controlling a size of a via hole on a TFT substrate includes:
S101, depositing an amphoteric metal layer mask on an interlayer insulating layer;
The amphoteric metal is aluminum and zinc, aluminum is more advantageous in terms of raw material cost, and in this embodiment, preferably, the amphoteric metal is aluminum and the amphoteric metal layer mask is an aluminum layer mask. As shown in fig. 2, the TFT substrate structure sequentially comprises, from top to bottom, a photoresist 6, an aluminum layer mask 5, a SiN x second interlayer insulating layer 422, a SiO x second interlayer insulating layer 421, a first interlayer insulating layer 41, a SiN x gate insulating layer 32, a SiO x gate insulating layer 31, and an active layer 2, wherein the aluminum layer is deposited as a mask on the SiN x second interlayer insulating layer 422, the photoresist 6 is coated on the aluminum layer mask 5, and the photoresist 6 is exposed and developed to obtain a pattern of via holes. The photoresist 6 is used to pattern vias and transfer the pattern onto the aluminum layer mask 5.
The thickness of the aluminum layer mask 5 is 30-80nm, when the thickness of the aluminum layer mask 5 is larger than 80nm, the time required for dry etching of the aluminum layer is prolonged, the photoresist 6 is caused to retreat, the effect of controlling the aperture can not be achieved, when the thickness of the aluminum layer mask 5 is smaller than 30nm, the aluminum layer is easily etched when a film layer is etched to form a via hole, the effect of controlling the aperture can not be achieved, the thickness of the aluminum layer mask 5 is in the range of 30-80nm, the etching time is short, the photoresist 6 does not retreat obviously in the etching process of the aluminum layer, and the aperture on the aluminum layer mask 5 can keep the aperture in the photoresist 6.
The principle of Physical Vapor Deposition (PVD) is that gas generates low-temperature plasma through glow discharge under the action of high voltage in a reaction chamber, and bombards target materials in an electric field by means of charged ions in an acceleration manner, so that the target materials form a film on a substrate. In the embodiment, the physical vapor deposition method is adopted to form the aluminum layer mask 5, the argon flow is 100-130sccm, the energy provided by Ar ions ionized by the argon in the flow range meets the requirement that atoms on the surface of a target material are separated from lattice constraint and fly to a substrate to deposit the aluminum layer mask 5, the pressure is 0.3-0.4Pa, when the pressure is greater than 0.4Pa, the thickness of the aluminum layer mask 5 is less than 30nm, the aluminum layer mask 5 cannot play a role in controlling the aperture, when the pressure is less than 0.3Pa, the thickness of the aluminum layer mask 5 is greater than 80nm, the aluminum layer mask 5 loses the role in controlling the aperture, the power is 40-50KW, the temperature is 100-120 ℃, in the power and temperature ranges, the uniformity of the film layer of the aluminum layer mask 5 is good, the film layer is higher than that of a SiN x, the film layer of the aluminum layer mask 5 is uniform and the structure is stable, the film layer is stable, the phenomenon of backing is avoided, the aperture is not changed in the process of etching the via hole, and the aperture is controlled.
S102, performing first dry etching on the amphoteric metal layer mask to obtain a pattern of the via hole;
Development refers to dissolving the soluble areas of the photoresist with a developer to form a pattern. After the aluminum layer mask 5 is deposited, a layer of photoresist 6 is coated on the aluminum layer mask 5, the photoresist 6 forms a pattern of a via hole after exposure and development process, the aluminum layer mask 5 exposes the aluminum layer mask at the lower layer of the photoresist 6, namely, the position where the photoresist 6 is developed, dry etching is carried out on the aluminum layer mask at the position, and the pattern of the via hole on the photoresist 6 is transferred to the aluminum layer mask 5.
In the first dry etching of the aluminum layer mask 5, the pressure is 1-4pa, the Cl 2 flow rate is 500-1000sccm, and the BCl 3 flow rate is 50-300sccm.
Cl 2 etches the aluminum layer mask 5 through reaction with aluminum, when the Cl 2 flow is larger than 1000sccm, the Cl 2 concentration is high, the etching rate is high, the transverse overetching of the through holes on the aluminum layer mask 5 is easy to occur, the aperture size deviation is large, when the Cl 2 flow is smaller than 500sccm, the Cl 2 concentration is low, the etching rate is low, the through hole patterns on the aluminum layer mask 5 cannot be completely etched, and the aperture size of the through holes is affected.
The oxidation layer on the surface of the aluminum layer can prevent chlorine from contacting with aluminum, and BCl 3 is used for reducing the oxidation layer on the surface of the aluminum layer and promoting the etching process. When the flow of BCl 3 is larger than 300sccm and the ratio of BCl 3 in etching gas is too large, the ratio of Cl 2 is small, the etching speed of the aluminum layer mask 5 is reduced, and the aperture size of the via hole is affected, and when the flow of BCl 3 is smaller than 50sccm, the oxide layer on the surface of the aluminum layer is incompletely removed, the via hole pattern on the aluminum layer mask 5 cannot be completely etched, and the aperture size of the via hole is affected.
The pressure influences the etching speed, the pressure is in the range of 1-4pa, the etching speed and the etching depth can be effectively controlled, and the etching effect is ensured.
S103, performing second dry etching on the TFT substrate to form a via hole;
And removing photoresist by using a stripping liquid after the aluminum layer mask 5 is subjected to dry etching, so as to obtain a film structure taking the aluminum layer as a mask.
As shown in fig. 2, the interlayer insulating layer 4 and the gate insulating layer 3 are etched from top to bottom in the film layer to form a via hole. In the second dry etching, the flow rate of CF 4 is 300-600sccm, the flow rate of O 2 is 50-200sccm, and the chamber pressure is 1-2Pa.
CF 4 provides an etching ion source, CF 4 flow is 300-600sccm, the quantity of carbon tetrafluoride influences the size of a through hole in a film layer, the size of the through hole comprises transverse size and longitudinal size, when CF 4 flow is more than 600sccm, the transverse etching speed of the through hole is far higher than that of the longitudinal etching speed, the transverse etching quantity is overlarge, the transverse size deviation of the through hole is large, the prepared through hole does not meet the requirements, waste of materials and devices is caused, and when CF 4 flow is less than 300sccm, the etching speed is low, and the processing time cost is increased.
The flow of O 2 influences the uniformity of the gradient of the etching section of the via hole in the film layer, when the flow of O 2 exceeds 200sccm, the etching section is rough, and the layering phenomenon of the etching section occurs, so that the uniformity of the hole wall layer of the via hole and the structure of the via hole are damaged. Meanwhile, the oxygen has the effect of improving the etching rate, so as to avoid the out-of-control etching process caused by too fast etching, thereby causing the rejection of devices due to the unsatisfactory etching of the etched via holes. Under the condition that the flow of CF 4 is 300-600sccm, the flow of oxygen is controlled to be 50-200sccm, and in the range, the oxygen can play a role in accelerating the etching rate on one hand, and can ensure the uniformity among the hole wall layers of the through hole on the other hand, so that layering phenomenon can not occur.
The pressure influences the concentration of CF 4 and O 2, and further influences the etching speed and the etching depth, and the pressure is 1-2Pa, so that the etching speed and the etching depth can be effectively controlled within the range, and the etching effect is ensured.
In the second dry etching, the aluminum layer mask 5 at the via hole reacts with F -、O2 - to generate AlF 3、Al2O3, the product is attached to the side wall of the via hole, the side wall is protected, excessive etching of the lateral dimension of the via hole is avoided, namely the mask layer is prevented from retreating, and the aperture size is ensured.
And S104, performing alkaline solution wet etching on the amphoteric metal layer mask.
The wet etching has high etching selectivity, is beneficial to controlling over etching and residue, does not damage other film layers, and has high reliability, simple operation and low cost. After the film layer is etched to form a via hole, the aluminum layer mask 5 is removed by wet etching. The film layer contains a metal Mo layer, mo can be dissolved in an acidic solution, and the condition that the performance of a device is influenced because the Mo layer is dissolved can be avoided by using an alkaline solvent, and in order to avoid etching other metals in the film layer, the inventor selects an amphoteric metal layer as a mask, and the amphoteric metal can react with the acidic solution and also react with the alkaline solvent, namely, the amphoteric metal can be etched by the acidic solvent or the alkaline solvent. In this embodiment, the alkaline solvent etches only the aluminum layer mask 5.
The alkaline solution reacts with the aluminum layer mask 5 to perform etching, the etching reaction is a reversible reaction, as the concentration of Al 3+ in the alkaline solution increases with the progress of the etching process, the increase of the concentration of Al 3+ promotes the progress of the reverse reaction, and suppresses the progress of the main reaction, i.e., the etching reaction, to thereby cause the reduction of the etching rate, so that the alkaline solution in which Al 3+ is dissolved needs to be replaced during the etching process to ensure the etching rate and the etching effect. The inventor finds that the aluminum layer mask 5 can be completely etched under the conditions that the PH value of the alkaline solution is 10-12, the etching time is 3-5min and the etching temperature is 50-60 ℃ and the etching effect is optimal.
The invention has the advantages that 1, the precise etching of the amphoteric metal layer mask is realized through the design of the thickness of the amphoteric metal layer mask and the regulation and control of etching gas flow, pressure and power, the etching time of the amphoteric metal layer mask is short, the retreating phenomenon is avoided, 2, the aperture on the amphoteric metal layer mask can keep the aperture size in the photoresist, namely, the aperture size is only related to the aperture imaging time, and 3, in the subsequent dry etching of the through hole, the amphoteric metal in the amphoteric metal layer mask reacts with the etching gas to generate a side wall protection layer, and the retreating is also avoided. The method for controlling the size of the etching aperture of the through hole effectively enhances the control of the size of the aperture, thereby controlling CD LOSS and ensuring the lap resistance and the electrical property of the product.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (8)
1. A method of controlling the size of a via hole in a TFT substrate, the via hole penetrating through an interlayer insulating layer and a gate insulating layer, the method comprising:
S1, depositing an amphoteric metal layer mask on the interlayer insulating layer;
s2, performing first dry etching on the amphoteric metal layer mask to obtain the pattern of the via hole;
S3, performing second dry etching on the TFT substrate to form the via hole;
S4, performing alkaline solution wet etching on the amphoteric metal layer mask;
In the step S3, the etching gas used in the second dry etching comprises CF4 and O2, wherein the CF4 flow is 300-600sccm, the O2 flow is 50-200sccm, and the chamber pressure is 1-2Pa;
And in the second dry etching process, the amphoteric metal layer mask at the via hole reacts with F-, O2-, so as to generate fluoride and oxide which are attached to the side wall of the via hole.
2. The method for controlling a via hole size on a TFT substrate according to claim 1, the amphoteric metal is any one of aluminum and zinc.
3. The method of controlling the pore size of a via hole on a TFT substrate as set forth in claim 2, wherein the amphoteric metal layer mask is deposited on the second interlayer insulating layer, and the amphoteric metal layer mask has a thickness of 30-80nm.
4. The method of claim 2, wherein the amphoteric metal layer mask is formed by physical vapor deposition, wherein the physical vapor deposition is performed at a temperature of 100-120 ℃ with an argon flow of 100-130sccm, a pressure of 0.3-0.4Pa, a power of 40-50KW, and a temperature of 100-120 ℃.
5. The method according to claim 1, wherein in the step S2, the etching gas used in the first dry etching includes Cl2 and BCl3, wherein the pressure is 1-4pa, the Cl2 flow is 500-1000sccm, and the BCl3 flow is 50-300sccm.
6. The method of claim 1, wherein the alkaline solution has a PH of 10-12, and the wet etching time is 3-5min and the temperature is 50-60 ℃.
7. The method of claim 1, further comprising coating a photoresist on the amphoteric metal layer mask, exposing the photoresist, and developing to obtain a pattern of the via hole.
8. The method of claim 7, further comprising removing photoresist using a stripping solution after the masking of the amphoteric metal layer completes the first dry etching to obtain a film structure with the amphoteric metal layer as a mask between step S2 and step S3.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560657A (en) * | 2004-03-05 | 2005-01-05 | 武汉光迅科技有限责任公司 | Method for reaction ion deep etching to silica using compound mask |
| CN110310921A (en) * | 2019-07-09 | 2019-10-08 | 京东方科技集团股份有限公司 | A display substrate and its manufacturing method, a display panel and a display device |
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| JP2009238998A (en) * | 2008-03-27 | 2009-10-15 | Epson Imaging Devices Corp | Method of forming contact hole, pattern forming method, and method of manufacturing electrooptical device |
| US8187929B2 (en) * | 2009-11-04 | 2012-05-29 | Cbrite, Inc. | Mask level reduction for MOSFET |
| US8647980B2 (en) * | 2010-02-25 | 2014-02-11 | Sharp Kabushiki Kaisha | Method of forming wiring and method of manufacturing semiconductor substrates |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560657A (en) * | 2004-03-05 | 2005-01-05 | 武汉光迅科技有限责任公司 | Method for reaction ion deep etching to silica using compound mask |
| CN110310921A (en) * | 2019-07-09 | 2019-10-08 | 京东方科技集团股份有限公司 | A display substrate and its manufacturing method, a display panel and a display device |
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