CN114065675B - Simulation system and method thereof - Google Patents
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Abstract
一种仿真系统及其方法，通过连接系统电源传输模型、模拟电流时域模型与数字电流时域模型，并取得获取供电电流后所产生的电源噪音；基于相位锁定回路所输出的时钟信号的传输，通过仿真程序取得每一接口连结电路模型在电源噪音下的抖动时域信息；通过仿真程序仿真出每一接口连结电路模型于时钟端接收理想信号时电压量测点的电压阶跃响应，进而生成对应的第一电压时域模型；以及基于每一接口连结电路模型在电源噪音下的抖动时域信息、其对应的第一电压时域模型与数据的传输，生成对应的系统波形，进而取得对应的眼图与时域抖动分布。
A simulation system and method thereof are provided, which connect a system power transmission model, an analog current time domain model and a digital current time domain model, and obtain the power supply noise generated after obtaining the power supply current; based on the transmission of the clock signal output by the phase-locked loop, obtain the jitter time domain information of each interface connection circuit model under the power supply noise through a simulation program; simulate the voltage step response of the voltage measurement point of each interface connection circuit model when the clock end receives an ideal signal through the simulation program, and then generate the corresponding first voltage time domain model; and based on the jitter time domain information of each interface connection circuit model under the power supply noise, its corresponding first voltage time domain model and the transmission of data, generate the corresponding system waveform, and then obtain the corresponding eye diagram and time domain jitter distribution.
Description
Technical Field
The present invention relates to a simulation system and a method thereof, and more particularly to a simulation system and a method thereof integrating signal and power integrity.
Background
In recent years, advanced applications such as internet of things, handheld systems, automotive electronics, high-speed operation and AI chips are emerging, more and more functional blocks are integrated into a System on a Chip (SoC), and the operating speed of an Application Specific Integrated Circuit (ASIC) and the data transmission rate of each input/output block in the System on a Chip become higher and higher, so that signal integrity and power integrity become more and more mutually affected.
Power integrity covers ASIC core power and power per input-output block and is largely dependent on the mode in the SoC. Typically, an ASIC core power supply will be used to provide power for each input-output block, and the activity of the ASIC will affect the signal quality in each input-output block through the core power supply.
As the data transfer rate of each i/o block becomes higher and the system bandwidth is limited, jitter in the package and printed circuit board is amplified, and thus, system performance also needs to take into account this effect. In addition, crosstalk effects from the package and the printed circuit board are also related to modes in the SoC.
However, in the conventional method, quantitative analysis is performed for the independent performance requirements of the input/output interface (i.e. the input/output blocks), the package and the printed circuit board, and finally, the integrated design of the full-chip system is performed, which has the problems of consuming a lot of unnecessary manpower and material resources and causing waste of area/power consumption. There is therefore a need for improved techniques to solve this problem.
Disclosure of Invention
The invention discloses a simulation system and a simulation method.
First, the invention discloses a simulation system, which comprises a memory module and a processor. The System comprises a memory module, a processor and a control module, wherein the memory module is used for storing a plurality of instructions, and the processor is used for executing the instructions stored by the memory module to perform simulation analysis programs on a full-Chip System, and the full-Chip System comprises a packaging structure, a printed circuit board and a System on a Chip (SoC). The simulation analysis program comprises a modeling module, a system power transmission model and an interface connection circuit model, wherein the modeling module is used for generating a signal channel model corresponding to each input and output power domain based on the design layout of a packaging structure and a printed circuit board, generating the system power transmission model based on the design layout of the packaging structure and the printed circuit board and the distribution of a plurality of power supply nodes on the layout of a single chip of the system, and establishing the interface connection circuit model for each input and output power domain, wherein each interface connection circuit model comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measuring point and a voltage measuring point, two sides of the signal channel model are respectively connected with the transmitter and the receiver in each interface connection circuit model, and the transmitter is provided with a data input end, The clock end and the input and output power end, the current measuring point is arranged on the input and output power end, the voltage measuring point is arranged at the joint of the signal channel model and the receiver, the corresponding second current time domain model is generated based on the response of the current measuring point when the first current time domain model corresponding to each interface connection circuit model receives random data at the data input end, and the third current time domain model is generated based on the current change of each power supply node in the digital circuit corresponding to the digital power domain. the simulation module is connected with the modeling module and is used for simulating the current step response of the current measuring point in each interface connection circuit model through a Simulation Program (SPICE) focusing on the integrated circuit so as to generate a corresponding first current time domain model, and simulating the voltage step response of the voltage measuring point when each interface connection circuit model receives an ideal signal at a clock end through the simulation program focusing on the integrated circuit so as to generate a corresponding first voltage time domain model. The power supply noise module is connected with the modeling module and the simulation module and is used for connecting the system power supply transmission model, each second current time domain model and each third current time domain model to generate a complete power supply transmission model, and obtaining power supply noise generated after the complete power supply transmission model obtains power supply current. the storage module is used for recording a clock output by the phase locking loop, and the phase locking loop is connected with each interface connection circuit model. The jitter module is connected with the storage module and the power supply noise module and is used for simulating the sensitivity of each interface connection circuit model to the power supply through a simulation program focusing on the integrated circuit based on the transmission of the clock signal output by the phase locking loop, so as to obtain the jitter time domain information of each interface connection circuit model under the power supply noise. The analysis module is connected with the modeling module, the dithering module and the simulation module and is used for generating a system waveform corresponding to each interface connection circuit model based on dithering time domain information of each interface connection circuit model under power noise, a first voltage time domain model corresponding to each interface connection circuit model and data transmission in each interface connection circuit model, and further obtaining an eye diagram corresponding to each interface connection circuit model and time domain dithering distribution.
In addition, the invention discloses a simulation method for performing simulation analysis on a full-chip system, wherein the full-chip system comprises a packaging structure, a printed circuit board and a system single chip, the simulation method comprises the following steps of (a) generating a signal channel model corresponding to each input and output power supply domain based on the design layout of the packaging structure and the printed circuit board and the distribution of a plurality of power supply nodes on the layout of the system single chip, (b) generating a system power supply transmission model based on the design layout of the packaging structure and the printed circuit board, (c) establishing an interface connection circuit model for each input and output power supply domain, wherein each interface connection circuit model comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measuring point and a voltage measuring point, in each interface connection circuit model, two sides of the signal channel model are respectively connected with the transmitter and the receiver, the transmitter is provided with a data input end, the clock end and the input and the output power end, the current quantity is arranged on the input and output power end, d) generating a current step response current corresponding to a first digital power supply model corresponding to the current step response to the first digital power supply model in the time domain by simulating a Simulation Program (SPC) of the integrated circuit, based on a Simulation Program (SPS) on the integrated circuit, and generating a current step response current corresponding to the first digital power supply model based on the current step-time domain, and the digital power supply model, the method comprises the steps of (1) generating a third current time domain model, (g) connecting a system power transmission model, each second current time domain model and each third current time domain model to generate a complete power transmission model, obtaining power supply noise generated after the complete power transmission model obtains power supply current, (h) recording clock signals output by a phase locking loop, wherein the phase locking loop is connected with each interface connection circuit model, (i) simulating sensitivity of each interface connection circuit model to a power supply through a simulation program focused on an integrated circuit based on transmission of the clock signals output by the phase locking loop, further obtaining jitter time domain information of each interface connection circuit model under the power supply noise, (j) simulating voltage step response of voltage measurement points when each interface connection circuit model receives ideal signals at a clock end through the simulation program focused on the integrated circuit, further generating a corresponding first voltage time domain model, and (k) generating a corresponding system of each interface connection circuit by transmitting data in each interface connection circuit model based on jitter time domain information of each interface connection circuit model under the power supply noise, and further obtaining a corresponding waveform distribution of each interface connection circuit model.
The system and the method disclosed by the invention are different from the prior art in that the system and the method are characterized in that a system power transmission model, an analog current time domain model and a digital current time domain model are connected, power supply noise generated after power supply current is acquired, jitter time domain information of each interface connection circuit model under the power supply noise is acquired through a simulation program focusing on an integrated circuit based on the transmission of clock signals output by a phase locking loop, voltage step response of a voltage measurement point when each interface connection circuit model receives an ideal signal at a clock end is simulated through the simulation program focusing on the integrated circuit, a corresponding first voltage time domain model is generated, and system waveforms corresponding to each interface connection circuit model are generated based on the jitter time domain information of each interface connection circuit model under the power supply noise, the first voltage time domain model corresponding to each interface connection circuit model and the transmission of data in each interface connection circuit model, so that eye patterns and time domain jitter distribution corresponding to each interface connection circuit model are acquired.
Through the technical means, the full-chip system can be abstractly modeled to carry out simulation analysis on signal integrity and power supply integrity.
Drawings
FIG. 1A is a schematic diagram illustrating components of a simulation system according to an embodiment of the present invention.
FIG. 1B is a system architecture diagram of an embodiment of a simulation system of the present invention.
FIGS. 2A and 2B are flowcharts illustrating an exemplary method for executing a simulation analysis procedure by the simulation system of FIG. 1B.
FIG. 3 is a schematic diagram of an embodiment of an interface connection circuit model according to the present invention.
Wherein reference numerals are used to refer to
50. Current measuring point
60. Voltage measuring point
72. Data input terminal
74. Clock terminal
76. Input/output power supply terminal
100. Simulation system
101. Processor and method for controlling the same
102. Memory module
103. Bus line
110. Modeling module
120. Simulation module
130. Power supply noise module
140. Storage module
150. Dithering module
160. Analysis module
170. Optimization module
180. Setting module
410. Transmitter
420. Signal channel model
430. Receiver with a receiver body
Step 210 generates a signal channel model corresponding to each input/output power domain based on the design layout of the package structure and the printed circuit board
Step 220 generates a system power transmission model based on the design layout of the package structure and the printed circuit board and the distribution of the power supply nodes on the layout of the system single chip
Step 230 establishes an interface connection circuit model for each input/output power domain, wherein each interface connection circuit model comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measurement point and a voltage measurement point, in each interface connection circuit model, two sides of the signal channel model are respectively connected with the transmitter and the receiver, the transmitter is provided with a data input end, a clock end and an input/output power end, the current measurement point is arranged on the input/output power end, and the voltage measurement point is arranged at the joint of the signal channel model and the receiver
Step 240 simulates a current step response of a current measurement point in each interface link circuit model by a simulation program focused on the integrated circuit to generate a corresponding first current time domain model
Step 250 generates a corresponding second current time domain model based on the response of the current measurement point when the first current time domain model corresponding to each interface link circuit model receives random data at the data input terminal
Step 260 generates a third current time domain model based on the current variation of each power supply node in the digital circuit corresponding to the digital power domain
Step 270 connects the system power transmission model, each second current time domain model and each third current time domain model to generate a complete power transmission model, and obtains the power noise generated by the complete power transmission model after obtaining the power supply current
Step 280 records the clock signal outputted from the phase-locked loop, which connects each interface link circuit model
Step 290 simulates the sensitivity of the interface connection circuit model to the power supply by the simulation program focusing on the integrated circuit based on the transmission of the clock signal outputted by the phase-locked loop, thereby obtaining the jitter time domain information of the interface connection circuit model under the power supply noise
Step 300 simulates a voltage step response of a voltage measurement point when each interface link circuit model receives an ideal signal at a clock end by a simulation program focusing on an integrated circuit, thereby generating a corresponding first voltage time domain model
Step 310 generates a system waveform corresponding to each interface link circuit model based on the jitter time domain information of each interface link circuit model under the power noise, the first voltage time domain model corresponding to each interface link circuit model and the data transmission in each interface link circuit model, and further obtains an eye pattern and a time domain jitter distribution corresponding to each interface link circuit model
Detailed Description
The following detailed description of embodiments of the present invention will be given with reference to the drawings and examples, by which the implementation process of how the technical means are applied to solve the technical problems and achieve the technical effects can be fully understood and implemented.
Referring to fig. 1A and fig. 1B, fig. 1A is a schematic diagram illustrating elements of an embodiment of a simulation system according to the present invention, and fig. 1B is a system architecture diagram of an embodiment of a simulation system according to the present invention. In this embodiment, the simulation system 100 may include, but is not limited to, one or more processors 101, one or more memory modules 102, a bus 103, and other hardware elements, where the bus 103 may connect different hardware elements. With the plurality of hardware elements included, the simulation system 100 may be applied to a computing device to execute corresponding software or program applications.
The bus 103 may include one or more types of buses including, for example, a data bus (data bus), an address bus (address bus), a control bus (control bus), an extended function bus (expansion bus), and/or a local bus (local bus), among others. The buses of the computing device include, but are not limited to, a parallel Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, a Video Electronics Standards Association (VESA) local bus, a serial Universal Serial Bus (USB), a peripheral component interconnect express (PCI-E) bus, and the like.
In this embodiment, processor 101 may be coupled to bus 103. The processor 101 may include a Register set or space that may be disposed entirely on the processing chip or may be disposed entirely or partially off the processing chip and coupled to the processor 101 via dedicated electrical connections and/or via the bus 103. Wherein the processor 101 may be a processing unit, a microprocessor, or any suitable processing element. When the simulation system 100 includes multiple processors, the processors may be the same or similar processors and are coupled and in communication via the bus 103. The processor 101 may interpret a series of instructions to perform a particular operation or action, such as a mathematical operation, a logical operation, a data comparison, copying/moving data, etc., to thereby execute various program applications, modules and/or elements.
In addition, the processor 101 may be coupled to the chipset or electrically connected to the chipset via a bus 103. The chipset is composed of one or more Integrated Circuits (ICs) including a memory controller and a peripheral input/output (I/O) controller, that is, the memory controller and the peripheral input/output controller may be included in one integrated circuit or may be implemented using two or more integrated circuits. A chipset typically provides input, output, and memory management functions as well as a plurality of general purpose and/or special purpose registers, timers, etc. that are accessible or used by one or more processors 101 coupled or electrically connected to the chipset.
In addition, the processor 101 may also access data in the memory module 102 and mass storage area installed on the simulation system 100 through the memory controller. The memory module 102 includes any type of volatile memory (NVRAM) and/or non-volatile memory, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), flash memory (Flash), read Only Memory (ROM), etc. The mass storage area may include any type of storage device or storage medium, such as a hard disk drive, an optical disk, a flash memory, a memory card (memory card), a Solid state disk (Solid STATE DISK, SSD), or any other storage device. That is, the memory controller may access data in static random access memory, dynamic random access memory, flash memory, hard disk drive, solid state disk.
The processor 101 may be connected to and communicate with peripheral devices or interfaces such as a GPS receiver via the bus 103 via a peripheral i/o controller. The peripheral input device may be any type of input device, such as a keyboard, a mouse, a trackball, a touch pad, a joystick, etc., and the peripheral output device may be any type of output device, such as a display, a printer, etc., and the peripheral input device and the peripheral output device may be the same device, such as a touch screen, etc. The communication interface may include a wireless communication interface and/or a wired communication interface, where the wireless communication interface may include an interface supporting a wireless area network such as Wi-Fi, zigbee, bluetooth, infrared, near Field Communication (NFC), a mobile communication network such as 3G/4G/5G, or other wireless data transmission protocols, and the wired communication interface may be an ethernet device, an Asynchronous Transfer Mode (ATM) device, a DSL modem, a Cable modem, or the like. The processor 101 may periodically poll (poll) various peripheral devices and interfaces so that the simulation system 100 can perform data input and output through the various peripheral devices and interfaces.
As shown in FIG. 1B, the simulation system 100 includes a modeling module 110, a simulation module 120, a power noise module 130, a storage module 140, a dithering module 150, and an analysis module 160, and an attachable optimization module 170, and a setup module 180. The modeling module 110, the simulation module 120, the power noise module 130, the storage module 140, the dithering module 150, the analysis module 160, the optimization module 170, and the setting module 180 are generally generated after the processor 101 executes a specific program loaded into the memory module 102 or are included in the processor 101. In practical implementations, the simulation system 100 may be applied to, but not limited to, a tablet, a desktop, or a notebook.
Next, referring to fig. 2A and 2B, fig. 2A and 2B are flowcharts of a method for executing a simulation analysis procedure in the simulation system of fig. 1B, wherein the simulation analysis procedure can be used for performing a simulation analysis on a full-chip system, the full-chip system comprises a package structure, a printed circuit board and a system single chip, and the simulation analysis procedure comprises the steps of generating a signal channel model corresponding to each input/output power domain based on a design layout of the package structure and the printed circuit board (step 210); generating a system power supply transmission model based on the design layout of a packaging structure and a printed circuit board and the distribution of a plurality of power supply nodes on the layout of a system single chip (step 220), establishing an interface connection circuit model for each input/output power supply domain, wherein each interface connection circuit model comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measuring point and a voltage measuring point, in each interface connection circuit model, the transmitter and the receiver are respectively connected to two sides of the signal channel model, the transmitter is provided with a data input end, a clock end and an input/output power supply end, the measuring point is arranged on the input/output power supply end, the current measuring point is arranged at the connection position of the signal channel model and the receiver (step 230), simulating the current step response of the current measuring point in each interface connection circuit model through a Simulation Program (SPICE) focusing on an integrated circuit, further generating a corresponding first current time domain model (step 240), receiving the response of the current measuring point when random data is received at the data input end based on the first current time domain corresponding to each interface connection circuit model, the method comprises the steps of generating a corresponding second current time domain model (step 250), generating a third current time domain model based on current change of each power supply node in a digital circuit corresponding to a digital power domain (step 260), connecting a system power transmission model, each second current time domain model and each third current time domain model to generate a complete power transmission model, acquiring power supply noise generated after the complete power transmission model acquires power supply current (step 270), recording clock signals output by a phase locking loop, connecting each interface connection circuit model by the phase locking loop (step 280), simulating sensitivity of each interface connection circuit model to a power supply through a simulation program focused on an integrated circuit based on transmission of the clock signals output by the phase locking loop, further acquiring jitter time domain information of each interface connection circuit model under the power supply noise (step 290), simulating voltage step response of a voltage measurement point when each interface connection circuit model receives ideal signals at a clock end through the simulation program focused on the integrated circuit, further generating a corresponding first voltage time domain model, generating a corresponding to each interface connection time domain distribution model based on jitter time domain information of each interface connection circuit model under the power supply noise, and corresponding to each interface connection time domain model in each interface connection circuit model (step 310).
In step 210, the modeling module 110 may describe the package structure and the printed circuit board by using a scattering parameter (SCATTERING PARAMETERS, S parameter) or one to multiple stages of RLCG (resistor-inductor-capacitor-conductance) circuits, so that the package structure and the printed circuit board are abstract-modeled, in more detail, the modeling module 110 may establish an electrical performance model (i.e. a first power transmission model and a first signal transmission model) corresponding to the package structure based on a design layout of the package structure, the model formats of the first power transmission model and the first signal transmission model may be S parameter or RLCG circuit, the modeling module 110 may establish an electrical performance model (i.e. a second power transmission model and a second signal transmission model) corresponding to the printed circuit board based on a design layout of the printed circuit board, the model formats of the second power transmission model and the second signal transmission model may be S parameter or RLCG circuit, and then, based on a connection relation between the package structure and the printed circuit board, the modeling module 110 may connect the first signal transmission model and the second signal transmission model, and divide according to different input/output power domains in the input/output interfaces, and generate a signal domain corresponding to each input power domain, and an output channel corresponding to the signal domain, and an input channel corresponding to the model.
In step 220, the modeling module 110 may describe the layout of the system-on-chip by using one or more stages of RLCG circuits, so that the system-on-chip is abstractly modeled, and thus, the modeling module 110 may establish a third power transmission model corresponding to the system-on-chip by using the RLCG circuits based on the distribution of the power supply nodes (i.e. the parasitic resistances, the parasitic capacitances and the parasitic inductances of the metal wires in the system-on-chip) on the layout of the system-on-chip, and then connect the first power transmission model, the second power transmission model and the third power transmission model based on the power connection relationship (i.e. the actual channel of the power supply) between the package structure, the printed circuit board and the system-on-chip, so as to generate a system-on-chip power transmission model, where the model format of the system-on-chip may be S parameters, but the embodiment is not limited to this disclosure, and the model format of the system-on-chip may be impedance parameters (Z parameters).
In step 230, the modeling module 110 may establish a corresponding interface connection circuit model for each input/output power domain of a system single chip (as shown in fig. 3, fig. 3 is a schematic diagram of an embodiment of the interface connection circuit model of the present invention), wherein each interface connection circuit model includes a transmitter 410, a corresponding signal channel model 420, a receiver 430, a current measurement point 50 and a voltage measurement point 60, in each interface connection circuit model, two sides of the signal channel model 420 are respectively connected to the transmitter 410 and the receiver 420, the transmitter 410 has a data input end 72, a clock end 74 and an input/output power end 76, the current measurement point 50 is disposed on the input/output power end 76, the voltage measurement point 60 is disposed at a connection between the signal channel model 420 and the receiver 430, the data input end 72 is used for receiving data to be transmitted through the transmitter 410, the clock end 74 is used for receiving clock signals, and the input/output power end 76 is used for receiving power from the input/output power domains.
In step 240, the simulation module 120 may simulate the current step response of the current measurement point 50 in each interface link circuit model established by the modeling module 110 by a Simulation Program (SPICE) focusing on the integrated circuit, thereby generating a corresponding first current time domain model. In more detail, after the modeling module 110 establishes each of the interface link circuit models, the simulation module 120 can simulate the current change of the current measurement point 50 when the data received by the data input terminal 72 is changed from 0 to 1 (i.e. the data rising edge), and the current change of the current measurement point 50 when the data received by the data input terminal 72 is changed from 1 to 0 (i.e. the data falling edge), so that the simulation module 120 can simulate the current step response of each of the current measurement points 50, and generate the first current time domain model corresponding to each of the interface link circuit models based on the current step response of each of the current measurement points 50.
In step 250, the modeling module 110 may generate a corresponding second current time domain model based on the response of the current measurement point 50 of each interface link circuit model when the data input 72 receives random data. In more detail, when the simulation module 120 generates a first current time domain model corresponding to each interface link circuit model and the data input 72 receives random data (e.g., 010010010001.+ -.), the modeling module 110 can compare a current data bit with a previous data bit in the random data to obtain an interface data variation corresponding to each first current time domain model, and generate a second current time domain model corresponding to each first current time domain model based on the first current time domain model corresponding to each interface link circuit model, the current step response of the current measurement point 50 of each first current time domain model generated in step 240 (i.e., the simulation data in step 240), and the interface data variation corresponding to each first current time domain model. When the current data bit in the random data is the same as the previous data bit (i.e. has no change), the current at the current measurement point 50 of the first current time domain model is zero.
In step 260, the modeling module 110 may generate a third current time domain model based on the current variation of each power supply node in the digital circuit corresponding to the digital power domain. In more detail, the modeling module 110 can find the data change of each power supply node in the digital circuit by using the VCD file, find the current step response of each power supply node in any standard cell (i.e. the current change when the data of each power supply node is changed from 0 to 1 or from 1 to 0) by using the standard cell library to generate the current time domain model of each power supply node in the standard cell under the data change, and obtain the current change of each power supply node by using the linear superposition mode based on the plurality of standard cells to which each power supply node belongs, so as to generate the third current time domain model.
In step 270, the power noise module 130 may connect the system power transmission model, each of the second current time domain models and each of the third current time domain models to generate a complete power transmission model, and obtain the power noise generated by the complete power transmission model after obtaining the power supply current. In other words, after the complete power transmission model is generated, the power noise module 130 can enable the complete power transmission model to obtain the power supply current, and further obtain the power noise correspondingly generated.
In step 280, the storage module 140 can record the clock signal outputted from the phase locked loop of the system on chip, wherein the phase locked loop is connected to each interface link circuit model. In other words, the storage module 140 can record the time domain information corresponding to the clock edge of the clock signal outputted by the phase-locked loop, that is, record the clock edge of the actual waveform outputted by the phase-locked loop, wherein the clock edge is the rising edge and the falling edge of the clock signal.
In step 290, the dithering module 150 may simulate the sensitivity of each interface link circuit model to the power supply by SPICE based on the transmission of the clock signal output by the phase-locked loop (i.e., the clock signal transmitted from the phase-locked loop to the transmitter 410), thereby obtaining the dithering time domain information of each interface link circuit model under the power supply noise. The dithering module 150 may further superimpose all the dithering time domain information with the time domain information corresponding to the clock edge of the clock signal output by the phase locked loop in step 280, so as to generate actual dithering time domain information of the whole system.
In step 300, the simulation module 120 may simulate the voltage step response of the voltage measurement point 60 of each interface link circuit model when the clock end 74 receives the ideal signal (i.e. the ideal clock signal) through SPICE, thereby generating a corresponding first voltage time domain model. In more detail, the simulation module 120 can simulate the voltage change of the voltage measuring point 60 when the clock terminal 74 of each interface link circuit model receives the ideal clock signal and the data received by the data input terminal 72 thereof is changed from 0 to 1, and the voltage change of the voltage measuring point 60 when the clock terminal 74 of each interface link circuit model receives the ideal clock signal and the data received by the data input terminal 72 thereof is changed from 1 to 0, by SPICE, so the simulation module 120 can simulate the voltage step response of the voltage measuring point 60 when the clock terminal 74 of each interface link circuit model receives the ideal signal (i.e. is the ideal clock signal), and generate the corresponding first voltage time domain model based on the voltage step response of each voltage measuring point 60.
In step 310, the analysis module 160 may generate a system waveform corresponding to each interface link circuit model based on the jitter time domain information of each interface link circuit model under the power noise in step 290, the first voltage time domain model corresponding to each interface link circuit model generated in step 300, and the data transmission in each interface link circuit model, so as to obtain an eye diagram and a time domain jitter distribution corresponding to each interface link circuit model.
Through the steps, the full-chip system can be abstractly modeled so as to carry out simulation analysis on the signal integrity and the power integrity. In other words, the quantitative analysis can be performed according to the performance requirements of the full-chip system (i.e., the quantitative analysis is performed for the overall system performance requirements of the input/output interface, the package and the printed circuit board), so that the waste of area/power consumption during final integration due to the independent performance requirements of the input/output interface, the package and the printed circuit board is avoided.
In addition, in the present embodiment, a setting procedure may be performed before executing the simulation analysis procedure (i.e. steps 210 to 310), where the setting procedure may include receiving and setting a preset eye pattern standard corresponding to each input/output circuit and a capacitance value of a blocking capacitor (de-coupling capacity) between the input/output circuit and the digital circuit corresponding to each input/output power domain in a single chip of the system. The setting module 180 may be connected to the modeling module 110 and execute the setting procedure described above. The isolation capacitor of the system single chip is used for reducing the influence of power supply jitter.
In addition, in the embodiment, after the simulation analysis procedure (i.e., steps 210 to 310) is performed, an optimization procedure may be performed, where the optimization procedure includes determining whether the eye pattern corresponding to each input/output circuit meets the corresponding preset eye pattern standard, and when it is determined that the eye pattern corresponding to one input/output circuit does not meet the corresponding preset eye pattern standard, adjusting the capacitance value of the blocking capacitor between the input/output circuit and the digital circuit, and re-performing the simulation analysis procedure until it is determined that the eye pattern corresponding to the input/output circuit meets the corresponding preset eye pattern standard. The optimizing module 170 may connect the analyzing module 160 with the setting module 180 and execute the optimizing procedure described above. Wherein each preset eye pattern criteria includes an eye width (eye width) criteria and/or an eye height (EYE HEIGHT) criteria.
Through the optimization program, the influence of power supply jitter can be reduced by adjusting the capacitance value of each partition capacitor of a single chip of the system, the number of partition capacitors used by the traditional simulation method can be reduced, and the area waste caused by setting excessive partition capacitors is avoided.
In summary, the difference between the present invention and the prior art is that the power supply noise generated after the power supply current is obtained by connecting the system power supply transmission model, the analog current time domain model and the digital current time domain model, the jitter time domain information of each interface connection circuit model under the power supply noise is obtained by focusing on the simulation program of the integrated circuit based on the transmission of the clock signal output by the phase locking loop, the voltage step response of the voltage measurement point when each interface connection circuit model receives the ideal signal at the clock end is simulated by focusing on the simulation program of the integrated circuit, so as to generate the corresponding first voltage time domain model, and the system waveform corresponding to each interface connection circuit model is generated based on the jitter time domain information of each interface connection circuit model under the power supply noise, the transmission of the data in each interface connection circuit model, so as to obtain the eye pattern and the time domain jitter distribution corresponding to each interface connection circuit model. In other words, the quantitative analysis can be performed according to the performance requirements of the full-chip system (i.e., the quantitative analysis is performed for the overall system performance requirements of the input/output interface, the package and the printed circuit board), so that the waste of area/power consumption during final integration due to the independent performance requirements of the input/output interface, the package and the printed circuit board is avoided.
In addition, the optimization program of the invention can reduce the influence of power supply jitter by adjusting the capacitance value of the isolating capacitor of the single chip of the system, and can reduce the use quantity of the isolating capacitor, thereby avoiding the area waste caused by the arrangement of excessive isolating capacitors.
Although the foregoing embodiments of the present invention have been described in detail, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
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| CN109684755A (en) * | 2018-12-28 | 2019-04-26 | 佛山中科芯蔚科技有限公司 | A kind of digital-analog mix-mode chip asynchronous circuit full custom method and system |
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| CN109684755A (en) * | 2018-12-28 | 2019-04-26 | 佛山中科芯蔚科技有限公司 | A kind of digital-analog mix-mode chip asynchronous circuit full custom method and system |
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