CN114064531B - A system for fast access to remote storage devices based on FPGA - Google Patents
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- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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Abstract
A system for quickly accessing remote storage equipment based on FPGA comprises a receiving module, an arbitration module and a storage module, wherein the receiving module is connected with the arbitration module and is configured to package data transmission tasks into descriptors and send the descriptors to the arbitration module, and the arbitration module is connected with the storage module and is configured to send data transmitted by the data transmission tasks corresponding to the descriptors to the storage module for storage according to the descriptors. The system for quickly accessing the remote storage device based on the FPGA provided by the invention is used for performing the functions of device handshake protocol in the active reverse direction, register transfer descriptor logic, polling arbitration and multi-channel output. The method and the device realize high-efficiency interaction with the host end, transfer data without occupying interrupt resources, link a plurality of storage devices, realize storage balance load, adopt register configuration to transfer descriptor execution, improve hardware execution efficiency, process host end requests in batches and improve system access storage device efficiency.
Description
Technical Field
The invention belongs to the field of computer storage, and particularly relates to a system for quickly accessing remote storage equipment based on an FPGA.
Background
Because the FPGA has the advantages of high speed, high efficiency, flexibility, stability, high integration level and the like, the FPGA is very necessary in hardware logic verification and design. For data transfer to high-speed peripherals, an effective way is to bypass the CPU, access the memory directly, and transfer blocks of data directly between the peripheral and the memory. The transmission of the external hardware is completed without intervention of a CPU, and the CPU can perform read/write operation on the external storage through the port address of the CPU so as to initialize the quick access remote storage device or inquire the state of the quick access remote storage device. But it is significantly different from the general interface circuit in that the fast access remote storage device can obtain system bus control, and when it obtains system bus control, it can provide a series of control signals to control data transmission between peripheral and memory like CPU. That is, the fast access remote storage device has two operating states, a slave state (or called dynamic) as an interface circuit, a master state (or called active) controlled by the CPU, and a control system bus. The data transmission mode of the remote storage device control memory and the peripheral is completely different from the mode of the CPU. In the design of FPGA and ASIC, the fast access remote storage device can greatly save CPU interrupt resources and has higher transmission rate, thus being widely applied to data transmission systems. At present, when the remote equipment performs data transmission, the remote equipment is mostly dependent on the interaction of CPUs at two ends, the CPU interruption needs to be frequently triggered, and when the data is carried, the CPU is required to complete access and carrying operations, so that a large amount of bus resources for data transmission are consumed. The prior art has the following defects that 1, remote storage is accessed, a large amount of CPU interrupt resources are required to be occupied, 2, byte transmission is adopted more, data block transmission cannot be realized, and 3, the transmission rate is low, and a plurality of storage devices cannot be accessed simultaneously.
Therefore, a system for quickly accessing a remote storage device is needed to complete the movement and remote transmission of memory block data without requiring the CPU to participate in the transmission.
Disclosure of Invention
In order to solve the above problems, the present invention provides a system for quickly accessing a remote storage device based on FPGA, comprising:
a receiving module;
An arbitration module;
A storage module;
The receiving module is connected with the arbitration module and is configured to package data transmission tasks into descriptors and send the descriptors to the arbitration module;
The arbitration module is connected with the storage module and is configured to send the data transmitted by the data transmission task corresponding to the descriptor to the storage module for storage according to the descriptor.
In some embodiments of the present invention, the arbitration module includes an arbiter and a plurality of handshake modules,
Wherein the arbiter is configured to receive the descriptors of the receiving modules and to assign the descriptors to corresponding handshake modules.
In some embodiments of the present invention, the memory module includes a plurality of memory channels and a plurality of memory devices, where the plurality of memory channels are connected to the plurality of memory devices in a one-to-one correspondence.
In some embodiments of the present invention, the receiving module includes a configuration register module configured to receive the data transmission task and parse the data transmission task and encapsulate the parsed data transmission task into the descriptor.
In some embodiments of the invention, the configuration register module is further configured to:
acquiring the data transmission task, and configuring a descriptor control word of the descriptor according to a preset transmission specification;
configuring a storage channel of the descriptor according to a source address and a destination address of the data transmission task;
configuring the number of transmission bytes of the descriptor according to the data size of the data transmission task;
and configuring the source equipment and the destination equipment of the descriptor according to the source address and the destination address of the data transmission task.
In some embodiments of the invention, the arbiter is further configured to:
And monitoring the plurality of handshake modules, responding to the fact that destination equipment and/or storage channels in the descriptors in the plurality of handshake modules are the same, and initiating handshake requests by the plurality of handshake modules and a main terminal, arbitrating the handshake requests of the plurality of handshake modules and controlling the storage channels in the storage modules.
In some embodiments of the invention, the arbiter is further configured to;
And monitoring the plurality of handshake modules, and arbitrating the use of the corresponding storage channels in the storage modules by the plurality of handshake modules except the handshake modules where the descriptors are located in response to the source equipment and the destination equipment in the descriptors in any handshake module being in the storage modules.
In some embodiments of the present invention, the storage module further includes a buffer module configured to buffer data in the arbitration module and/or the storage module that cannot be stored in time.
In some embodiments of the invention, the receiving module further comprises a descriptor queue configured to receive and buffer the descriptors encapsulated by the configuration register module.
In some embodiments of the invention, a plurality of handshake modules acquire data in the data transfer task from a data bus on which the system is mounted in a reverse handshake manner.
The system for quickly accessing the remote storage device based on the FPGA provided by the invention is used for performing the functions of device handshake protocol in the active reverse direction, register transfer descriptor logic, polling arbitration and multi-channel output. The method and the device realize high-efficiency interaction with the host end, transfer data without occupying interrupt resources, link a plurality of storage devices, realize data interaction of the storage devices and realize storage balance load in the invention, adopt register configuration to transfer descriptor execution, improve hardware execution efficiency, process host end requests in batches and improve system access storage device efficiency.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a system for fast accessing a remote storage device based on an FPGA according to an embodiment of the present invention;
FIG. 2 is a data handshake diagram of one embodiment of a system for fast access to a remote storage device based on an FPGA according to the present invention;
FIG. 3 is a data handshake diagram of one embodiment of a system for fast access to a remote storage device based on an FPGA provided by the present invention;
Fig. 4 is a data handshake diagram of an embodiment of a system for fast access to a remote storage device based on FPGA according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, to solve the above problems, the present invention proposes a system for fast accessing a remote storage device based on FPGA, comprising:
a receiving module 1;
an arbitration module 2;
A storage module 3;
Wherein the receiving module 1 is connected with the arbitration module 2 and is configured to package data transmission tasks into descriptors and send the descriptors to the arbitration module 2;
The arbitration module 2 is connected with the storage module 3, and is configured to send data transmitted by the data transmission task corresponding to the descriptor to the storage module 3 for storage according to the descriptor.
In this embodiment, as shown in fig. 1, the present invention proposes a system for quickly accessing a remote storage device through programming an FPGA chip, where the system proposed in the present invention generally includes a large module, i.e., a receiving module 1, an arbitration module 2, and a storage module 3, where the receiving module 1 is responsible for receiving a data transmission task of a data bus mounted on the system for quickly accessing a remote storage device proposed in the present invention (hereinafter referred to as a system for short), and resolving and encapsulating the data transmission task into a descriptor defined in the system provided in the present invention, further sending the descriptor to the arbitration module 2, and performing a corresponding data processing operation by the arbitration module 2 according to the content of the descriptor. And the data in the data transmission task is sent to a storage module to realize storage. Or the corresponding data is read from the storage module according to the content of the descriptor and sent to the data bus mounted by the system, the data bus mounted by the system is not limited, and the system can be adapted according to the data transmission requirements of different buses, for example, the system is applied to high-speed buses of computers such as PCIE buses.
The data bus in some embodiments of the present invention also refers to an end device data bus, which also accompanies data interaction with the end device when a handshake requirement occurs.
In some embodiments of the present invention, the arbitration module includes an arbiter and a plurality of handshake modules,
Wherein the arbiter is configured to receive the descriptors of the receiving modules and to assign the descriptors to corresponding handshake modules.
As shown in fig. 1, the arbitration module 2 includes an arbiter 6 and a plurality of handshake modules 7, the arbiter 6 is connected to the reception module 1, acquires descriptors issued in the reception module 1, and transmits the descriptors to the plurality of handshake modules 7.
In some embodiments of the present invention, the memory module includes a plurality of memory channels 8 and a plurality of memory devices 10, where the plurality of memory channels are connected to the plurality of memory devices in a one-to-one correspondence.
As shown in fig. 1, in this embodiment, the memory module 3 includes a plurality of memory channels 8, each of which is independently connected to a memory device. The system realizes the management and data transmission of a plurality of external storage devices through a plurality of storage channels 8. And the storage channel is a channel linked with the storage equipment and has an AXI master-slave bus function and is used for receiving the descriptor, analyzing the descriptor, finishing read-write interaction with the storage equipment, reading the data of the designated address and transmitting the data to the designated address.
In some embodiments of the present invention, the receiving module includes a configuration register module configured to receive the data transmission task and parse the data transmission task and encapsulate the parsed data transmission task into the descriptor.
In this embodiment, the receiving module 1 includes a configuration register module 4, where the configuration register 4 is connected to a data bus on which the system is mounted, receives a data transmission command, that is, a data transmission task, from a host device on which the system is mounted, and parses and encapsulates the data transmission task, and encapsulates the data transmission task into a descriptor supported by the system. Specifically, taking a system-mounted PCIE bus as an example, the configuration register module 4 communicates with the CPU, receives a data access control command issued by the CPU, parses the command, and encapsulates the command into the following structure:
The descriptor control word, memory channel, transmission byte number, source address and destination address, and the configuration capable of continuous multiple transmission.
The descriptor control word is formulated according to the data transmission specification of the system provided by the invention, the storage channel represents the storage channel 8 corresponding to the internal storage device through which the data is transmitted in the system, the transmission byte number represents the size of the data transmission task, the source address represents the source of the data transmission data, the destination address represents the data sending address of the data transmission task, the data transmission can be continuously carried out for multiple times to represent whether the task can be transmitted in a breakpoint, and the data can be decomposed into multiple times to be transmitted to the destination address according to the busy condition of the task of the system.
In some embodiments of the invention, the configuration register module is further configured to:
acquiring the data transmission task, and configuring a descriptor control word of the descriptor according to a preset transmission specification;
configuring a storage channel of the descriptor according to a source address and a destination address of the data transmission task;
configuring the number of transmission bytes of the descriptor according to the data size of the data transmission task;
and configuring the source equipment and the destination equipment of the descriptor according to the source address and the destination address of the data transmission task.
In this embodiment, the configuration register module 4 parses and encapsulates the received data task, i.e. configures the descriptor control word for data transmission in the subsequent module according to the transmission specification provided by the system of the present invention, determines the storage channel 8 used in the subsequent data transmission according to the source address and the destination address of the data transmission task, specifically, if the task is a task of writing data, determines the storage channel connected to the storage device according to the destination writing storage device. The memory channel is written in the configuration register module 4 into the descriptor of the data transfer task in the system of the invention.
In addition, the descriptor also has the number of data transmission bytes for recording the size of the data transmission time. Including the overall size of the data and the block size at the time of transmission in block storage.
In addition, the source address and destination address of the data transfer task are added to the descriptor.
In some embodiments of the invention, the arbiter is further configured to:
And monitoring the plurality of handshake modules, responding to the fact that destination equipment and/or storage channels in the descriptors in the plurality of handshake modules are the same, and initiating handshake requests by the plurality of handshake modules and a main terminal, arbitrating the handshake requests of the plurality of handshake modules and controlling the storage channels in the storage modules.
In this embodiment, after each descriptor is sent to each handshake module 7, the arbiter 6 also needs to monitor the data transmission task executed in each handshake module 7, if there are two handshake modules 7 that use the same memory channel at the same time, and both handshake modules 7 acquire or send data from the data bus in a handshake manner, and need to store the data to the corresponding memory device through the same memory channel, or read the corresponding data from the same memory device and send the data to the data bus. At this time, in order to prevent the two handshake modules 7 from simultaneously using one memory channel to cause abnormal data transmission, the arbiter 6 arbitrates the plurality of handshake modules 7 that are behind in sequence, and prohibits the plurality of handshake modules 7 from performing data interaction with the data bus in a handshake manner. Only the preceding one of the handshake modules 7 can carry out data transfer with the data bus by means of handshake. And at the same time controls the corresponding memory channel 8, only the data in the reserved handshake module 7 can be received.
In some embodiments of the invention, the arbiter is further configured to;
And monitoring the plurality of handshake modules, and arbitrating the use of the corresponding storage channels in the storage modules by the plurality of handshake modules except the handshake modules where the descriptors are located in response to the source equipment and the destination equipment in the descriptors in any handshake module being in the storage modules.
In this embodiment, when the destination device and the source device in the descriptor are both storage devices connected to the storage module, it indicates that the data transmission is considered to be capable of implementing data transmission only through two or more storage channels in the system without being controlled by other devices outside the system of the present invention. The arbiter 6 arbitrates the use of the memory channel by the other handshake modules 7, and only the use of the memory channel by the handshake module in which the descriptor is located is reserved.
In some embodiments of the present invention, the storage module further includes a buffer module configured to buffer data in the arbitration module and/or the storage module that cannot be stored in time.
The memory module 3 further comprises a buffer module 9 in this embodiment, where the buffer module 9 is configured to buffer the handshake module 7 or the data acquired from the memory channel. The BUFFER module 9 is constituted by a BUFFER device for buffering data from the end device data bus retrieved according to a handshake protocol.
In some embodiments of the invention, when the arbiter in the arbitration module 2 arbitrates the handshake module, part of the handshake module 7 may be allowed to handshake with the data bus according to the capacity in the buffer module 9, but the data obtained by the handshake module 7 is not transferred through the memory channel 8 already used by the other handshake module 7, but buffered in the buffer module 9. Specifically, when the remaining space in the buffer module 9 is above 50%, the arbiter judges the number of transmission bytes in the descriptor corresponding to the arbitrated handshake module, and if the number of transmission bytes in the descriptor is lower than 5% of the total capacity of the buffer module, the corresponding handshake module 7 is operated to perform handshake interaction with the data bus to obtain corresponding data, and the corresponding data is buffered in the buffer module 9.
Furthermore, in some embodiments of the present invention, when a certain handshake module 7 performs data transfer between a plurality of memory devices within a memory module, other handshake modules that are connected to and acquire data from the data bus may normally perform a handshake interaction procedure to acquire data from the data bus and buffer the data to the buffer module 9.
In some embodiments of the invention, the receiving module further comprises a descriptor queue configured to receive and buffer the descriptors encapsulated by the configuration register module.
In this embodiment, the receiving module 1 is further provided with a descriptor queue 5 for caching descriptors generated by the configuration register module 4. The arbiter 6 may obtain descriptors from the descriptor queue 5 and send them to the handshake module.
In some embodiments of the present invention, when a certain descriptor configuration parameter includes a configuration that can be transmitted continuously for a plurality of times, the data transmission of the descriptor by the arbiter 6 can be flexibly interrupted, that is, when the transmission load of the system provided by the present invention is full, other descriptors can be processed preferentially. Specifically, the descriptor is sent to the descriptor queue 5, and the data transmission task represented by the descriptor is completed in multiple times.
In some embodiments of the invention, a plurality of handshake modules acquire data in the data transfer task from a data bus on which the system is mounted in a reverse handshake manner.
In this embodiment, in the present invention, the handshake module 7 does not receive data from the data bus, but obtains corresponding data from the data bus through an interaction manner of the reverse handshake proposed by the present invention, and sends the data to the corresponding storage channel 8 after passing through the buffer module 9, and further transmits the data to the storage device 10.
In this embodiment, the handshake module 7 and the Data bus acquire Data in a handshake manner as shown in fig. 2, and the system provided by the invention generates a corresponding descriptor in the configuration register module, after the handshake module obtains the descriptor for reading the Data from the Data bus by the arbiter 6, the handshake module 7 in the system initiates a Cfg 1Read request to the Data bus, the Data bus responds to Cfg 1CPL under the condition permission, then the handshake module 7 initiates a Data Read request to the Data bus, and then the Data on the Data bus is sent to the storage channel 8 corresponding to the descriptor and further sent to the storage device 10. After the data transmission on the data bus is completed, the data bus sends a CPLD response to the handshake module, indicating that the data transmission is completed, and the system stores the data to the memory device 10 through the corresponding memory channel. It should be noted that, the source address and the destination address in the descriptor not only refer to the corresponding storage device 10 but also include the corresponding data storage address.
In some embodiments of the present invention, a process of sending data to the data bus by the handshake module 7 is shown in fig. 3, specifically, after the handshake module 7 obtains the corresponding descriptor, the handshake module initiates a handshake request cfg 1Read with the data bus according to the descriptor;
The data bus responds to Cfg 1CPL under conditional permission;
the system reads the data formulated in the descriptors from the corresponding storage devices 10 through the storage channels 8, and sends the data to the data bus or the buffer module 9, and after all the data are sent to the data bus, the storage devices 10 respond to the CPLD and send the data to the handshake module 7;
after receiving CPLD, the system initiates DATA WRITE handshake request to the data bus;
The data bus processes the relevant data after receiving DATA WRITE and sends a response WREQ CMPLT to the handshake module in the system after processing is completed. The handshake module 7 completes the transfer of data to the data bus.
In some embodiments of the present invention, the handshake interaction procedure of data transmission between the storage devices 10 is as shown in fig. 4, and the system sends the corresponding Cfg 1Rread to the data bus through the handshake module 7;
data bus response Cfg 1CPL;
The system performs Data transfer, namely Data exchange, on Data among a plurality of storage devices 10 through a plurality of internal storage channels;
after the data transmission is completed, a CPLD response is returned to the system from the storage device;
After receiving the CPLD, the system sends EX CPL to the data bus through a handshake module 7;
the data bus responds Exreq cmplt that the data transfer task is complete.
The system for quickly accessing the remote storage device based on the FPGA provided by the invention is used for performing the functions of device handshake protocol in the active reverse direction, register transfer descriptor logic, polling arbitration and multi-channel output. The method and the device realize high-efficiency interaction with the host end, transfer data without occupying interrupt resources, link a plurality of storage devices, realize data interaction of the storage devices and realize storage balance load in the invention, adopt register configuration to transfer descriptor execution, improve hardware execution efficiency, process host end requests in batches and improve system access storage device efficiency.
In the system provided by the invention, the transmission of the handshake module 7 and the data bus and the generation of the descriptor by the configuration register module 4 can realize decoupling, namely, the configuration register module 4 is only responsible for acquiring the corresponding data transmission task and generating the corresponding descriptor, and then the handshake module 7 is responsible for communicating with the data bus. The handshake module 7 may perform handshake interactions with the data bus initiated by the handshake module 7 as long as the arbiter arbitrates to allow. And the data transmission tasks are generated by FPGA programming, the number of handshake modules and the number of configuration registers can be configured according to the pressure of the data transmission tasks, flexible allocation is realized, and the data transmission tasks which are originally executed through the main control chip are executed in parallel through a plurality of handshake modules 7.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It will be appreciated by persons skilled in the art that the foregoing discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples, that combinations of features of the above embodiments or of different embodiments may be made and that many other variations of the different aspects of the embodiments of the invention described above exist within the spirit of the embodiments of the invention, which are not provided in detail for clarity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (5)
1. A system for fast access to a remote storage device based on an FPGA, comprising:
a receiving module;
An arbitration module;
A storage module;
The receiving module is connected with the arbitration module and is configured to package data transmission tasks into descriptors and send the descriptors to the arbitration module;
The arbitration module is connected with the storage module and is configured to send the data transmitted by the data transmission task corresponding to the descriptor to the storage module for storage according to the descriptor;
Wherein the arbitration module comprises an arbiter and a plurality of handshake modules, wherein the arbiter is configured to receive the descriptors of the receiving modules and assign the descriptors to the corresponding handshake modules;
The receiving module comprises a configuration register module, wherein the configuration register module is configured to receive the data transmission task and package the data transmission task into the descriptor after analysis;
the configuration register module is further configured to acquire the data transmission task, configure a descriptor control word of the descriptor according to a preset transmission specification, configure a storage channel of the descriptor according to a source address and a destination address of the data transmission task, configure a transmission byte number of the descriptor according to a data size of the data transmission task, and configure source equipment and destination equipment of the descriptor according to the source address and the destination address of the data transmission task;
The arbiter is further configured to monitor the plurality of handshake modules, and to arbitrate use of a corresponding storage channel in the storage module by the plurality of handshake modules other than the handshake module in which the descriptor is located in response to the source device and the destination device in the descriptor in any one of the handshake modules being in the storage module, to only reserve use of the storage channel by the handshake module in which the descriptor is located;
The storage module further comprises a buffer module, the buffer module is configured to buffer the arbitration module and/or data which cannot be stored in time in the storage module, and when the arbiter in the arbitration module arbitrates the handshake module, part of the handshake module is allowed to handshake interaction with the data bus according to the available capacity of the buffer module.
2. The system of claim 1, wherein the memory module comprises a plurality of memory channels and a plurality of memory devices, the plurality of memory channels being connected in a one-to-one correspondence with the plurality of memory devices.
3. The system of claim 1, wherein the arbiter is further configured to:
And monitoring the plurality of handshake modules, responding to the fact that destination equipment and/or storage channels in the descriptors in the plurality of handshake modules are the same, and initiating handshake requests by the plurality of handshake modules and a main terminal, arbitrating the handshake requests of the plurality of handshake modules and controlling the storage channels in the storage modules.
4. The system of claim 1, wherein the receiving module further comprises a descriptor queue configured to receive and buffer the descriptors encapsulated by the configuration register module.
5. The system of claim 1, wherein the plurality of handshake modules acquire data in the data transfer task from a data bus on which the system is mounted in a reverse handshake.
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| CN112765059A (en) * | 2021-01-20 | 2021-05-07 | 苏州浪潮智能科技有限公司 | DMA (direct memory access) equipment based on FPGA (field programmable Gate array) and DMA data transfer method |
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| JP2004021613A (en) * | 2002-06-17 | 2004-01-22 | Seiko Epson Corp | Data transfer control device, electronic device, and data transfer control method |
| WO2010150654A1 (en) * | 2009-06-25 | 2010-12-29 | 日本電気株式会社 | Asynchronous logic circuit, congestion avoiding path calculation module, semiconductor circuit, and path calculation method in asynchronous logic circuit |
| US8285912B2 (en) * | 2009-08-07 | 2012-10-09 | Arm Limited | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure |
| TW201339842A (en) * | 2012-03-20 | 2013-10-01 | Copystar Backup & Storage Corp | Cooperative bus arbitration multitasking architecture and data access arbitration in accordance with the architecture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8880756B1 (en) * | 2013-07-01 | 2014-11-04 | Atmel Corporation | Direct memory access controller |
| CN112765059A (en) * | 2021-01-20 | 2021-05-07 | 苏州浪潮智能科技有限公司 | DMA (direct memory access) equipment based on FPGA (field programmable Gate array) and DMA data transfer method |
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