CN114063918A

CN114063918A - Data access method, memory storage device and memory controller

Info

Publication number: CN114063918A
Application number: CN202111340766.0A
Authority: CN
Inventors: 刘梓键
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-18
Anticipated expiration: 2041-11-12
Also published as: CN114063918B

Abstract

The invention provides a data access method, a memory storage device and a memory controller. The method comprises the following steps: establishing a state bitmap of an entity unit, wherein the state bitmap is used for storing management information of the entity unit; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and establishing an entity window table for managing the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is accomplished according to the logic-to-entity mapping table. Thus, the speed of access of large files and large data from a host system to memory storage devices and memory modules can be significantly increased; even the small SRAM capacity in the memory storage and memory modules allows for the speed of large file accesses from a host system to the memory modules.

Description

Data access method, memory storage device and memory controller

Technical Field

The present invention relates to memory management technologies, and in particular, to a data access method, a memory storage device, and a memory controller.

Background

Non-volatile memory modules, such as flash memory modules, have the advantages of non-volatile storage of data, low power consumption, and fast data access. For the nonvolatile memory module such as NAND FLASH, there is a corresponding method for bad block management because the manufacturing process and the storage principle determine that bad blocks are inevitably generated during the production process and the use process. However, the conventional management method manages the blocks in units of blocks, and as long as the number of bad pages or bad pages in the block exceeds a limit value, the block is discarded without use. It is known that the management method using blocks as units has a problem of low flash memory utilization. As the capacity of each block is increased with the development of flash memories, the whole block is discarded, which results in a great waste, and therefore, it is very necessary to provide a management method based on page unit.

Disclosure of Invention

The invention provides a data access method, a memory storage device and a memory controller, which can improve the speed of accessing data from a host system to the memory storage device.

An embodiment of the present invention provides a data access method for a memory storage device, wherein the memory storage device includes a memory module, the memory module includes at least one physical unit, the physical unit includes a plurality of physical programming units, and the data access method includes: establishing a state bitmap of the entity unit, wherein the state bitmap is used for storing management information of the entity unit, and the management information comprises the total number of entity programming units of the entity unit, the number of the entity programming units with effective states and address values of the effective entity programming units in the entity unit; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing entity window tables of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is accomplished according to the logic-to-entity mapping table.

Optionally, an embodiment of the present invention further provides a memory storage device, including: a connection interface for connecting to a host system; a memory module comprising at least one physical unit; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to establish a status bitmap of the physical units, the status bitmap is used to store management information of the physical units, and the management information includes a total number of physical programming units of the physical units, a number of physical programming units whose status is valid, and address values of the valid physical programming units in the physical units; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing entity window tables of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is accomplished according to the logic-to-entity mapping table.

Optionally, an embodiment of the present invention further provides a memory controller, configured to control a memory module, where the memory module includes at least one physical unit, and the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; the memory control circuit is used for establishing a state bitmap of the entity unit, the state bitmap is used for storing management information of the entity unit, and the management information comprises the total number of entity programming units of the entity unit, the number of the entity programming units with valid states and address values of the valid entity programming units in the entity unit; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing entity window tables of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is accomplished according to the logic-to-entity mapping table.

By this, the speed of accessing large files and data from the host system to the memory storage device and memory module can be significantly increased; even the small SRAM capacity in the memory storage and memory modules allows for the speed of large file accesses from a host system to the memory modules.

Drawings

FIG. 1 is a schematic diagram of a memory storage device shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a memory controller according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the invention;

FIG. 4 is a schematic diagram illustrating a management memory module according to an embodiment of the present invention;

FIG. 5 is a flow chart illustrating a data access method according to an embodiment of the invention;

FIG. 6 is a diagram illustrating a status bitmap, according to an embodiment of the present invention;

FIG. 7 is a flow chart illustrating a method of interval value model building according to an embodiment of the present invention;

FIG. 8 is a flow chart illustrating a method of interval value model building according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a physical window table according to an embodiment of the present invention;

FIG. 10 is a flowchart illustrating a method for establishing a logic-to-entity mapping table according to an embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating mapping of logical entity program cells to corresponding entity program cells according to an embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating the mapping of "page-by-page" logical entity program cells to corresponding entity program cells according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage device shown in accordance with an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 may be any type of computer system. For example. The host system 11 can be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, and a digital camera. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state disk, a U-disk, a memory card, or other type of non-volatile storage device. The host system 11 may be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Thus, the host system 11 may store data to the memory storage device 12 and/or read data from the memory storage device 12.

Memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 may communicate with the host system 11 via the connection interface 121.

The memory module 122 is used to store data. The memory module 122 may include a rewritable non-volatile memory module. The memory module 122 includes an array of memory cells. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi-Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be used to control memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable Logic controller (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.

In one embodiment, memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access the memory cells according to the sequence of instructions.

FIG. 2 is a schematic block diagram of a memory controller according to an exemplary embodiment of the present invention. Referring to fig. 2, the memory controller 123 includes a memory control circuit 1233, a host interface 1231, and a memory interface 1232.

The memory control circuit 1233 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 1233 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 12. When the operation of the memory control circuit 1233 is described below, the operation of the memory controller 123 is equivalently described.

In the present exemplary embodiment, the control instructions of the memory control circuit 1233 are operated in the form of firmware. For example, the memory control circuit 1233 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 12 is in operation, the control instructions are executed by the microprocessor unit to perform data writing, reading, and erasing operations.

In another exemplary embodiment, the control instructions of the memory control circuit 1233 may also be stored in the form of program code in a specific area of the memory module 122 (e.g., a system area of the memory module dedicated to storing system data). Further, the memory control circuit 1233 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (pcode), and when the memory controller 123 is enabled, the mcu first executes the boot code to load the control instructions stored in the memory module 122 into the ram of the memory control circuit 1233. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory control circuit 1233 may also be operated in a hardware manner. For example, the memory control circuit 1233 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the memory module 122. The memory write circuit is configured to issue a write command sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a sequence of read commands to the memory module 122 to read data from the memory module 122. The memory erase circuit is used for issuing an erase command sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit is used for processing data to be written into the memory module 122 and data read from the memory module 122. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the memory module 122 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory control circuit 1233 may issue other types of command sequences to the memory module 122 to instruct the corresponding operations to be performed.

The host interface 1231 is electrically connected to the memory control circuit 1233 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted from the host system 11 are transmitted to the memory control circuit 1233 through the host interface 1231. In the exemplary embodiment, host interface 1231 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 1231 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 1232 is electrically connected to the memory control circuit 1233 and is used for accessing the memory module 122. That is, the data to be written into the memory module 122 is converted into a format accepted by the memory module 122 through the memory interface 1232. Specifically, if the memory control circuit 1233 is to access the memory module 122, the memory interface 1232 transmits a corresponding sequence of instructions. For example, the instruction sequences may include a write instruction sequence indicating to write data, a read instruction sequence indicating to read data, an erase instruction sequence indicating to erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). Such sequences of instructions may be generated, for example, by memory control circuitry 1233 and transferred to memory module 122 via memory interface 1232. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In the exemplary embodiment, the memory controller 123 may perform single-frame (single-frame) coding on data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on data stored in a plurality of physical program units. Depending on the encoding algorithm employed, the memory controller 123 may encode the data to be protected to generate corresponding error correction codes and/or error check codes.

In an exemplary embodiment, the memory controller 123 further includes a buffer 1235, an error checking and correcting circuit 1234 and a power management circuit 1236. The buffer 1235 is electrically connected to the memory control circuit 1233 and is used for temporarily storing data and instructions from the host system 11 or data from the memory module 122. The power management circuit 1236 is electrically connected to the memory control circuit 1233 and is used for controlling the power of the memory storage device 12. The error checking and correcting circuit 1234 is electrically connected to the memory control circuit 1233 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory control circuit 1233 receives a write command from the host system 11, the error checking and correcting circuit 1234 generates a corresponding Error Correcting Code (ECC) and/or Error Detecting Code (EDC) for data corresponding to the write command, and the memory control circuit 1233 writes the data corresponding to the write command and the corresponding error correcting code and/or error detecting code into the memory module 122. Thereafter, when the memory control circuit 1233 reads data from the memory module 122, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 1234 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the invention. Referring to fig. 1 to 4, the memory module 122 includes a plurality of physical units 301(1) -301 (a). Each physical unit includes a plurality of memory cells and is used for non-volatile storage of data. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more physical pages. A plurality of memory cells in a physical programming cell can be programmed simultaneously to store data. In addition, all memory cells in a physical block can be erased simultaneously.

In one embodiment, the physical units 301(1) -301(A) in the memory module 122 are divided into the data area 31. The entity units 301(0) to 301(a) in the data area 31 store data from the host system 11.

In one embodiment, the memory control circuitry 1233 may configure a plurality of logic cells 302(0) -302 (B) to map physical cells in the data region 31. For example, a logical unit may consist of one or more logical addresses. The mapping relationship between the logic unit and the entity unit can be recorded in the logic-to-entity mapping table. When receiving an access command from the host system 11, the memory control circuit 1233 may access data to the physical units in the data region 31 according to the corresponding logical-to-physical mapping table. Specifically, such mapping is block mapping.

In one embodiment, the memory control circuit 1233 may configure a plurality of logical entity programming units 42(0) -42 (E) to map the entity programming units 41(0) -41 (D) in the entity units 301 in the data region 31. For example, a logical entity programming unit may be composed of one or more logical entity programming addresses. The mapping relationship between the logic entity programming unit and the entity programming unit can be recorded in the logic-to-entity mapping table of the logic entity programming unit and the entity programming unit. When receiving an access command from the host system 11, the memory control circuit 1233 may access data to the physical units in the data region 31 according to the corresponding logical-to-physical mapping tables of the logical-to-physical program units and the physical program units. Specifically, the mapping is page mapping.

Fig. 4 is a schematic diagram of managing physical units in a memory module according to an embodiment of the present invention, which is a logical-to-physical mapping diagram of a logical-to-physical programming unit mapping to a physical programming unit in the physical units 301 (1). Wherein D is the total number of physical programming units of the physical units 301(1), which includes the value of the valid physical programming unit and the value of the invalid physical programming unit of the physical units 301 (1); the numerical value of the effective entity programming unit is less than or equal to D; which is a positive integer. E is a positive integer less than or equal to D; the value of E indicates that it is the value of the active physical programming cell in the physical cells 301 (1).

In an embodiment, the present application provides a data access method for a memory storage device 12, wherein the memory storage device 12 includes a memory module 122, the memory module 122 includes at least one entity unit 301(E) (E is an address value of the entity unit), the entity unit includes a plurality of entity programming units 41(0) -41 (C), and particularly, the data access method of the entity programming units includes an entity programming unit 41(F) with an invalid state (F is an address value of the entity programming unit), as shown in fig. 5, the data access method includes:

step S501, carrying out erasing, data writing and reading test operations on the entity unit, and establishing a state bitmap of the entity unit, wherein the state bitmap is used for storing management information of the entity unit, and the management information comprises the total number of entity programming units of the entity unit, the number of the entity programming units with effective states and address values of the effective entity programming units in the entity unit;

s502, dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing entity window tables of the entity windows;

s503, establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value;

and S504, realizing the data access from the host system to the memory storage device according to the logic-to-entity mapping table.

Specifically, for step S501, in an embodiment, a method for constructing a state bitmap is provided, specifically, the method includes performing erase, data write, and data write/read test operations on the entity units 301(1) -301(a) to construct a state bitmap of the entity units 301(1) -301(a), where the state bitmap is used to store management information of the entity units, and the management information includes information of a total number of entity program units in the entity units, information of a number of entity program units whose states are invalid, information of a number of entity program units whose states are valid, and address values of valid entity program units in the entity units. For example, taking a physical unit including 32 physical program units as an example, after performing erase, data write/read test operations, the state bitmap diagram shown in fig. 6 is obtained.

In one embodiment, the physical programming cells with the invalid state are represented by "1" and the physical programming cells with the valid state are represented by "0", as shown in FIG. 6.

As shown in fig. 6, the physical units include 18 effective physical programming units and 14 ineffective physical programming units; the addresses of the 18 effective physical programming units are respectively: p0, P2, P3, P4, P6, P11, P12, P14, P18, P19, P20, P21, P22, P23, P25, P26, P27, P31; the addresses of the 14 invalid entity programming units are respectively: p1, P5, P7, P8, P9, P10, P13, P15, P16, P17, P24, P28, P29, P30.

In an embodiment, the present application further provides a method for constructing a logic-to-entity mapping interval value calculation model, as shown in fig. 7, which includes:

in step S702, calculating the sum of the mapping traversal times of each logical entity programming unit and the corresponding entity programming unit in the entity unit according to the total number of the entity programming units in the state bitmap of the entity unit, the number of the entity programming units with valid states, and the address values of the valid entity programming units in the entity unit; each logical entity programming unit can only perform mapping management with the entity programming unit (also called effective entity programming unit) whose state is effective.

Specifically, as shown in fig. 8, the specific operation method of step S702 includes:

substep S7021: determining an address value of each logical entity programming unit according to the number of the effective entity programming units in the state bitmap of the entity unit;

substep S7022: determining the state of each logic entity programming unit as the address of the effective entity programming unit when the mapping address dereferencing is carried out on each logic entity programming unit according to the state of each entity programming unit in the state bitmap of the entity unit;

substep S7023: making a difference between the address of the entity programming unit corresponding to each logic entity programming unit and the address of the logic entity programming unit to obtain the traversal times required by mapping management established between each logic entity programming unit and the entity programming unit;

substep S7024: and accumulating the traversal times corresponding to all the logic entity programming units to obtain the total mapping traversal time.

Exemplarily, the calculation of the traversal number can be represented by the following expression:

wherein, S is the number of traversals required for mapping management between all logic entity programming units and entity programming units in the memory module 122; nvp indicates the number of logical entity program cells, which is also the number of valid entity program cells; a represents the address of the logical entity programming unit; f (a) represents the mapping of the logical entity programming unit to the entity programming unit.

As shown in fig. 6, the physical units include 18 effective physical programming units and 14 ineffective physical programming units; the address values of the 18 effective physical programming units are respectively: p0, P2, P3, P4, P6, P11, P12, P14, P18, P19, P20, P21, P22, P23, P25, P26, P27, P31; the address values of the 14 invalid entity program units are respectively: p1, P5, P7, P8, P9, P10, P13, P15, P16, P17, P24, P28, P29, P30.

Thus, for the traversal time S required for the physical unit, since the physical unit has 18 effective physical program units, 18 mapping management is required, i.e. the address of the logical physical program unit takes a value of 0 to 17.

For the logical entity programming cell 0, there is S₀Wherein, f (0) -0-1, wherein S is₀If f (0) -0-1 means that the logical entity program unit with address 0 needs to traverse 1 time for the entity program unit with address 0 to establish mapping management.

For address 1A logic entity programming unit having S₁In the example, the state of the physical program unit with address 2 is invalid, so that mapping management needs to be performed only by mapping to a valid physical program unit, i.e., the physical program unit with address 3. For the following mapping traversal times, the same calculation method is used, and the following steps are included:

S₂＝4-2＝2；S₃＝5-3＝2；S₄＝7-4＝3；S₅＝12-5＝7；

S₆＝12-6＝6；S₇＝14-7＝7；S₈＝18-8＝10；S₉＝19-9＝10；

S₁₀＝20-10＝10；S₁₁＝21-11＝10；S₁₂＝22-12＝10；S₁₃＝23-13＝10；

S₁₄＝25-14＝11；S₁₅＝26-15＝11；S₁₆＝27-16＝11；S₁₇＝31-17＝14；

thus, for the summation of the 18 traversal times f (0) -f (17), S equals 133.

Further, as shown in fig. 7, after step S702 is executed, step S704 is executed.

In step S704, the sum of the calculated mapping traversal times is multiplied by 2, and then the ratio operation is performed on the total number of the entity programming units to obtain a ratio result, and the square root operation is performed on the ratio result to obtain a square root result. Further, after the square root result is processed correspondingly, a better mapping interval value for mapping the logical entity programming unit and the entity programming unit in the memory block can be calculated.

For example, the logical entity program unit and the entity program unit mapping interval value model constructed as above are expressed as follows:

wherein S represents the sum of the calculated traversal times required for mapping management between each logical entity program unit and the corresponding entity program unit in the memory module 122, Nvp represents the number of valid entity program units stored in the state bitmap, and X represents the square root result to be solved.

Further, after calculating the square root result, the method may further include step S706:

s706, rounding up or rounding down the square root result to obtain an integer, and taking the integer as the mapping interval value between the logic entity programming unit and the entity programming unit.

Illustratively, the interval value model is mapped by using the above logic entity programming unit and entity programming unit, namely

Approximately equal to 3.8, the mapping interval value X is 3 by rounding down (or 4 by rounding up). It is understood that the required mapping interval value can be calculated by the above-mentioned logical entity programming unit and entity programming unit mapping interval value model.

The method for constructing a logic-to-entity mapping interval value calculation model provided by the application calculates a logic entity programming unit-to-entity programming unit mapping interval value of an entity unit according to the actual conditions of the entity unit, such as the total number of the entity programming units, the number of the entity programming units with effective states and the address value of the effective entity programming units in the entity unit; the method can establish state bitmaps of different entity units according to the different entity units, calculate different interval values of the entity units and calculate mapping interval values of the entity units; constructing a logic-to-entity mapping table of the memory module 122 based on the interval values, and implementing data access from the host system 11 to the memory storage device 12 based on the constructed logic-to-entity mapping table; has the effect of increasing the speed at which data is accessed from the host system 11 to the memory storage device 12.

Specifically, for the step S502, a plurality of physical windows are divided in the physical unit according to a mapping interval value and the state bitmap, and a physical window table of the plurality of physical windows is constructed.

And establishing an entity window table for managing the entity windows, wherein the entity window table is used for storing the distribution condition of each entity window, the number of the effective entity programming units in each entity window and the number of the effective entity programming units from the starting entity window to the current entity window.

As shown in fig. 9, fig. 9 is a physical window table including 11 physical windows, which is established according to a mapping interval value of 3. The entity window table comprises the following information: distribution of each physical window: the physical window comprises 11 physical windows, the A0-A9 physical window comprises 3 physical programming units, the A10 physical window comprises 2 physical programming units, and two physical programming units in the A10 physical window are used for storing the state bitmap and the physical window table (the address values of the physical programming units stored in the state bitmap and the physical window table are omitted hereinafter and are not described again); the number of effective physical program cells (i.e. the number of "0", hereinafter abbreviated) in the physical windows A0-A10 is: a0 ═ 2, a1 ═ 2, a2 ═ 1, A3 ═ 1, a4 ═ 2, a5 ═ 0, a6 ═ 3, a7 ═ 3, A8 ═ 2, a9 ═ 1, a10 ═ 1; the number of "0" from the starting physical window to the A0-A10 physical window is: 0. 4, 5, 6, 8, 11, 14, 16, 17, 18.

In one embodiment, each physical window may include a different number of physical program cells. For example, as shown in FIG. 9, the A0-A9 physical window includes 3 physical program cells, and the A10 physical window includes 2 physical program cells.

In one embodiment, the physical program cell states included in the physical window may be different. Specifically, all of the physical program cell states in the physical window are valid, such as the A6 and A7 physical windows in FIG. 9; all physical program cell states in the physical window are invalid, such as the A5 physical window in FIG. 9; the physical window includes valid entity programming units and invalid entity programming units, such as the physical windows a0, a1, a2, A3, a4, A8, a9 and a10 in fig. 9.

Specifically, for the step S503, a logic-to-entity mapping table is established according to the entity window table and the mapping interval value, and in one embodiment, the specific operation for the step S503 is to establish the logic-to-entity mapping table according to the distribution of the entity windows and the number of effective entity program units from the starting entity window to the current entity window.

Establishing a logic-to-entity mapping table according to the distribution condition of each entity window and the number of effective entity programming units from the initial entity window to the current entity window; its further operation is shown in fig. 10, comprising sub-step S5031 and sub-step S5032.

Substep S5031, comparing the address value of the target logical entity programming unit with the number of the effective entity programming units from the starting entity window to the current entity window, and taking the minimum value of the number in all the numbers which are more than or equal to the number to determine the target entity window to which the entity programming unit corresponding to the target logical entity programming unit belongs.

For example, taking the above entity unit including 32 entity program units as an example, a mapping table of the entity program unit P20 needs to be established, and the results of L10 — P20 shown in fig. 11 are achieved on the premise that 10 invalid entity program units, P1, P5, P7, P8, P9, P10, P13, P15, P16, and P17, precede the P20 entity program units. Specifically, it is operated to find the entity window with the number of "0" in the entity window being equal to or greater than 11 (this is because Logical10 is actually the 11 th effective entity programming unit) according to the entity window table in fig. 9, as shown in fig. 9, the number of "0" in 5 entity windows of a6, a7, a8, a9, a10 is greater than 11, 14, 16, 17, 18 respectively; the target physical window to which the Logica10 belongs is determined by taking the physical window a6 in which the minimum value of all values, i.e., "0", is equal to 11.

For example, to implement L8- - -P18 shown in FIG. 11, an entity window with the number of "0" in the entity window being greater than or equal to 9 is searched (Logical8 is actually the 9 th effective entity programming unit), and as shown in FIG. 9, the number of "0" in 5 entity windows of A6, A7, A8, A9 and A10 is greater than 9, 11, 14, 16, 17 and 18 respectively; the target entity window to which the Logical8 belongs is determined by taking the entity window a6 in which the minimum value of all values, i.e., "0", is equal to 11.

For example, to implement L9- - -P19 shown in FIG. 11, an entity window (Logical9 is actually the 10 th effective entity programming unit) with the number of "0" in the entity window being greater than or equal to 10 is searched, and as shown in FIG. 9, the number of "0" in 5 entity windows A6, A7, A8, A9 and A10 is greater than 10, 11, 14, 16, 17 and 18 respectively; the target entity window to which the Logical9 belongs is determined by taking the entity window a6 in which the minimum value of all values, i.e., "0", is equal to 11.

For example, to implement L4 — P6 shown in fig. 11, an entity window with the number of "0" being greater than or equal to 5 in the entity window is searched (Logical4 is actually the 5 th effective entity programming unit), as shown in fig. 9, the number of "0" in the 5 entity windows in the 3 entity windows of a0, a1 and a2 is greater than 5, and is 2, 4 and 5 respectively; namely, the entity window A2 with the minimum value of all the numerical values, namely the number of 0's, equal to 5 is taken to determine the target entity window to which the logic 4 belongs.

For example, to implement L14 — P25 shown in fig. 11, an entity window with "0" number ≧ 15 (Logical4 is actually the 15 th effective entity programming unit) is searched, and as shown in fig. 9, the number of "0" in 5 entity windows of a8, a9, a10 is greater than 9, 16, 17, 18 respectively; namely, the entity window A8 with the minimum value of all the numerical values, namely "0", equal to 16 is taken to determine the target entity window to which the logic 14 belongs.

Substep S5032, calculating an address value of an initial entity programming unit in the target entity window according to the sequence number of the entity window and the mapping interval value, determining an address of an entity programming unit corresponding to the target logic entity programming unit, establishing a mapping relation of the target logic entity programming unit to the corresponding entity programming unit, and establishing a logic-to-entity mapping table of the logic entity programming unit in the entity unit to the entity programming unit according to the mapping relation.

Illustratively, as described above, the sequence number of the entity window a6 is 6, and the mapping interval value is 3; 18, where 18 is the starting physical program cell address value 18 in the physical window a6, i.e., the physical program cell address in the physical window a6 is P18; further, since the mapping interval value is 3, it indicates that there are three physical program cells, P18, P19 and P20, respectively, in the physical window a6, and the address values thereof are 18, 19 and 20, respectively. Still further, according to the number of "0" in the entity window a6 in fig. 9 being 3, which indicates that all of the 3 entity program units P18, P19, and P20 in the entity window a6 are valid entity program units, to implement L10 — P20, the mapping query starts from P18, and goes through 3 traversals, when traversing to P20, L10 — P20 can be established, and the mapping relationship is loaded in the logic-to-entity mapping table, so that when subsequent data is accessed from the host system to the memory module, data can be accessed from the host system to the memory module through the logic-to-entity mapping table.

Illustratively, as described above, the sequence number of the entity window a6 is 6, and the mapping interval value is 3; 18, where 18 is the starting physical program cell address value 18 in the physical window a6, i.e., the physical program cell address in the physical window a6 is P18; further, since the mapping interval value is 3, it indicates that there are three physical program cells, P18, P19 and P20, respectively, in the physical window a6, and the address values thereof are 18, 19 and 20, respectively. Still further, according to the number of "0" in the entity window a6 in fig. 9 being 3, which indicates that all of the 3 entity program units P18, P19, and P20 in the entity window a6 are valid entity program units, to implement L8 — P18, the mapping query starts from P18, and after 1 traversal, L8 — P18 can be established, and the mapping relationship is loaded in the logic-to-entity mapping table, so that when subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logic-to-entity mapping table.

Illustratively, as described above, the sequence number of the entity window a6 is 6, and the mapping interval value is 3; 18, where 18 is the starting physical program cell address value 18 in the physical window a6, i.e., the physical program cell address in the physical window a6 is P18; further, since the mapping interval value is 3, it indicates that there are three physical program cells, P18, P19 and P20, respectively, in the physical window a6, and the address values thereof are 18, 19 and 20, respectively. Still further, according to the number of "0" in the entity window a6 in fig. 9 being 3, which indicates that 3 entity program units P18, P19, and P20 in the entity window a6 are all valid entity program units, to implement L9 — P19, a mapping query starts from P18, and goes through 2 traversals, when traversing to P19, L9 — P19 can be established, and the mapping relationship is loaded in the logic-to-entity mapping table, so that when subsequent data is accessed from the host system to the memory module, data can be accessed from the host system to the memory module through the logic-to-entity mapping table.

Illustratively, as described above, the sequence number of the entity window a2 is 2, and the mapping interval value is 3; 2 × 3 ═ 6, where 6 is the starting physical program cell address value 6 in the physical window a2, i.e., the physical program cell address in the physical window a2 is P6; further, since the mapping interval value is 3, it indicates that there are three physical program cells, P6, P7 and P8, respectively, in the physical window A2, and the address values thereof are 6, 7 and 8, respectively. Still further, according to the number of "0" in the entity window a2 in fig. 9 being 1, it indicates that there are only 1 valid entity program unit P6, P7, and P8 in the entity window a2, and to implement L4-P6, the mapping query starts from P6, and goes through 1 traversal, when traversing to P6, L4-P6 can be established, and the mapping relationship is loaded in the logic-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logic-to-entity mapping table.

Illustratively, as described above, the sequence number of the entity window A8 is 8, and the mapping interval value is 3; 24, where 24 is the starting physical program cell address value 24 in the physical window A8, i.e., the physical program cell address in the physical window a6 is P24; further, since the mapping interval value is 3, it indicates that there are three physical program cells, P24, P25 and P26, respectively, in the physical window A8, and the address values thereof are 24, 25 and 26, respectively. Still further, according to the number of "0" in the entity window A8 in fig. 9 being 2, 3 entity program units P24, P25, and P26 in the entity window A8 are represented, and there are 2 valid entity program units, and to implement L14 — P25, the mapping query starts from P24, and goes through 2 traversals, and when traversing to P25, L14 — P25 can be established, and the mapping relationship is loaded in the logic-to-entity mapping table, so that when subsequent data is accessed from the host system to the memory module, data can be accessed from the host system to the memory module through the logic-to-entity mapping table.

In one embodiment, in the logic-to-entity mapping table, the address value of the entity program unit is 1 bit in size.

For example, during data reading and writing, the prior art solution stores the physical address value of each physical program unit in the buffer 1235 to realize data reading and writing. The physical address value of the entity programming unit comprises an entity unit address where the entity programming unit is located and an entity programming unit address, and the physical address value of each entity programming unit is 5 bytes (40 bits); for example, in the prior art, to implement L10 — P20, the size of the buffer 1235 needs to be 5 bytes by 32 bytes or 160 bytes; to realize the data read/write operation in the page mapping mode, the space of the buffer memory 1235 needs to be 160 bytes.

In an embodiment, if the buffer Memory 1235 is an SRAM (Static Random-Access Memory), the size of the SRAM is generally 4K-8 kbytes, and the number of physical programming units needed to be used in the data reading and writing process of the Memory module 122 is far greater than 32, so the data reading and writing speed of the Memory module 122 based on the page mapping management mode is very slow.

As shown in fig. 6 and 9, in the state bitmap and the physical window table of the physical cells, a "1" indicates a physical program cell whose state is invalid, and a "0" indicates a physical program cell whose state is valid. Further, the mapping management method for mapping the logical entity programming unit to the entity programming unit in the logical-to-entity mapping table of the present application determines the physical address of the entity programming unit corresponding to the logical entity programming unit by calculating the number of "0" and searching the address value corresponding to "0"; and "0" is 1 bit in size in the mapping table, so the address value size of the physical programming unit in the logical-to-physical mapping table is 1 bit; this reduces the size of the logical to physical mapping table.

In an embodiment, the operation method for determining the address of the physical program unit corresponding to the target logical physical program unit by calculating the address value of the initial physical program unit in the target physical window according to the sequence number of the physical window and the mapping interval value further includes:

and after the determined target entity window to which the entity programming unit corresponding to the target logic entity programming unit belongs, determining the address of the entity programming unit corresponding to the target logic entity programming unit through the traversal times less than or equal to the mapping interval value.

Illustratively, the traversal or query times of the corresponding entity program unit of the above L10- - -P20, L8- - -P18, L9- - -P19, L4- - -P6, L14- - -P25 are 3 times, 1 time, 2 times, 1 time and 2 times respectively; are less than or equal to 3 (mapping interval value).

Specifically, with respect to step S504 above, where data is accessed from the host system to the memory storage device according to the logic-to-entity mapping table, in one embodiment, data is accessed from the host system to the memory storage device according to the logic-to-entity mapping table as described herein.

In the data reading and writing process, the state bitmap and the mapping interval value are stored in the buffer memory 1235, the size stored in the buffer memory 1235 in the embodiment of the application is the number of 0, and the occupied capacity of one 0 storage is 1 bit; in one embodiment, the buffer 1235 is an SRAM (Static Random-Access Memory), which is half of a size of 4K-8 kbytes and can store 32-64K "0" s at a time; i.e., 32-64K active physical program cells. If the size of the SRAM is 4 kbytes, the physical address of the physical programming unit can be loaded into the SRAM at one time, and the storage of the 500MB data from the host system 11 to the memory storage device 12 can be quickly realized, if the size of the SRAM is calculated by taking the size of 1 physical programming unit as 16KB and if the size of 500MB data (16KB × 32K) is stored from the host system 11 to the memory storage device 12; similarly, the reading of data from the memory storage device 12 into the host system 11 may also be implemented at once. Therefore, applying the logic-to-entity mapping table constructed by the above method to the memory storage device 12 and the memory module 122 can significantly improve the speed of accessing large files and data from the host system to the memory storage device 12 and the memory module 122.

The logic-to-entity mapping management method enables the mapping management speed from the logic programming unit to the entity programming unit to be very high, and when the target logic-to-entity mapping management is carried out, the address of the entity programming unit corresponding to the target logic entity programming unit can be determined only through limited traversal by a target entity window to which the entity programming unit corresponding to the target logic entity programming unit belongs; the entity programming unit corresponding to the logic entity programming unit can be quickly determined, and a logic-to-entity mapping table is not required to be established by adopting a page-type traversal page mapping method.

FIG. 12 is a schematic diagram of a "page-wise" traversal page mapping method, as shown in FIG. 12, in the mapping management process, when the entity program units 0-3 are all valid entity program units, the mapping between the logic entity program units 0-3 and the entity program units 0-3 can be very fast, but when the entity program unit 4 is an invalid entity program unit, the logic entity program unit 4 must skip the invalid entity program unit 4 and the next valid entity program unit, i.e., the entity program unit 5, to map, if the entity program unit 5 is also an invalid entity program unit, the next valid entity program unit is skipped until the entity program unit with the valid state is skipped, and the traversal page mapping method based on the "page-wise" is affected by the invalid entity program unit, if the ratio of the number of invalid physical programming units in the physical units to the total number of the physical units is not large, the data read-write speed of the memory storage device 12 including such physical units is not greatly influenced; however, if the memory storage device 12 includes a large number of such physical units, the data read/write speed of the memory storage device 12 is greatly affected.

Further, the logic-to-entity mapping interval value calculating method provided by the present application calculates the mapping interval value of the entity unit according to the actual situation of the entity unit, such as the total number of the entity programming units; it will be appreciated that the total number of physical units is different and the mapping interval values of the physical units are different. A logical-to-physical mapping table for the memory module 122 is constructed based on the mapping interval values, thereby increasing the speed of data access from the host system 11 to the memory storage device 12.

In one embodiment, the present application also proposes a memory storage device 12, the memory storage device 12 comprising: a connection interface 121 for connecting to the host system 11; a memory module 122 comprising at least one physical unit; and a memory controller 123 connected to the connection interface 121 and the memory module 122; wherein the data access methods of fig. 5, 7, 8 and 10 can be applied on the memory controller 123. The steps in fig. 5, 7, 8 and 10 have been described in detail above, and are not repeated herein. It should be noted that, the steps in fig. 5, fig. 7, fig. 8 and fig. 10 can be operated as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 5, 7, 8 and 10 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In an embodiment, the present application also proposes a memory controller 123 for controlling a memory module 122, wherein the memory module 122 includes at least one physical unit, and the memory controller 123 includes: a host interface 1231 for connecting to a host system 11; a memory interface 1232 for connecting to the memory module 122; and memory control circuitry 1233 connected to the host interface 1231 and the memory interface 1232; wherein the data access methods of fig. 5, 7, 8 and 10 can be applied on the memory control circuitry 1233. The steps in fig. 5, 7, 8 and 10 have been described in detail above, and are not repeated herein. It should be noted that, the steps in fig. 5, fig. 7, fig. 8 and fig. 10 can be operated as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 5 and fig. 8 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the present application provides a data access method and a method for constructing a logical-to-entity mapping table; applying the above-described method to memory storage device 12 and memory module 122 may significantly increase the speed at which large files and large data are accessed from a host system to memory storage device 12 and memory module 122.

Further, the present application also provides a method for constructing a logic-to-entity mapping interval value calculation model, which calculates a logic entity programming unit-to-entity programming unit mapping interval value of an entity unit according to the actual conditions of the entity unit, such as the total number of the entity programming units, the number of the entity programming units with effective states, and the address values of the effective entity programming units in the entity unit; the method can establish state bitmaps of different entity units according to the different entity units, calculate different interval values of the entity units and calculate mapping interval values of the entity units; constructing a logic-to-entity mapping table for the memory module 122 based on the interval values, thereby increasing the speed of data access from the host system 11 to the memory storage device 12; the memory storage device 12 and the memory module 122 which are applied to the data access method, the logic-to-entity mapping table construction method and the logic-to-entity mapping interval value calculation model construction method can remarkably improve the speed of accessing large files and large data from a host system to the memory storage device 12 and the memory module 122; even though the SRAM capacity in the memory storage device 12 and memory module 122 is small, large files may be achieved embodiments of the present application may increase the speed at which data is accessed from a host system to a memory module.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data access method for a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprises at least one physical unit, the physical unit comprises a plurality of physical programming units, and the data access method comprises:

establishing a state bitmap of the entity unit, wherein the state bitmap is used for storing management information of the entity unit, and the management information comprises the total number of entity programming units of the entity unit, the number of the entity programming units with effective states and address values of the effective entity programming units in the entity unit;

dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing entity window tables of the entity windows;

establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value;

access of data from the host system to the memory storage device is accomplished according to the logic-to-entity mapping table.

2. The data access method of claim 1, wherein the method of partitioning the plurality of physical windows in the physical unit according to a mapping interval value and the status bitmap comprises: dividing the entity unit into a plurality of regions according to the mapping interval value of the logic entity programming unit in the entity unit to the entity programming unit, wherein each region comprises a plurality of entity programming units, and the region is the entity window.

3. The data access method of claim 1, wherein the mapping interval value is calculated by a logical-to-physical mapping interval value calculation model.

4. The data access method of claim 3, wherein the method for constructing the logical-to-entity mapping interval value calculation model comprises:

calculating the sum of the mapping traversal times of each logic entity programming unit in the entity units and the corresponding entity programming unit according to the total number of the entity programming units in the state bitmap of the entity units, the number of the entity programming units with the effective states and the address values of the effective entity programming units in the entity units;

and multiplying the sum of the mapping traversal times by 2, then performing ratio operation on the total number of the effective entity programming units to obtain a ratio result, and performing square root processing on the ratio result to obtain a square root result, wherein the square root result is used as a mapping interval value between the logic entity programming unit and the entity programming unit.

5. The data access method of claim 4, wherein the method of constructing the logical-to-entity mapping interval value calculation model further comprises:

and after the square root result is obtained, carrying out upward rounding or downward rounding on the square root result to obtain an integer, and taking the integer as the mapping interval value between the logic entity programming unit and the entity programming unit.

6. The data access method of claim 4, wherein the sum of the mapping traversal times of each logical physical program cell and the corresponding physical program cell in the physical cells is calculated according to the total number of the physical program cells in the status bitmap of the physical cells, the number of the physical program cells whose status is valid, and the address values of the valid physical program cells in the physical cells; the method comprises the following steps:

determining an address value of each logical entity programming unit according to the number of the effective entity programming units in the state bitmap of the entity units;

determining the state of each logic entity programming unit as the address of the effective entity programming unit when the mapping address dereferencing is carried out on each logic entity programming unit according to the state of each entity programming unit in the state bitmap of the entity unit;

making a difference between the address of the entity programming unit corresponding to each logic entity programming unit and the address of the logic entity programming unit to obtain the traversal times required by mapping management established between each logic entity programming unit and the entity programming unit;

and accumulating the traversal times corresponding to all the logic entity programming units to obtain the total mapping traversal time.

7. The data accessing method of claim 1, wherein the physical window table stores the distribution of each physical window and the number of the active physical program units from the starting physical window to the current physical window.

8. The method of claim 3, wherein the step of building a logical-to-physical mapping table based on the physical window table and the mapping interval value comprises:

and establishing a logic-to-entity mapping table according to the distribution condition of each entity window and the number of the effective entity programming units from the initial entity window to the current entity window.

9. The method of claim 8, wherein the step of establishing a logic-to-entity mapping table according to the distribution of the physical windows and the number of the active physical program units from the starting physical window to the current physical window comprises:

comparing the address value of the target logic entity programming unit with the number of the effective entity programming units from the starting entity window to the current entity window, and taking the minimum value of the number in all the numbers which are more than or equal to the number to determine the target entity window to which the entity programming unit corresponding to the target logic entity programming unit belongs;

calculating an initial entity programming unit address value in the target entity window according to the sequence number of the entity window and the mapping interval value, determining the address of the entity programming unit corresponding to the target logic entity programming unit, establishing a mapping relation of the target logic entity programming unit to the corresponding entity programming unit, and establishing a logic-to-entity mapping table of the logic entity programming unit in the entity unit to the entity programming unit according to the mapping relation.

10. The data accessing method of claim 9, wherein the operation of calculating the address value of the initial physical program unit in the target physical window according to the sequence number of the physical window and the mapping interval value and determining the address of the physical program unit corresponding to the target logical physical program unit further comprises:

11. The data accessing method of claim 9, wherein the physical program unit address value size in the logical-to-physical mapping table is 1 bit.

12. The data accessing method of claim 1, wherein the status bitmap of the physical cells indicates the physical program cells with "1" as the failed status and "0" as the valid status.

13. The data accessing method of claim 1, wherein the physical window comprises a plurality of physical programming cells consisting of valid physical programming cells and/or invalid physical programming cells.

14. The data access method of claim 1, wherein the constructing of the status bitmap of the entity unit comprises:

and carrying out erasing, data writing and data reading test operations on the entity unit to obtain a state bitmap of the entity unit.

15. A memory storage device, comprising:

a connection interface for connecting to a host system;

a memory module comprising at least one physical unit;

and a memory controller connected to the connection interface and the memory module;

wherein the memory controller is configured to perform the data access method of any of claims 1-14.

16. A memory controller for controlling a memory module, wherein the memory module comprises at least one physical unit, and the memory controller comprises:

a host interface for connecting to a host system;

a memory interface for connecting to the memory module; and

a memory control circuit connected to the host interface and the memory interface; wherein the memory control circuit is configured to perform the data access method of any of claims 1-14.