CN114039605B - A Sigma-Delta Modulator with Adjustable Gain - Google Patents

Abstract

The invention belongs to the technical field of signal processing, and in particular relates to a Sigma-Delta modulator with adjustable gain. The present invention adopts a second-order CIFB Discrete-Time Sigma-Delta modulator structure with a feedforward path, including: a first integrator, a second integrator, a gain control switch, a quantizer, a feedback DAC, and an adder. The input terminal of the first integrator is connected to the input signal and the output of the feedback DAC, the input terminal of the second integrator is connected to the output of the first integrator output, the input signal and the feedback DAC, and the output of the quantizer is fed back The DAC feeds back the input of the first integrator and the second integrator, and the input signal is scaled through a gain control switch, and the function of the adder is implemented on the first integrator, the second integrator and the quantizer circuit respectively. In the present invention, three different combinations are realized by controlling the coefficients of the gain amplifier to realize scaling of the signal transfer function (STF), while the noise transfer function (NTF) remains unchanged, thereby increasing the dynamic range of the input signal.

Description

A Sigma-Delta Modulator with Adjustable Gain

technical field

The invention belongs to the technical field of signal processing, in particular to a Sigma-Delta modulator with adjustable gain.

Background technique

Analog to Digital Converters (ADC) is a bridge connecting analog signals and digital signals, and has a wide range of applications in the field of modern communications. Because signals in nature are analog in nature, analog-to-digital converters are becoming more and more important in integrated circuits. The Sigma-Delta modulator uses Noise-Shaping and Oversampling technology to move the noise in the frequency band of interest to a higher frequency and shape it, so that the noise in the effective bandwidth is effectively suppressed, thereby improving the ADC performance. The use of sub-micron technology makes the use of lower power supply voltage, making the research and development of Sigma-Delta modulators towards low voltage, low power consumption, high precision, high speed, etc., so as to adapt to the application in the fields of biology and medical treatment. As the input signal decreases, the dynamic performance of the Sigma-Delta modulator decreases sharply. In order to alleviate the performance degradation caused by the decrease of the input signal, the input signal needs to be amplified.

The signal transfer function (STF) of the traditional second-order CIFB Discrete-Time Sigma-Delta modulator with a feedforward path will not change after the parameters are determined. The expression is as follows (1):

The noise transfer function (NTF) of the traditional second-order CIFB Discrete-Time Sigma-Delta modulator with a feedforward path will not change after the parameters are determined. The expression is as follows (2):

From the above formulas (1) and (2), it can be concluded that changing the coefficients b3, b2, and b1 will change the STF, but will not change the NTF, so the noise shaping function of the modulator remains unchanged. In the case of b3=1, b2=a2, and b1=a1, STF=1.

Contents of the invention

The present invention aims at the Sigma-Delta modulator of prior art because along with the reduction of input signal, the dynamic performance of Sigma-Delta modulator reduces sharply, proposes a kind of gain-adjustable Sigma-Delta modulator can be in the modulator part The signal amplification is completed, which reduces the requirement on the input signal amplitude.

Technical scheme of the present invention is:

A Sigma-Delta modulator with adjustable gain, comprising a first switch, a second switch, a third switch, a first adder, a second adder, a third adder, a first integrator, a second integrator, Quantizer, feedback DAC, first gain amplifier, second gain amplifier, third gain amplifier, fourth gain amplifier, fifth gain amplifier, sixth gain amplifier, seventh gain amplifier; wherein, the input end of the first gain amplifier The input signal is connected after the first switch, the output of the first gain amplifier is connected to an input of the first adder, the other input of the first adder is connected to the output of the sixth gain amplifier, and the output of the first adder The terminal is connected to the input terminal of the first integrator, and the output terminal of the first integrator is connected to the input terminal of the fourth gain amplifier; the output terminal of the fourth gain amplifier is connected to the first input terminal of the second adder, and the first input terminal of the second adder Two input ends connect the output end of the second gain amplifier, the third input end of the second adder connects the output end of the seventh gain amplifier, the output end of the second adder connects the input end of the second integrator; the second gain amplifier The input terminal of the second integrator is connected to the input signal after the second switch, and the input terminals of the sixth gain amplifier and the seventh gain amplifier are connected to the feedback output of the feedback DAC; the output of the second integrator is connected to the input terminal of the fifth gain amplifier, and the fifth gain amplifier The output of the third adder is connected to an input end of the third adder; the other input end of the third adder is connected to the output end of the third gain amplifier, and the input end of the third gain amplifier is connected to the input signal after the third switch; the third adder The output terminal of the quantizer is connected to an input terminal of the quantizer, and the quantization noise E (z) is input to the quantizer, and the output of the quantizer is the output of the Sigma-Delta modulator, and the output of the quantizer is connected to the input end of the feedback DAC simultaneously; A gain amplifier (b11, b12, b14), a second gain amplifier (b21, b22, b24), and a third gain amplifier (b31, b32, b34) have the following functions under the control of the first switch, the second switch, and the third switch Three different gain combinations make the signal transfer function change while the noise transfer function does not change.

As shown in Figure 2, the first switch, the first gain amplifier, the first adder and the first integrator are implemented by switched capacitor circuits, which specifically include: a first sub-switch, a second sub-switch, a third sub-switch, a fourth Sub-switch, fifth sub-switch, sixth sub-switch, seventh sub-switch, eighth sub-switch, ninth sub-switch, tenth sub-switch, eleventh sub-switch, twelfth sub-switch, thirteenth sub-switch , fourteenth sub-switch, fifteenth sub-switch, sixteenth sub-switch, first capacitor, second capacitor, third capacitor, fourth capacitor, fifth capacitor, sixth capacitor, seventh capacitor, eighth capacitor and transconductance amplifier; define the gain control signal as s ₁ and s ₀ , the differential input signal as _up and _un , the common mode signal as V _com , the DAC feedback signal as V _refp and V _refn , and the two-phase non-overlapping clock signal φ ₁ and φ ₂ ; wherein, the control signal of the first sub-switch is φ ₂ , one end of which is connected to V _com , and the other end is connected to one end of the first capacitor, the first capacitor is a gain capacitor; the control signal of the second sub-switch is φ ₂ , one end of which is connected to V _com , the other end is connected to one end of the second capacitor, the second capacitor is a gain capacitor; the control signal of the third sub-switch is φ ₁ ·s ₁ , one end is connected to _up , and the other end is connected to the first capacitor One terminal of the fourth sub-switch is φ ₁ ·s ₀ , one terminal of which is connected to _up and the other terminal is connected to one terminal of the second capacitor; the control signal of the fifth sub-switch is φ ₁ , one terminal of which is connected to _up and the other One end is connected to one end of the third capacitor, and the third capacitor is a sampling capacitor; the control signal of the sixth sub-switch is φ ₂ , one end of which is connected to V _refp , and the other end is connected to one end of the third capacitor; the control signal of the seventh sub-switch is φ ₂ , one end of which is connected to V _refn , the other end is connected to one end of the fourth capacitor, and the fourth capacitor is a sampling capacitor; the control signal of the eighth sub-switch is φ ₁ , one end is connected to _un , and the other end is connected to one end of the fourth capacitor; The control signal of the ninth sub-switch is φ ₁ ·s ₀ , one end of which is connected to _un and the other end is connected to one end of the fifth capacitor, which is a gain capacitor; the control signal of the tenth sub-switch is φ ₁ ·s ₁ , One end of it is connected to _un , the other end is connected to one end of the sixth capacitor, and the sixth capacitor is a gain capacitor; the control signal of the eleventh sub-switch is φ ₂ , one end is connected to V _com , and the other end is connected to one end of the fifth capacitor; The control signal of the twelve sub-switches is φ ₂ , one end of which is connected to V _com , and the other end is connected to one end of the sixth capacitor; one end of the thirteenth sub-switch is connected to the other end of the first capacitor, the other end of the second capacitor, and the third capacitor. The other end of the capacitor, the other end of the thirteenth sub-switch is connected to the negative input end of the transconductance amplifier and one end of the seventh capacitor, and the other end of the seventh capacitor is connected to the positive output end of the transconductance amplifier; one end of the fourteenth sub-switch One end of the thirteenth sub-switch is connected, the other end of the fourteenth sub-switch is connected to V _com and one end of the fifteenth sub-switch, the other end of the fifteenth sub-switch is connected to the other end of the fourth capacitor and the other end of the fifth capacitor One end, the other end of the sixth capacitor and one end of the sixteenth sub-switch; the other end of the sixteenth sub-switch is connected to the positive input end of the transconductance amplifier and one end of the eighth capacitor, and the other end of the eighth capacitor is connected to the transconductance amplifier negative output terminal; the seventh capacitor and the eighth capacitor are integral capacitors;

The second switch, the second gain amplifier, the second adder and the second integrator are realized by a switched capacitor circuit, and the structure is the same as the switched capacitor circuit of the first switch, the first gain amplifier, the first adder and the first integrator; The third switch, the third gain amplifier and the third adder are realized by a switched capacitor circuit, and the structure is the same as that of the first switch, the first gain amplifier, the first adder and the first integrator.

Through the gain control switch, the three combinations of control coefficients b11 b21 b31, b12 b22 b32, b14 b24 b34 make the signal transfer function (STF) change, and the selectable gains are 1, 2, and 4 times. The noise transfer function (NTF) does not change. Among them, the coefficient b11 b21 b31 corresponds to the signal transfer function (STF) 1 times scaling, the coefficient b12 b22 b32 corresponds to the signal transfer function (STF) 2 times scaling, and the coefficient b14 b24 b34 corresponds to the signal transfer function (STF) 4 times scaling.

The beneficial effect of the invention is that the invention reduces the requirement of the Sigma-Delta modulator on the amplitude of the input signal and increases the dynamic range of the input signal.

Description of drawings

Figure 1 shows the structure of a second-order CIFB Discrete-Time Sigma-Delta modulator with a feedforward path.

Figure 2 is the realization of the modulator gain control switched capacitor circuit.

Figure 3 is the clock signal.

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in Figure 1, the structure of the second-order CIFB Discrete-Time Sigma-Delta modulator with feed-forward path includes: first integrator 104, second integrator 105, gain control switches 101, 102 and 103, quantizer 106 , Feedback DAC107.

The input terminal of the first integrator 104 is connected to the input signal and the output of the feedback DAC107, the input terminal of the second integrator 105 is connected to the output of the first integrator output 104, the input signal and the feedback DAC107, and the quantizer 106 The output of is fed back to the input of the first integrator 104 and the second integrator 105 through the feedback DAC107, and the input signal is scaled through the gain control switches 101, 102 and 103.

Among them, the quantizer adopts a 3bits flash ADC structure, and the feedback DAC adopts a 3bits capacitor form.

Figure 2 shows the implementation of modulator control gain, where s ₁ and s ₀ are the gain control signals, u _p and u _n are the input signals, V _refp and V _refn are the DAC feedback signals, and V _com is the input common mode signal , C _s0 and C _s1 are gain capacitors, C _s is a sampling capacitor, C _f is an integrating capacitor, φ ₁ and φ ₂ are two-phase non-overlapping clock signals, and OTA is a transconductance operational amplifier.

The specific control method is as follows:

When φ ₁ is high level, the sampling capacitor C _s samples the input signals _up and _un , and φ ₂ is low level at this time.

When φ ₁ is high level, φ ₂ is low level at this time. s ₁ and s ₀ are gain control signals. When both s ₁ and s ₀ are 0, the gain capacitors C _s0 and C _s1 do not sample the input signal at this time. In this case, when φ ₂ is high level, φ ₁ When the level is low, the integration capacitor C _f integrates the input signal stored in the sampling capacitor C _s through the OTA function, and integrates the feedback signals V _refp and V _refn at the same time. The sampling capacitor C _s works on both the input signals _up , _un and the feedback signals V _refp , V _refn . The corresponding coefficients are:

When s ₁ is 0, s ₀ is 1, and φ ₁ is high level, φ ₂ is low level at this time, and the gain capacitor C _s0 samples the input signal. In this case, when φ ₂ is high level and φ ₁ is low level, the integration capacitor C _f acts through OTA to integrate the input signal stored in the gain capacitor C _s0 . The gain capacitor C _s0 only works on the input signals _up and _un , and has no effect on the feedback signals V _refp and V _refn . That is, the coefficient b changes and the coefficient a does not change, respectively:

取C_s0＝C_s，此时b＝2a，实现了STF的2倍增益，而NTF不变。

Taking C _s0 =C _s , and b=2a at this time, the double gain of STF is realized, while the NTF remains unchanged.

When s ₁ and s ₀ are both 1, φ ₁ is high level, and φ ₂ is low level at this time, gain capacitors C _s0 and C _s1 sample the input signal. In this case, when φ ₂ is at high level and φ ₁ is at low level, the integrating capacitor C _f acts through OTA to integrate the input signal stored in gain capacitors C _s0 and C _s1 . The gain capacitors C _s0 and C _s1 only work on the input signals _up and _un , and have no effect on the feedback signals V _refp and V _refn . That is, the coefficient b changes and the coefficient a does not change, respectively:

取C_s0＝C_s，C_s1＝2C_s，此时b＝4a，实现了STF的4倍增益，而NTF不变。

Taking C _s0 =C _s , C _s1 =2C _s , and b=4a at this time, a 4-fold gain of the STF is realized, while the NTF remains unchanged.

Figure 3 shows two non-overlapping clock signals of _φ1 and _φ2 .

Claims (2)

1. A Sigma-Delta modulator with adjustable gain, which is characterized by comprising a first switch, a second switch, a third switch, a first adder, a second adder, a third adder, a first integrator, a second integrator, a quantizer, a feedback DAC, a first gain amplifier, a second gain amplifier, a third gain amplifier, a fourth gain amplifier, a fifth gain amplifier, a sixth gain amplifier and a seventh gain amplifier; the input end of the first gain amplifier is connected with an input signal through a first switch, the output end of the first gain amplifier is connected with one input end of the first adder, the other input end of the first adder is connected with the output end of the sixth gain amplifier, the output end of the first adder is connected with the input end of the first integrator, and the output end of the first integrator is connected with the input end of the fourth gain amplifier; the output end of the fourth gain amplifier is connected with the first input end of the second adder, the second input end of the second adder is connected with the output end of the second gain amplifier, the third input end of the second adder is connected with the output end of the seventh gain amplifier, and the output end of the second adder is connected with the input end of the second integrator; the input end of the second gain amplifier is connected with an input signal through a second switch, and the input ends of the sixth gain amplifier and the seventh gain amplifier are connected with the feedback output of the feedback DAC; the output of the second integrator is connected with the input end of a fifth gain amplifier, and the output of the fifth gain amplifier is connected with one input end of a third adder; the other input end of the third adder is connected with the output end of the third gain amplifier, and the input end of the third gain amplifier is connected with an input signal through a third switch; the output end of the third adder is connected with one input end of the quantizer, the quantization noise E (z) is input into the quantizer, the output of the quantizer is the output of the Sigma-Delta modulator, and the output of the quantizer is connected with the input end of the feedback DAC; the first gain amplifier, the second gain amplifier and the third gain amplifier have three different gain combinations under the control of the first switch, the second switch and the third switch, so that the signal transfer function is changed, and the noise transfer function is not changed.

2. The gain-adjustable Sigma-Delta modulator of claim 1, wherein the first switch, the first gain amplifier, the first adder and the first integrator are implemented by switched capacitor circuits, comprising: a first sub-switch, a second sub-switch, a third sub-switch, a fourth sub-switch, a fifth sub-switch, a sixth sub-switch, a seventh sub-switch, an eighth sub-switch, a ninth sub-switch, a tenth sub-switch, an eleventh sub-switch, a twelfth sub-switch, a thirteenth sub-switch, a fourteenth sub-switch, a fifteenth sub-switch, a sixteenth sub-switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, and a transconductance amplifier; defining the gain control signal as s ₁ Sum s ₀ The differential input signal is u _p And u _n The common mode signal is V _com The DAC feedback signal is V _refp And V _refn Two-phase non-overlapping clock signal phi ₁ And phi ₂ The method comprises the steps of carrying out a first treatment on the surface of the Wherein the control signal of the first sub-switch is phi ₂ One end of it is connected with V _com The other end is connected with one end of a first capacitor, and the first capacitor is a gain capacitor; the control signal of the second sub-switch is phi ₂ One end of it is connected with V _com The other end is connected with one end of a second capacitor, and the second capacitor is a gain capacitor; the control signal of the third sub-switch is phi ₁ ·s ₁ One end of it is connected to u _p The other end is connected with one end of the first capacitor; the control signal of the fourth sub-switch is phi ₁ ·s ₀ One end of it is connected to u _p The other end is connected with one end of the second capacitor; the control signal of the fifth sub-switch is phi ₁ One end of it is connected to u _p The other end is connected with one end of a third capacitor, and the third capacitor is a sampling capacitor; the control signal of the sixth sub-switch is phi ₂ One end of it is connected with V _refp The other end is connected with one end of the third capacitor; the control signal of the seventh sub-switch is phi ₂ One end of it is connected with V _refn The other end is connected with one end of a fourth capacitor, and the fourth capacitor is a sampling capacitor; eighth sub-switchControl signal of phi ₁ One end of it is connected to u _n The other end is connected with one end of the fourth capacitor; the control signal of the ninth sub-switch is phi ₁ ·s ₀ One end of it is connected to u _n The other end is connected with one end of a fifth capacitor, and the fifth capacitor is a gain capacitor; the control signal of the tenth sub-switch is phi ₁ ·s ₁ One end of it is connected to u _n The other end is connected with one end of a sixth capacitor, and the sixth capacitor is a gain capacitor; the control signal of the eleventh sub-switch is phi ₂ One end of it is connected with V _com The other end is connected with one end of the fifth capacitor; the twelfth sub-switch has a control signal phi ₂ One end of it is connected with V _com The other end is connected with one end of the sixth capacitor; one end of the thirteenth sub-switch is connected with the other end of the first capacitor, the other end of the second capacitor and the other end of the third capacitor, the other end of the thirteenth sub-switch is connected with the negative input end of the transconductance amplifier and one end of the seventh capacitor, and the other end of the seventh capacitor is connected with the positive output end of the transconductance amplifier; one end of the fourteenth sub-switch is connected with one end of the thirteenth sub-switch, and the other end of the fourteenth sub-switch is connected with V _com And one end of the fifteenth sub-switch, the other end of the fifteenth sub-switch is connected with the other end of the fourth capacitor, the other end of the fifth capacitor, the other end of the sixth capacitor and one end of the sixteenth sub-switch; the other end of the sixteenth sub-switch is connected with the positive input end of the transconductance amplifier and one end of the eighth capacitor, and the other end of the eighth capacitor is connected with the negative output end of the transconductance amplifier; the seventh capacitor and the eighth capacitor are integrating capacitors;

the second switch, the second gain amplifier, the second adder and the second integrator are realized by a switch capacitor circuit, and the structure of the second switch, the second gain amplifier, the second adder and the second integrator is the same as that of the switch capacitor circuit of the first switch, the first gain amplifier, the first adder and the first integrator; the third switch, the third gain amplifier and the third adder are realized by a switched capacitor circuit, and the structure of the third switch, the third gain amplifier and the third adder is the same as that of the switched capacitor circuit of the first switch, the first gain amplifier, the first adder and the first integrator.

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