CN114038814A - Packaging structure and forming method thereof - Google Patents
Packaging structure and forming method thereof Download PDFInfo
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- CN114038814A CN114038814A CN202111370112.2A CN202111370112A CN114038814A CN 114038814 A CN114038814 A CN 114038814A CN 202111370112 A CN202111370112 A CN 202111370112A CN 114038814 A CN114038814 A CN 114038814A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A package structure and a method of forming the same, the structure comprising: a substrate; a wafer fixed on a substrate, wherein the wafer comprises a functional surface and a non-functional surface which are opposite, the non-functional surface of the wafer is fixed on the surface of the substrate, and the area of the wafer is smaller than that of the substrate; a first passivation layer on the substrate, the first passivation layer also on the top surface and sidewall surfaces of the wafer; a rewiring layer on the first passivation layer and on the wafer, the rewiring layer being electrically connected to the wafer; a solder layer on the rewiring layer, the solder layer being electrically connected to the rewiring layer on the wafer. The warpage of the package structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a package structure and a method for forming the same.
Background
In a semiconductor manufacturing process, packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip, which is the last ring of manufacturing the chip.
The packaging process comprises the following steps: the wafer from the previous wafer process is cut into small chips (Die) through a scribing process, then the cut chips are fixed on a lead frame, and the bonding pads of the chips are externally connected by utilizing superfine metal (gold tin copper aluminum) wires or conductive resin; the individual chips are then encapsulated and protected by a plastic housing.
However, the yield of the chip is affected by the conventional packaging method, and the packaging process needs to be improved to improve the yield.
Disclosure of Invention
The invention provides a packaging structure and a forming method thereof, which improve the packaging process to improve the yield.
In order to solve the above technical problem, a technical solution of the present invention provides a package structure, including: a substrate; a wafer fixed on a substrate, wherein the wafer comprises a functional surface and a non-functional surface which are opposite, the non-functional surface of the wafer is fixed on the surface of the substrate, and the area of the wafer is smaller than that of the substrate; a first passivation layer on the substrate, the first passivation layer also on the top surface and sidewall surfaces of the wafer; a rewiring layer on the first passivation layer and on the wafer, the rewiring layer being electrically connected to the wafer; a solder layer on the rewiring layer, the solder layer being electrically connected to the rewiring layer on the wafer.
Optionally, the vickers hardness of the substrate is greater than or equal to 70 Gpa; the substrate comprises a semiconductor material or an inorganic material, the semiconductor material comprises a silicon plate, and the inorganic material comprises tempered glass.
Optionally, the material of the first passivation layer includes an organic material, and the organic material includes polyimide or poly-p-phenylene benzobisoxazole.
Optionally, the method further includes: the bonding layer is positioned between the substrate and the wafer, and the substrate and the wafer are fixed through the bonding layer; the thickness of the first passivation layer is greater than or equal to the sum of the thicknesses of the wafer and the bonding layer.
Optionally, the method further includes: the rewiring layer is positioned in the second passivation layer, and the welding layer is positioned on the second passivation layer; the material of the second passivation layer is the same as the material of the first passivation layer.
Correspondingly, the technical scheme of the invention also provides a forming method of the packaging structure, which comprises the following steps: providing a substrate; providing a wafer comprising opposing functional and non-functional sides, the wafer having an area smaller than the area of the substrate; fixing the wafer on a substrate, wherein the non-functional surface of the wafer is fixed on the surface of the substrate; forming a first passivation layer on the substrate, the first passivation layer also being located on the top surface and the sidewall surface of the wafer; forming a rewiring layer on the first passivation layer and on the wafer, the rewiring layer being electrically connected to the wafer; a solder layer is formed on the rewiring layer, the solder layer being electrically connected to the rewiring layer on the wafer.
Optionally, the method for forming the first passivation layer on the substrate includes: forming a passivation material layer on the substrate, wherein the process for forming the passivation material layer comprises a spin coating process or a spray coating process; and carrying out curing treatment on the passivation material layer to form the first passivation layer.
Optionally, the material of the first passivation layer includes an organic material, and the organic material includes polyimide or poly-p-phenylene benzobisoxazole; the process for curing the passivation material layer comprises the following steps: carrying out thermocuring treatment; when the passivation material layer is polyimide, the temperature range of the thermosetting treatment is 360-380 ℃; when the passivation material layer is poly-p-phenylene benzobisoxazole, the temperature range of the thermocuring treatment is 325-335 ℃.
Optionally, the vickers hardness of the substrate is greater than or equal to 70 Gpa; the substrate comprises a semiconductor material or an inorganic material, the semiconductor material comprises a silicon plate, and the inorganic material comprises tempered glass.
Optionally, the method for fixing the wafer on the substrate includes: forming an adhesive layer on a substrate; and arranging the wafer on the bonding layer.
Optionally, the method for forming a redistribution layer on the first passivation layer includes: forming a patterning layer on the wafer and the first passivation layer, wherein the patterning layer is internally provided with a plurality of first grooves and second grooves, the first grooves expose part of the top surface of the wafer, and the second grooves expose part of the top surface of the first passivation layer; forming a rewiring material layer in the first groove, the second groove and the patterning layer; flattening the rewiring material layer until the top surface of the patterning layer is exposed to form the rewiring layer; and removing the patterning layer after the rewiring layer is formed.
Optionally, after forming the redistribution layer, the method further includes: forming a second passivation layer on the first passivation layer, the wafer and the rewiring layer, wherein the rewiring layer is located in the second passivation layer, and the second passivation layer exposes the top surface of the rewiring layer on the wafer; the welding layer is positioned on the second passivation layer; the material of the second passivation layer is the same as the material of the first passivation layer.
Optionally, the method for forming the second passivation layer includes: forming a passivation material layer on the first passivation layer, on the wafer and on the rewiring layer; curing the passivation material layer to form an initial second passivation layer; and removing part of the initial second passivation layer until the top surface of the rewiring layer on the wafer is exposed, and forming the second passivation layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the wafer is fixed on the substrate, the first passivation layer is formed on the substrate, the rewiring layer is formed on the first passivation layer, the Vickers hardness of the substrate is greater than or equal to 70Gpa, and the substrate is high in hardness, so that the substrate is not prone to deformation in the subsequent process of forming the first passivation layer, the situation that packaged chips are warped and deformed is reduced, and the yield of the packaged chips is improved.
Further, the material of the substrate comprises a semiconductor material or an inorganic material, the semiconductor material comprises a silicon plate, and the inorganic material comprises tempered glass. The silicon plate and the toughened glass have high hardness and are not easy to deform.
Further, the material of the first passivation layer includes an organic material including polyimide or poly-p-phenylene benzobisoxazole. The deformation amount of the polyimide or poly-p-phenylene benzobisoxazole material in the forming process is small, and the packaged chip is not easy to warp and deform due to large stress on the substrate and the wafer.
Furthermore, rewiring layers are formed on the first passivation layer and the wafer, and the rewiring layers are located on the first passivation layer and the wafer, so that the distributable areas of the rewiring layers on the first passivation layer and the wafer are increased, the distance between the first grooves in the wafer is increased, a process window for manufacturing the rewiring layers on the wafer is increased, and when a welding layer electrically connected with the rewiring layers on the wafer is formed, the process window is also increased, and the production efficiency is improved.
Drawings
Fig. 1-3 are schematic diagrams illustrating a process of forming a package structure according to an embodiment;
fig. 4 to 9 are schematic views illustrating a process of forming a package structure according to an embodiment of the invention.
Detailed Description
As described in the background, there is a need to improve the packaging process to improve yield. The analysis will now be described with reference to specific examples.
Fig. 1 to 3 are schematic views illustrating a process of forming a package structure according to an embodiment.
Referring to fig. 1, a carrier 100 is provided; forming an adhesive layer 101 on the carrier 100; providing a wafer 102, the wafer 102 comprising a functional side and a non-functional side; the functional side of the wafer 102 is fixed to the adhesive layer 101.
Referring to fig. 2, a molding layer 103 is formed on the carrier 100, and the molding layer 103 covers the sidewall surface and the non-functional surface of the wafer 102.
Referring to fig. 3, the carrier 100 and the adhesive layer 101 are removed to expose the functional surface of the wafer 102; forming a rewiring layer 104 on the functional surface of the wafer 102, forming an insulating layer 105 on the functional surface of the wafer 102 and the plastic package layer 103, wherein the rewiring layer 104 is electrically connected with the wafer 102, and the rewiring layer 104 is positioned in the insulating layer 105; solder balls 106 are formed on the insulating layer 105, and the solder balls 106 are electrically connected to the redistribution layer 104.
In the forming process of the packaging structure, when the plastic package layer 103 is formed, the carrier plate 100 is preheated, molten plastic materials are injected on the wafer 102 and the carrier plate 100, the molten plastic materials react and solidify under the action of heat treatment, and the plastic package layer 103 is cooled after being formed.
Since the material of the carrier plate 100 and the material of the plastic sealing layer 103 are both plastics, in the process from melting to solidification and cooling, the plastic material has a large deformation amount when the plastic sealing layer 103 is formed after solidification and cooling, and the stress of the plastic sealing layer 103 and the wafer 102 and the stress of the plastic sealing layer 103 and the carrier plate 100 are not matched, so that the wafer 102 is easily warped, and the yield is easy to occur.
In order to solve the above problems, the technical scheme of the present invention provides a package structure and a method for forming the package structure, in which a wafer is fixed on a substrate, a first passivation layer is formed on the substrate, and a redistribution layer is formed on the first passivation layer, the vickers hardness of the substrate is greater than or equal to 70Gpa, and the substrate has a high hardness, so that the substrate is not easily deformed in the subsequent process of forming the first passivation layer, thereby reducing the warpage of the packaged chip and improving the yield of the packaged chip.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 9 are schematic views illustrating a process of forming a package structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, wherein the vickers hardness of the substrate 200 is greater than or equal to 70 Gpa.
The material of the substrate 200 includes a semiconductor material or an inorganic material.
In this embodiment, the semiconductor material comprises a silicon plate and the inorganic material comprises tempered glass.
The vickers hardness of the substrate 200 is greater than or equal to 70Gpa, and the hardness of the silicon plate and the tempered glass is relatively high, so that deformation is not easily generated.
With continued reference to fig. 4, a wafer 202 is provided, the wafer 202 including opposing functional and non-functional sides, the wafer 202 having an area smaller than the area of the substrate 200.
The functional side of the wafer 202 has a number of semiconductor devices.
With continued reference to fig. 4, the non-functional side of the wafer 202 is mounted on a substrate 200.
The method of securing the wafer 202 to the substrate 200 includes: forming an adhesive layer 201 on the substrate 200; the wafer 202 is disposed on the adhesive layer 201.
The adhesive layer 201 is made of a material having a certain viscosity, and can bond and fix the nonfunctional surface of the wafer 202 to the substrate 200.
In this embodiment, the adhesive layer 201 is a DAF film, and the DAF film is a resin adhesive with high thermal conductivity.
Referring to fig. 5, a first passivation layer 203 is formed on the substrate 200, wherein the first passivation layer 203 is also located on the top surface and the sidewall surface of the wafer 202.
The method of forming the first passivation layer 203 on the substrate 200 includes: forming a passivation material layer (not shown) on the substrate 200; and curing the passivation material layer to form the first passivation layer 203.
The material of the first passivation layer 203 includes an organic material, and the organic material includes Polyimide (PI) or Poly-p-Phenylene Benzobisoxazole (PBO).
The shrinkage rate and the linear expansion coefficient of the polyimide or poly-p-phenylene benzobisoxazole material are small, so that the deformation amount is small in the process of curing to form the first passivation layer 203, and the packaged chip is not prone to warping and deformation due to large stress on the substrate 200 and the wafer 202.
The process for curing the passivation material layer comprises the following steps: carrying out thermocuring treatment; when the passivation material layer is polyimide, the temperature range of the thermosetting treatment is 360-380 ℃; when the passivation material layer is poly-p-phenylene benzobisoxazole, the temperature range of the thermocuring treatment is 325-335 ℃.
The thermal curing process of the temperature range causes a smaller amount of deformation when the passivation material layer is cured.
The process of forming the passivation material layer includes a spin coating process or a spray coating process.
In this embodiment, the thickness of the first passivation layer 203 is greater than or equal to the sum of the thicknesses of the wafer 202 and the bonding layer 201.
In this embodiment, the thickness of the first passivation layer 203 is equal to the sum of the thicknesses of the wafer 202 and the bonding layer 201.
Next, a rewiring layer electrically connected to the wafer 202 is formed on the first passivation layer 203 and on the wafer 202. The process of forming the rewiring layer is described with reference to fig. 6 and 7.
Referring to fig. 6, a patterned layer 204 is formed on the wafer 202 and on the first passivation layer 203, the patterned layer 204 having a plurality of first recesses 205 and second recesses 206 therein, the first recesses 205 exposing portions of the top surface of the wafer 202, and the second recesses 206 exposing portions of the top surface of the first passivation layer 203.
The first recess 205 is used for subsequently forming a solder layer in a portion of the first recess 205 for electrical connection to the wafer 202.
The material of the patterned layer 204 includes photoresist, and the process of forming the patterned layer 204 includes photolithography and development processes.
Referring to fig. 7, a rewiring material layer (not shown) is formed in the first recess 205, the second recess 206 and on the patterned layer 204; planarizing the rewiring material layer until the top surface of the patterning layer 204 is exposed to form the rewiring layer 207; after the re-wiring layer 207 is formed, the patterning layer 204 is removed.
The material of the redistribution layer 207 includes a metal, and in this embodiment, the metal includes copper.
A rewiring layer 207 is formed on the first passivation layer 203 and on the wafer 202, the rewiring layer 207 is located on the first passivation layer 203 and on the wafer 202, so that the distributable area of the rewiring layer 207 on the first passivation layer 203 and on the wafer 202 is increased, the distance between the first grooves 205 located on the wafer 202 is increased, the process window for manufacturing the rewiring layer 207 on the wafer 202 is increased, and when a solder layer electrically connected with the rewiring layer 207 on the wafer 202 is formed, the process window is also increased, and the production efficiency is improved.
Referring to fig. 8, a second passivation layer 208 is formed on the first passivation layer 203, on the wafer 202, and on the redistribution layer 207, the redistribution layer 207 is located in the second passivation layer 208, and the second passivation layer 208 exposes the top surface of the redistribution layer 207 on the wafer 202.
The second passivation layer 208 insulates the rewiring layer 207.
In this embodiment, the material of the second passivation layer 208 is the same as the material of the first passivation layer 203.
The method for forming the second passivation layer 208 includes: forming a passivation material layer (not shown) on the first passivation layer 203, on the wafer 202, and on the rewiring layer 207; curing the passivation material layer to form an initial second passivation layer (not shown); portions of the initial second passivation layer are removed until portions of the top surface of the redistribution layer 207 on the wafer 202 are exposed, forming the second passivation layer 208.
Referring to fig. 9, a solder layer 209 is formed on the second passivation layer 208, and the solder layer 209 is electrically connected to the exposed redistribution layer 207 on the wafer 202.
The soldering layer 209 is made of soldering tin, tin-lead alloy soldering tin, antimony-added soldering tin, cadmium-added soldering tin, silver-added soldering tin or copper-added soldering tin.
Therefore, in the formed packaging structure, the hardness of the substrate is high, and the deformation amount of the materials of the first passivation layer and the second passivation layer is small, so that the warping deformation of the packaged chip is reduced, and the yield of the packaged chip is improved.
In this embodiment, after forming the solder layer 209, the method further includes: and grinding and thinning the back surface of the substrate 200 to reduce the volume of the packaging structure.
In other embodiments, the back side of the substrate can be thinned.
In this embodiment, after forming the solder layer 209, the method further includes: and cutting the packaging structure along the back surface of the substrate 200 to form a plurality of discrete packaged chips.
Accordingly, an embodiment of the present invention further provides a package structure, including:
a substrate 200;
a wafer 202 mounted on a substrate 200, the wafer 202 comprising opposing functional and non-functional sides, the non-functional side of the wafer 202 being mounted on a surface of the substrate 200, the wafer 202 having an area smaller than the area of the substrate 200;
a first passivation layer 203 on the substrate, the first passivation layer 203 also being located on the top surface and sidewall surfaces of the wafer 202;
a re-wiring layer 207 on the first passivation layer 203 and on the wafer 202, the re-wiring layer 207 being electrically connected to the wafer 202;
a solder layer 209 on the redistribution layer 207, the solder layer 209 being electrically connected to the redistribution layer 207 on the wafer 202.
In the present embodiment, the vickers hardness of the substrate 200 is greater than or equal to 70 Gpa.
In the present embodiment, the material of the substrate 200 includes a semiconductor material including a silicon plate or an inorganic material including tempered glass.
In this embodiment, the material of the first passivation layer 203 includes an organic material, and the organic material includes polyimide or poly-p-phenylene benzobisoxazole.
In this embodiment, the method further includes: an adhesive layer 201 is disposed between the substrate 200 and the wafer 202, and the substrate 200 and the wafer 202 are fixed by the adhesive layer 201.
In this embodiment, the thickness of the first passivation layer 203 is greater than or equal to the sum of the thicknesses of the wafer 202 and the bonding layer 201.
In this embodiment, the method further includes: a second passivation layer 208 on the first passivation layer 203, the rewiring layer 207 being located in the second passivation layer 208, and the solder layer 209 being located on the second passivation layer 208.
In this embodiment, the material of the second passivation layer 208 is the same as the material of the first passivation layer 203.
In this embodiment, the material of the solder layer 209 includes solder, tin-lead alloy solder, antimony-added solder, cadmium-added solder, silver-added solder or copper-added solder.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A package structure, comprising:
a substrate;
a wafer fixed on a substrate, wherein the wafer comprises a functional surface and a non-functional surface which are opposite, the non-functional surface of the wafer is fixed on the surface of the substrate, and the area of the wafer is smaller than that of the substrate;
a first passivation layer on the substrate, the first passivation layer also on the top surface and sidewall surfaces of the wafer;
a rewiring layer on the first passivation layer and on the wafer, the rewiring layer being electrically connected to the wafer; a solder layer on the rewiring layer, the solder layer being electrically connected to the rewiring layer on the wafer.
2. The package structure of claim 1, wherein the substrate has a vickers hardness of greater than or equal to 70 Gpa; the substrate comprises a semiconductor material or an inorganic material, the semiconductor material comprises a silicon plate, and the inorganic material comprises tempered glass.
3. The encapsulation structure of claim 1, wherein a material of the first passivation layer comprises an organic material comprising polyimide or poly-p-phenylene benzobisoxazole.
4. The package structure of claim 1, further comprising: the bonding layer is positioned between the substrate and the wafer, and the substrate and the wafer are fixed through the bonding layer; the thickness of the first passivation layer is greater than or equal to the sum of the thicknesses of the wafer and the bonding layer.
5. The package structure of claim 1, further comprising: the rewiring layer is positioned in the second passivation layer, and the welding layer is positioned on the second passivation layer; the material of the second passivation layer is the same as the material of the first passivation layer.
6. A method for forming a package structure, comprising:
providing a substrate;
providing a wafer comprising opposing functional and non-functional sides, the wafer having an area smaller than the area of the substrate;
fixing the wafer on a substrate, wherein the non-functional surface of the wafer is fixed on the surface of the substrate;
forming a first passivation layer on the substrate, the first passivation layer also being located on the top surface and the sidewall surface of the wafer;
forming a rewiring layer on the first passivation layer and on the wafer, the rewiring layer being electrically connected to the wafer; a solder layer is formed on the rewiring layer, the solder layer being electrically connected to the rewiring layer on the wafer.
7. The method of forming the package structure of claim 6, wherein the method of forming the first passivation layer on the substrate comprises: forming a passivation material layer on the substrate, wherein the process for forming the passivation material layer comprises a spin coating process or a spray coating process; and carrying out curing treatment on the passivation material layer to form the first passivation layer.
8. The method for forming the encapsulation structure according to claim 6, wherein a material of the first passivation layer comprises an organic material, and the organic material comprises polyimide or poly-p-phenylene benzobisoxazole; the process for curing the passivation material layer comprises the following steps: carrying out thermocuring treatment; when the passivation material layer is polyimide, the temperature range of the thermosetting treatment is 360-380 ℃; when the passivation material layer is poly-p-phenylene benzobisoxazole, the temperature range of the thermocuring treatment is 325-335 ℃.
9. The method of claim 6, wherein the substrate has a Vickers hardness of greater than or equal to 70 GPa; the substrate comprises a semiconductor material or an inorganic material, the semiconductor material comprises a silicon plate, and the inorganic material comprises tempered glass.
10. The method of claim 6, wherein the step of securing the die to the substrate comprises: forming an adhesive layer on a substrate; and arranging the wafer on the bonding layer.
11. The method of forming the package structure of claim 6, wherein the method of forming the re-wiring layer on the first passivation layer comprises: forming a patterning layer on the wafer and the first passivation layer, wherein the patterning layer is internally provided with a plurality of first grooves and second grooves, the first grooves expose part of the top surface of the wafer, and the second grooves expose part of the top surface of the first passivation layer; forming a rewiring material layer in the first groove, the second groove and the patterning layer; flattening the rewiring material layer until the top surface of the patterning layer is exposed to form the rewiring layer; and removing the patterning layer after the rewiring layer is formed.
12. The method of forming a package structure of claim 11, wherein after forming the redistribution layer, further comprising: forming a second passivation layer on the first passivation layer, the wafer and the rewiring layer, wherein the rewiring layer is located in the second passivation layer, and the second passivation layer exposes the top surface of the rewiring layer on the wafer; the welding layer is positioned on the second passivation layer; the material of the second passivation layer is the same as the material of the first passivation layer.
13. The method for forming the package structure according to claim 12, wherein the method for forming the second passivation layer comprises: forming a passivation material layer on the first passivation layer, on the wafer and on the rewiring layer; curing the passivation material layer to form an initial second passivation layer; and removing part of the initial second passivation layer until the top surface of the rewiring layer on the wafer is exposed, and forming the second passivation layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115425003A (en) * | 2022-09-21 | 2022-12-02 | 苏州通富超威半导体有限公司 | Package structure and forming method thereof |
| CN115425002A (en) * | 2022-09-21 | 2022-12-02 | 苏州通富超威半导体有限公司 | Encapsulation structure and method for forming the encapsulation structure |
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