CN114023740A - Semiconductor structure with high voltage resistance device and manufacturing method thereof - Google Patents
Semiconductor structure with high voltage resistance device and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 58
- 238000005468 ion implantation Methods 0.000 claims description 29
- 150000002500 ions Chemical class 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000012876 topography Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 42
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 description 43
- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- 230000001590 oxidative effect Effects 0.000 description 13
- 230000005669 field effect Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
- H10D84/409—Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/112—Field plates comprising multiple field plate segments
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/115—Resistive field plates, e.g. semi-insulating field plates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, and more particularly, to a semiconductor structure with a high voltage resistor and a method for manufacturing the same. The structure includes: the substrate layer comprises a drain region, a source region and a drift region positioned between the drain region and the source region; a first conductive type high-resistance region, which is located in the substrate layer and extends through at least the drain region, the source region and the drift region; the upper surface of the first conductive type high-resistance region at the position of the drift region is oxidized to form a field oxide layer; the field oxide layer comprises a plurality of convex areas surrounding a plurality of circles at intervals and a plurality of concave areas surrounding a plurality of circles at intervals, and a circle of concave area is arranged between every two adjacent circles of convex areas; the polycrystalline silicon resistor layer spirally surrounds a plurality of circles at intervals on the field oxide layer, and each circle of polycrystalline silicon resistor layer is bridged on the field oxide layer between the convex area and the concave area. The manufacturing method is used for manufacturing the structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, and more particularly, to a semiconductor structure with a high voltage resistor and a method for manufacturing the same.
Background
The BCD (Bipolar-CMOS-DMOS) process integrates different devices such as a Bipolar (Bipolar) device having an analog function, a CMOS device for digital design, and a DMOS device of high voltage high power structure on the same chip. The Bipolar (Bipolar) device with an analog function is used as an interface between an external circuit and a semiconductor internal circuit, the CMOS device is used as a core of signal processing, and the DMOS device is used for driving an external circuit load. By integrating different functional circuits within the same chip, the number of interconnections within a semiconductor integrated circuit system is reduced.
In the manufacturing process of the BCD in the ultra-high voltage and high resistance state, in order to realize the high withstand voltage performance of the polysilicon resistor, the polysilicon resistor is usually wound on the drift region of the high voltage field effect transistor in a spiral type, and the high withstand voltage is provided to the polysilicon resistor through the high voltage field effect transistor. Therefore, the voltage resistance of the polysilicon resistor is required to depend on the voltage resistance of the high-voltage field effect transistor. Therefore, the related art generally increases the voltage endurance of the device by elongating the high voltage drift region of the high voltage fet, and thus increases the voltage endurance of the polysilicon resistor.
However, since the source region of the high voltage fet is connected to the source region metal and the first polysilicon field plate, the drain region is connected to the drain region metal and the second polysilicon field plate. And the drift region between the first polysilicon field plate and the second polysilicon field plate is not provided with a field plate to adjust the electric field, if the withstand voltage improved by only extending the drift region is limited, the withstand voltage can not be increased after a specific length is reached, and the effect of other field plates is also poor.
Disclosure of Invention
The application provides a semiconductor structure with a high-voltage resistor device and a manufacturing method thereof, which can solve the problem of limitation caused by the fact that the withstand voltage performance of a polysilicon resistor is improved by means of lengthening a drift region in the related art.
To solve the technical problems described in the background, a first aspect of the present application provides a semiconductor structure with a high-voltage resistance device, including:
a substrate layer including a drain region, a source region, and a drift region between the drain region and the source region;
a first-conductivity-type high-resistance region in the base layer, extending through at least the drain region, the source region, and the drift region; the upper surface of the first conduction type high-resistance region at the drift region position is oxidized to form a field oxide layer; the field oxide layer comprises a plurality of raised areas surrounding a plurality of circles at intervals and a plurality of recessed areas surrounding a plurality of circles at intervals, and a circle of recessed area is arranged between every two adjacent circles of raised areas;
the polycrystalline silicon resistor layer spirally surrounds a plurality of circles at intervals on the field oxide layer, and each circle of the polycrystalline silicon resistor layer is bridged on the field oxide layer between the convex area and the concave area.
Optionally, the polysilicon resistor layer comprises a first end and a second end, and the polysilicon resistor layer is spirally wound from the first end to the second end through a plurality of turns.
Optionally, the field plate structure comprises a gate polysilicon structure and a drain region field plate structure;
the grid polycrystalline silicon structure is positioned on one side of the polycrystalline silicon resistor layer close to the source region and is in bridge connection with the drift region and the source region;
the drain region field plate structure is positioned on one side of the polycrystalline silicon resistance layer close to the drain region.
In order to solve the technical problems described in the background art, a second aspect of the present application also provides a method of manufacturing a semiconductor with a high-voltage resistance device, including:
providing a semiconductor substrate layer;
forming a first blocking layer with a first blocking pattern on the drift region of the substrate layer, wherein the first blocking layer surrounds the first blocking pattern at intervals;
performing first conductive type ion implantation on the substrate layer with the first barrier layer, so that a first conductive type implantation area is formed in the substrate layer which is not covered with the first barrier layer, and an unimplanted area is formed in the substrate layer which is covered with the first barrier layer;
removing the first barrier layer so that the upper surface of the substrate layer is exposed;
performing high-temperature oxidation drive-in to oxidize the upper surface of the substrate layer to form an oxide layer, so that the first conductive type injection region is fused into a first conductive type high-resistance region; the thickness of the oxide layer formed by oxidizing the first conductive type injection region is larger than that of the oxide layer formed by oxidizing the non-injection region;
removing the oxide layer to expose the oxidized upper surface of the substrate layer, wherein the drift region comprises convex regions and concave regions which are alternately distributed;
according to the surface appearance of the substrate layer at the drift region position, oxidizing the upper surface of the substrate layer at the drift region position to form a field oxide layer with alternately distributed convex regions and concave regions;
and manufacturing a spiral polysilicon resistor layer which is wound at intervals on the field oxide layer, so that the polysilicon resistor layer is bridged on the field oxide layer between the convex area and the concave area.
Optionally, the step of performing a first conductivity type ion implantation on the base layer with the first barrier layer so as to form a first conductivity type implantation region in the base layer uncovered by the first barrier layer includes:
firstly, carrying out first-time ion implantation on the substrate layer with the first barrier layer by using first conductive type impurity ions;
performing second ion implantation on the substrate layer with the first barrier layer by using first conductive type impurity ions;
so that a first conductive type injection region is formed in the base layer which is not covered with the first barrier layer.
Optionally, the step of performing a first ion implantation with first conductivity type impurity ions on the substrate layer with the first barrier layer includes:
using impurity ions of the first conductivity type to conduct 30 keV-100 keV energy, 1e 13-5 e14 ions/cm2A first ion implantation of a dose.
Optionally, the step of performing a second ion implantation with impurity ions of the first conductivity type on the base layer with the first barrier layer includes:
using impurity ions of the first conductivity type to conduct 110 keV-1000 keV energy, 5e 11-1 e13 ions/cm2A second ion implantation of dose.
Optionally, performing high-temperature oxidation drive-in to oxidize the upper surface of the substrate layer to form an oxide layer, so that the first conductive type injection region is fused into a first conductive type high-resistance region; the step of oxidizing the first conductive type injection region to form the oxide layer, wherein the thickness of the oxide layer is larger than that of the oxide layer formed by oxidizing the non-injection region, and the step comprises the following steps:
performing high-temperature oxidation drive-in for a duration of 100min to 120min at a temperature range of 1000 ℃ to 1500 ℃, so that the upper surface of the substrate layer is oxidized to form an oxide layer, and the first conductive type injection region is fused into a first conductive type high-resistance region; the thickness of the oxide layer formed by oxidizing the first conductive type injection region is larger than that of the oxide layer formed by oxidizing the non-injection region.
Optionally, a first blocking layer with a first blocking pattern is formed on the drift region of the substrate layer, the first blocking layer surrounds a plurality of circles at intervals in the step of forming the first blocking pattern, and the interval between the first blocking layers is 2um to 10 um.
Optionally, the step of forming a first blocking layer with a first blocking pattern on the drift region of the base layer, the first blocking layer being formed to surround the first blocking pattern at intervals includes:
forming a first blocking layer with a first blocking pattern on the drift region of the base layer, wherein the first blocking layer spirally surrounds or concentrically surrounds the first blocking pattern at intervals.
The technical scheme at least comprises the following advantages: the polycrystalline silicon resistance layer is positioned on the drift region and is in bridge connection with the convex region and the concave region of the field oxide layer, so that the polycrystalline silicon resistance layer can play a role of a resistor on one hand, and can also be used as a field plate of the drift region on the other hand to adjust an electric field of the drift region and increase the voltage resistance of the field effect tube.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor device with a high voltage resistor according to an embodiment of the present application;
fig. 1a shows a schematic cross-sectional structural view of the semiconductor base layer provided in step S1;
FIG. 1b illustrates a schematic top view of one embodiment of a device formed after completion of step S2;
FIG. 1c is a schematic diagram illustrating a top view of another embodiment of a device formed after completion of step S2;
FIG. 1d shows a schematic cross-sectional view A-A of FIG. 1 b;
FIG. 1e is a schematic cross-sectional view of the device after step S3 is performed on FIG. 1 d;
FIG. 1f is a schematic cross-sectional view of the device after completion of step S4;
FIG. 1g shows a schematic cross-sectional structure of the device after the oxide layer shown in FIG. 1f is removed;
FIG. 1h shows a schematic cross-sectional structure of the device after completion of step S6;
FIG. 1i is a schematic cross-sectional view of the device after step S7 is completed;
fig. 1j shows a schematic cross-sectional structure of a device for forming a metal interconnection layer.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device with a high voltage resistor according to an embodiment of the present application, and it can be seen from fig. 1 that the method for manufacturing a semiconductor device with a high voltage resistor includes the following steps performed in sequence:
step S1: a semiconductor base layer is provided.
Referring to fig. 1a, which shows a schematic cross-sectional structural view of the semiconductor base layer provided in step S1, as can be seen from fig. 1a, the base layer 101 includes opposite upper and lower surfaces, the base layer 101 further includes a drain region 120 for forming a drain structure of the device, a source region 110 for forming a source structure of the device, and a drift region 130 located between the drain region 120 and the source region 110. Alternatively, the base layer 101 may be a silicon substrate.
Step S2: forming a first blocking layer with a first blocking pattern on the drift region of the substrate layer, wherein the first blocking layer surrounds the first blocking pattern at intervals, the first blocking pattern comprises blocking parts and exposed parts, and the blocking parts and the exposed parts are distributed alternately.
The first blocking layer may be formed by spirally and circumferentially spaced first blocking patterns, or formed by concentrically and circumferentially spaced first blocking patterns.
Referring to fig. 1b, which shows a schematic top view of an embodiment of the device formed after step S2 is completed, it can be seen from fig. 1b that the first blocking layer 210 is formed on the upper surface of the substrate layer 101, and the first blocking layer 210 is located on the upper surface of the substrate layer 101 at the position of the drift region 130. The first barrier layer 210 is spirally spaced and circularly formed from one end to the other end to form the first barrier pattern.
Referring to fig. 1c, which shows a schematic top view structure of another embodiment of the device formed after step S2 is completed, it can be seen from fig. 1c that a first blocking layer 210 is formed on the upper surface of the substrate layer 101, and the first blocking layer 210 is located on the upper surface of the substrate layer 101 at the position of the drift region 130. The first barrier layer 210 includes a plurality of concentric circles spaced around the first barrier pattern.
As shown in fig. 1b and 1c, the drain region 120 may be located in the middle of the device, the source region 110 is located outside the device, and the source region 110 is in a closed ring shape and surrounds the drain region 120.
Referring to fig. 1d, which shows a schematic sectional structure view along a-a in fig. 1b or 1c, as can be seen from fig. 1d, the first barrier layer 210 forms a first barrier pattern including barrier portions 211 and exposed portions 212, and the barrier portions 211 alternate with the exposed portions 212. The blocking portion 211 is a portion covered with the first blocking layer 210 surrounded by the space and capable of blocking the subsequent ion implantation, and the exposed portion 212 is a portion surrounded by the space of the first blocking layer 210, and the upper surface of the substrate layer 101 at the position of the exposed portion 212 is exposed.
If the first barrier layer 210 is spirally spaced and surrounded as shown in fig. 1b, the barrier portions 211 of the first barrier pattern are also spirally spaced and surrounded, and the exposed portions 212 of the first barrier pattern are spaced portions spirally spaced and surrounded.
If the first barrier layer 210 is surrounded by concentric circles as shown in fig. 1c, the barrier portions 211 of the first barrier pattern are also surrounded by the same concentric circles, and the exposed portions 212 of the first barrier pattern are the spaced portions surrounded by the concentric circles.
Alternatively, the first barrier layer 210 may be a photoresist, and the first barrier layer 210 has a first barrier pattern by a photolithography process.
Step S3: and performing first conductive type ion implantation on the base layer with the first barrier layer, so that a first conductive type implantation area is formed in the base layer which is not covered with the first barrier layer, and an unimplanted area is formed in the base layer which is covered with the first barrier layer.
In this embodiment, the N-type is the first conductivity type, and the performing the first conductivity type ion implantation is performing the N-type ion implantation. Referring to fig. 1e, which shows a schematic cross-sectional structural view of the device after step S3 is performed on fig. 1d, it can be seen from fig. 1e that after N-type ion implantation is performed on the structure shown in fig. 1c, an N-type implantation region 102 is formed in the base layer 101 not covered with the first barrier layer 210, that is, an N-type implantation region 102 is formed in the base layer 101 corresponding to the exposed portion 212 of the first barrier pattern, and the N-type implantation region 102 extends downward from the upper surface of the base layer 101. Due to the blocking effect of the first blocking layer 210 at the position of the blocking portion 211 of the first blocking pattern, the corresponding substrate layer 101 at the position is not implanted with N-type ions to form an unimplanted region.
Since the first blocking layer 210 surrounds and forms the first blocking pattern at intervals, and the blocking portions 211 and the exposed portions 212 are alternately distributed on the drift region 130 of the substrate layer 101, for the N-type implanted regions 102 and the non-implanted regions in the substrate layer 101 at the position of the drift region 130, the N-type implanted regions 102 and the non-implanted regions are alternately distributed at intervals, that is, one circle of non-implanted region is located between two adjacent circles of N-type implanted regions 102.
In the process of step S3, a first ion implantation with low energy and high dose may be performed on the substrate layer 101 with the first barrier layer 210 by using N-type impurity ions; carrying out second ion implantation with high energy and low dosage on the substrate layer 101 with the first barrier layer 210 by using N-type impurity ions; so that the N-type implantation region 102 is formed in the base layer 101 not covered with the first barrier layer 210.
Wherein the ion implantation energy of the first low-energy and high-dose ion implantation is 30 keV-100 keV, and the ion implantation dose is 1e 13-5 e14 ions/cm2The ion implantation energy of the second high-energy and low-dose ion implantation is 110keV to 1000keV, and the ion implantation dose is 5e11 to 1e13 ions/cm2。
After the formation of the first conductive type implantation region is completed in step S3, the first barrier layer 210 is removed.
Step S4: performing high-temperature oxidation drive-in to oxidize the upper surface of the substrate layer to form an oxide layer, so that the first conductive type injection region is fused into a first conductive type high-resistance region; the thickness of the oxide layer formed by oxidizing the first conductive type injection region is larger than that of the oxide layer formed by oxidizing the non-injection region.
Referring to fig. 1f, which shows a schematic cross-sectional structure of the device after step S4 is completed, in step S4, oxygen is introduced during the high-temperature drive-in process, so that the N-type injection regions 102 in fig. 1e are fused together to form the N-type high-resistance region 112, the upper surface of the base layer 101 is oxidized to form the oxide layer 310, and different regions of the upper surface of the base layer 101 are oxidized to form different thicknesses of the oxide layer 310. As can be seen from comparing fig. 1e and fig. 1f, the upper surface of the substrate layer 101 at the position of the N-type implantation region 102 is oxidized to a higher degree, the thickness of the oxide layer 310 formed is thicker, and the upper surface of the substrate layer 101 at the position (such as the non-implantation region) other than the N-type implantation region 102 is oxidized to a lower degree, and the thickness of the oxide layer 310 formed is thinner.
Since the N-type implanted regions 102 and the non-implanted regions are both alternately arranged around a plurality of circles, the N-type implanted regions 102 and the non-implanted regions are alternately arranged, so that the thicker oxide layers 310 formed by oxidizing the upper surface of the substrate layer 101 at the position of the N-type implanted region 102 and the thinner oxide layers 310 formed by oxidizing the upper surface of the substrate layer 101 at the position of the non-implanted region are also alternately arranged around a plurality of circles, and as shown in fig. 1f, the thicker oxide layers 310 and the thinner oxide layers 310 are alternately arranged, that is, one circle of the thinner oxide layers 310 is located between two adjacent circles of the thicker oxide layers 310.
Step S5: and removing the oxide layer to expose the oxidized upper surface of the substrate layer, wherein the drift region comprises convex regions and concave regions which are alternately distributed.
Referring to fig. 1g, which shows a schematic cross-sectional structure of the device after removing the oxide layer shown in fig. 1f, since in step S4, the upper surface of the base layer 101 is oxidized to different degrees, especially for the drift region 130, which is formed by oxidizing thicker oxide layers 310 and alternating with thinner oxide layers 310. So that after the oxide layer shown in fig. 1f is removed, the upper surface of the substrate layer 101 is uneven, especially for the drift region, the thicker oxide layer 310 is removed to form the recessed region 132, the thinner oxide layer 310 is removed to form the raised region 131, the raised region 131 and the recessed region 132 are alternately distributed at the position of the drift region 130, the raised region 131 and the recessed region 132 are both spaced and surround several circles, and one circle of the raised region 131 is located between two adjacent circles of the recessed region 132.
And step S6, according to the topography of the upper surface of the substrate layer at the drift region position, oxidizing the upper surface of the substrate layer at the drift region position to form a field oxide layer with alternately distributed convex regions and concave regions.
Referring to fig. 1h, which shows a schematic cross-sectional structural diagram of the device after step S6 is completed, as can be seen from fig. 1h, the upper surface of the base layer 101 at the position of the drift region 130 is oxidized to form a field oxide layer 410, and the field oxide layer 410 is formed according to the shape of the upper surface of the base layer 101 at the position of the drift region 130 shown in fig. 1g, so that the field oxide layer 410 also includes alternately distributed raised regions 131 and recessed regions 132, the raised regions 131 and the recessed regions 132 are both spaced and surrounded by several circles, and one circle of raised regions 131 is located between two adjacent circles of recessed regions 132.
Alternatively, an oxidation blocking layer may be formed on the upper surface of the base layer 101 in the region except the drift region 130, as shown in fig. 1g, so that the upper surface of the base layer 101 at the position of the drift region 130 is exposed, and an oxidation step may be performed, so that the upper surface of the base layer 101 at the position of the drift region 130 is oxidized to form the field oxide layer 410 shown in fig. 1 h. Wherein the oxidation barrier layer may be silicon nitride.
Step S7 is to fabricate a polysilicon resistor layer surrounding at intervals on the field oxide layer, so that the polysilicon resistor layer bridges the field oxide layer between the raised region and the recessed region.
Optionally, a polysilicon layer may be deposited on the device structure shown in fig. 1h, and then the polysilicon layer is selectively etched to form a polysilicon resistance layer, the formed polysilicon resistance layer is spirally and alternately surrounded, and the polysilicon resistance layer is bridged over the field oxide layer between the protruding region and the recessed region.
Referring to fig. 1i, which shows a schematic cross-sectional structure of the device after step S7 is completed, as can be seen from fig. 1i, the polysilicon resistor layer 510 includes a first end 511 and a second end 512, the polysilicon resistor layer 510 is spirally wound from the first end 511 to the second end 512 through a plurality of consecutive turns, two adjacent turns of the polysilicon resistor layer 510 are spaced apart, and each turn of the polysilicon resistor layer 510 is bridged between the convex region 131 and the concave region 132 where the field oxide layer 41 is connected, that is, each turn of the polysilicon resistor layer 510 covers the field oxide layer 410 at the boundary between the adjacent convex region 131 and the concave region 132.
The polycrystalline silicon resistance layer is positioned on the drift region and is in bridge connection with the convex region and the concave region of the field oxide layer, so that the polycrystalline silicon resistance layer can play a role of a resistor on one hand, and can also be used as a field plate of the drift region on the other hand to adjust an electric field of the drift region and increase the voltage resistance of the field effect tube.
In addition, in the step of selectively etching the polysilicon layer to form the polysilicon resistor layer, the gate polysilicon structure 520 and the drain field plate structure 530 may also be formed by selectively etching the polysilicon layer. As can be seen from fig. 1i, the gate polysilicon structure 520 is located on the polysilicon resistor layer 510 near the source region 110, the gate polysilicon structure 520 bridges the drift region 130 and the source region 110, and the drain field plate structure 530 is located on the polysilicon resistor layer 510 near the drain region 120.
After step S7 is completed and the structure shown in fig. 1i is formed, a source structure is formed in the source region 110, a drain structure is formed in the drain region 120, and then a metal interconnection layer is formed to form the structure shown in fig. 1j, such that the first end 511 of the polysilicon resistor layer 510 is led out through the first lead 610, the second end 512 is connected to the drain field plate structure 530 and the drain structure and led out through the second lead 620, and the gate polysilicon structure 520 is connected to the source structure and led out through the third lead 630.
The present application also provides a semiconductor structure of a high-voltage resistance device, which can be manufactured by the above-described semiconductor manufacturing method of a high-voltage resistance device.
The semiconductor structure of the high voltage resistor device fabricated with reference to fig. 1h and 1i includes:
a substrate layer 101, wherein the substrate layer 101 includes a drain region 120, a source region 110, and a drift region 130 between the drain region 120 and the source region 110.
A first conductive-type high resistance region 112, the first conductive-type high resistance region 112 being located in the base layer 101, extending through at least the drain region 120, the source region 110, and the drift region 130; the upper surface of the first conductive type high resistance region 112 at the position of the drift region 130 is oxidized to form a field oxide layer 410; the field oxide layer 410 comprises a plurality of circles of raised regions 131 and a plurality of circles of recessed regions 132, and one circle of recessed regions 132 is arranged between two adjacent circles of raised regions 131.
Alternatively, the plurality of circles of raised areas 131 and the plurality of circles of recessed areas 132 may be spirally spaced, and one circle of raised areas 131 is located between two adjacent circles of recessed areas 132.
In addition, the circles of raised areas 131 and the circles of recessed areas 132 may also be concentrically and circularly surrounded, and one circle of raised area 131 is located between two adjacent circles of recessed areas 132.
The polysilicon resistor layer 510 spirally surrounds a plurality of circles on the field oxide layer 410 at intervals, and each circle of the polysilicon resistor layer 510 is bridged on the field oxide layer 410 between the convex region 131 and the concave region 132.
The polysilicon resistor layer 510 includes a first end 511 and a second end 512, and the polysilicon resistor layer 510 is spirally wound from the first end 511 to the second end 512 for several consecutive turns.
With continued reference to fig. 1i, the semiconductor structure of the high voltage resistance device further includes a gate polysilicon structure 520 and a drain field plate structure 530.
The gate polysilicon structure 520 is located on one side of the polysilicon resistor layer 510 close to the source region 110, and the gate polysilicon structure 520 bridges the drift region 130 and the source region 110.
The drain field plate structure 530 is located on a side of the polysilicon resistor layer 510 close to the drain region 120.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010057754A (en) * | 1999-12-23 | 2001-07-05 | 오길록 | A power device with trench drain structure |
| CN104813452A (en) * | 2013-11-27 | 2015-07-29 | 瑞萨电子株式会社 | Semiconductor device |
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2021
- 2021-10-25 CN CN202111239119.0A patent/CN114023740A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010057754A (en) * | 1999-12-23 | 2001-07-05 | 오길록 | A power device with trench drain structure |
| CN104813452A (en) * | 2013-11-27 | 2015-07-29 | 瑞萨电子株式会社 | Semiconductor device |
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