CN114023281A

CN114023281A - Shift register, gate drive circuit and display device

Info

Publication number: CN114023281A
Application number: CN202111442230.XA
Authority: CN
Inventors: 王景棚; 陈鹏; 杜化鲲; 张栋栋; 马力; 张熠点; 陈健健; 吕凤珍; 马金念
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-02-08
Anticipated expiration: 2041-11-30
Also published as: CN114023281B

Abstract

The present disclosure provides a shift register, including: a signal generation circuit configured to generate a gate driving signal and output to the cascade output terminal; a first output control circuit configured to control whether the cascade output terminal and the first signal output terminal are conducted; a second output control circuit configured to control whether the cascade output terminal and the second signal output terminal are conducted; a first compensation circuit configured to output a first compensation signal through the first signal output terminal under the control of the control signal when the cascade output terminal outputs the inactive level; a second compensation circuit configured to output a second compensation signal through a second signal output terminal under the control of the control signal when the cascade output terminal outputs the inactive level; the first compensation signal and the second compensation signal are opposite in potential. The disclosure also provides a gate driving circuit and a display device.

Description

Shift register, gate drive circuit and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, and a display device.

Background

The basic principle of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) for displaying one frame of picture is to input a square wave with a certain width to each row of pixels in sequence from top to bottom through gate (gate) driving, and then output signals required for driving each row of pixels from top to bottom through source (source) in sequence. In order to overcome the above problems, the conventional display device is manufactured by adopting a design of a gate Drive On array (goa) circuit, and compared with the conventional Chip On Film (COF) or Chip On Glass (COG) process, the design of the display device has the advantages that the cost is saved, the aesthetic design of two symmetrical sides of the panel can be realized, and the Bonding area and the peripheral wiring space of the gate Drive circuit can be saved, so that the design of a narrow frame of the display device is realized, and the productivity and the yield of the display device are improved.

Disclosure of Invention

The present disclosure is directed to at least one of the problems of the prior art, and provides a shift register, a gate driving circuit and a display device.

To achieve the above object, in a first aspect, an embodiment of the present disclosure provides a shift register, including: the circuit comprises a signal generating circuit, a first output control circuit, a second output control circuit, a first compensating circuit and a second compensating circuit;

the signal generation circuit is configured to generate a gate driving signal and output the gate driving signal to the cascade output end;

the first output control circuit is configured to control whether the cascade output end and the first signal output end are conducted or not;

the second output control circuit is configured to control whether the cascade output end and the second signal output end are conducted;

the first compensation circuit is configured to output a first compensation signal through the first signal output terminal under the control of a control signal when the cascade output terminal outputs an inactive level;

the second compensation circuit is configured to output a second compensation signal through the second signal output terminal under the control of a control signal when the cascade output terminal outputs an inactive level; the first compensation signal and the second compensation signal are opposite in potential.

In some embodiments, further comprising: a control circuit;

the control circuit is configured to generate the control signal and output the control signal to the first compensation circuit and the second compensation circuit under the control of an indication signal transmitted by an indication signal terminal.

In some embodiments, the control circuit comprises: a sixteenth transistor;

and a first pole of the sixteenth transistor is respectively connected with the first compensation circuit and the second compensation circuit, and a control pole and a second pole of the sixteenth transistor are respectively connected with the indication signal end.

In some embodiments, the first compensation circuit comprises: a fourteenth transistor;

a first pole of the fourteenth transistor is connected with the first signal output end, a second pole of the fourteenth transistor is connected with the first compensation signal end, and a control pole of the fourteenth transistor receives the control signal;

the second compensation sub-circuit comprises: a fifteenth transistor;

a first pole of the fifteenth transistor is connected with the second signal output end, a second pole of the fifteenth transistor is connected with the second compensation signal end, and a control pole of the fifteenth transistor receives the control signal.

In some embodiments, the first output control circuit comprises: a twelfth transistor;

a first pole of the twelfth transistor is connected with the first signal output end, and a control pole and a second pole of the twelfth transistor are respectively connected with the cascade output end;

the second output control circuit includes: a thirteenth transistor;

and a first pole of the thirteenth transistor is connected with the second signal output end, and a control pole and a second pole of the thirteenth transistor are respectively connected with the cascade output end.

In some embodiments, the signal generation circuit comprises: the pull-down circuit comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and a pull-down sub-circuit corresponding to each pull-down control sub-circuit;

the input sub-circuit is configured to pre-charge a pull-up node under the control of an input signal; the pull-up node is a connection node of the input sub-circuit and the output sub-circuit;

the pull-down control sub-circuit is configured to write the effective level signal into a corresponding pull-down node thereof under the control of the effective level signal; the pull-down node is a connection node between one pull-down control sub-circuit and a corresponding pull-down sub-circuit;

the pull-down sub-circuit is configured to write an inactive level signal into the pull-down node corresponding to the pull-up sub-circuit under the control of the voltage of the pull-up node;

the output sub-circuit is configured to output a clock signal as the gate driving signal to the cascade output terminal under control of a voltage of the pull-up node.

In some embodiments, the input sub-circuit comprises: a first transistor;

a first pole of the first transistor is connected with the pull-up node, and a control pole and a second pole of the first transistor are respectively connected with an input signal end;

the output sub-circuit includes: a third transistor and a storage capacitor;

a first pole of the third transistor is connected with the cascade output end, a second pole of the third transistor is connected with a clock signal end, and a control pole of the third transistor is connected with the pull-up node;

the first end of the storage capacitor is connected with the pull-up node, and the second end of the storage capacitor is connected with the cascade output end;

the signal generating circuit further comprises a first reset sub-circuit; the first reset sub-circuit is configured to reset the pull-up node and the cascade output terminal by the inactive level signal under control of a first reset signal; the first reset sub-circuit comprises a second transistor and a fourth transistor;

a first pole of the second transistor is connected with a non-effective level signal end, a second pole of the second transistor is connected with the pull-up node, and a control pole of the second transistor is connected with a first reset signal end;

the first pole of the fourth transistor is connected with the inactive level signal end, the second pole of the fourth transistor is connected with the output end of the output sub-circuit, and the control pole of the fourth transistor is connected with the first reset signal end.

In some embodiments, the signal generation circuit further comprises a second reset sub-circuit; the second reset sub-circuit is configured to reset the pull-up node and the cascade output terminal by the inactive level signal under control of a second reset signal;

the second reset sub-circuit includes: a reset transistor and a seventh transistor;

a first pole of the reset transistor is connected with the inactive level signal end, a second pole of the reset transistor is connected with the pull-up node, and a control pole of the reset transistor is connected with a second reset signal end;

a first pole of the seventh transistor is connected to the inactive level signal terminal, a second pole of the seventh transistor is connected to the output terminal of the output sub-circuit, and a control pole of the seventh transistor is connected to the second reset signal terminal.

In some embodiments, the pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit comprises a sixth transistor and an eighth transistor;

a first pole of the fifth transistor is connected with the pull-down node, a second pole of the fifth transistor is connected with an effective level signal end, and a control pole of the fifth transistor is connected with a first pole of the ninth transistor;

a first pole of the sixth transistor is connected with a non-effective level signal end, a second pole of the sixth transistor is connected with the pull-down node, and a control pole of the sixth transistor is connected with the pull-up node;

a first pole of the eighth transistor is connected to the inactive level signal terminal, a second pole of the eighth transistor is connected to the first pole of the ninth transistor, and a control pole of the eighth transistor is connected to the pull-up node;

and a second pole and a control pole of the ninth transistor are respectively connected with the effective level signal end.

In some embodiments, the signal generation circuit comprises: the first pull-down control sub-circuit and the corresponding first pull-down sub-circuit, the first pull-down node, the second pull-down control sub-circuit and the corresponding second pull-down sub-circuit, the second pull-down node;

the active level signal terminal includes: a first effective level signal end corresponding to the first pull-down control sub-circuit, and a second effective level signal end corresponding to the second pull-down control sub-circuit.

In some embodiments, the signal generation circuit further comprises: a noise reduction sub-circuit; the noise reduction sub-circuit is configured to reduce noise on the pull-up node and the cascade output by the inactive level signal under control of a voltage of the pull-down node.

The noise reduction sub-circuit comprises: a tenth transistor and an eleventh transistor;

a first electrode of the tenth transistor is connected with a non-effective level signal end, a second electrode of the tenth transistor is connected with the pull-up node, and a control electrode of the tenth transistor is connected with the pull-down node;

a first pole of the eleventh transistor is connected to the inactive level signal terminal, a second pole of the eleventh transistor is connected to the output terminal of the output sub-circuit, and a control pole of the eleventh transistor is connected to the pull-down node.

In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, including a plurality of shift registers; the shift register is the shift register in any one of the above embodiments.

In some embodiments, the plurality of shift registers are cascaded;

the indication signal end corresponding to the control circuit of the nth stage shift register is the cascade output end of the (n +4) th stage shift register, and n is a positive integer.

In a third aspect, an embodiment of the present disclosure further provides a display device, including: a gate drive circuit as claimed in any one of the preceding embodiments.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a schematic structural diagram of a display device according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another shift register provided in the embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another shift register provided in the embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another shift register according to an embodiment of the present disclosure;

fig. 6 is a waveform diagram of an output of each signal terminal according to an embodiment of the disclosure.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present disclosure, the shift register, the gate driving circuit and the display device provided in the present disclosure are described in detail below with reference to the accompanying drawings.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element, component, or module discussed below could be termed a second element, component, or module without departing from the teachings of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The transistors employed in the embodiments of the present disclosure may be thin film transistors TFT or field effect transistors or other devices of the same characteristics, and since the source and drain of the transistors employed are symmetrical, there is no difference between the source and drain. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the embodiments of the present invention.

Meanwhile, in the embodiments of the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on when the signal is input to the control electrode of the transistor, and an "inactive level signal" refers to a signal that can control the transistor to be turned off when the signal is input to the control electrode of the transistor. For an N-type transistor, a high level signal is an active level signal, and a low level signal is a non-active level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal. Since the embodiment of the present disclosure is explained by using an N-type transistor, in the following embodiment, an effective level signal terminal is a high level signal terminal VDD, an effective level signal is a high level signal, an ineffective level signal terminal is a low level signal terminal VGL, and an ineffective level signal is a low level signal; also, in some embodiments, the first active level signal terminal is a first high level signal terminal VDDO, the first active level signal is a first high level signal, the second active level signal terminal is a second high level signal terminal VDDE, and the second active level signal is a second high level signal.

Specifically, in an exemplary display device, the display device at least includes a substrate, a Gate driving circuit, a plurality of Gate lines (gates), a plurality of DATA lines (DATA), and pixel units arranged in an array, which are disposed on the substrate.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Specifically, it exemplarily shows a partial structure corresponding to one pixel unit; as shown in fig. 1, which shows a corresponding portion 01 of two output terminals of a shift register, a gate a and a gate B of a TFT, and a pixel unit 02, the embodiment of the present disclosure is based on the dual gate driving structure shown in fig. 1.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure. Specifically, the gate driving circuit includes a plurality of shift registers; as shown in fig. 2, the shift register includes: the circuit includes a signal generation circuit 1, a first output control circuit 2, a second output control circuit 3, a first compensation circuit 4, and a second compensation circuit 5.

Wherein the signal generating circuit 1 is configured to generate the gate driving signal and output to the cascade output terminal GnC.

The first output control circuit 2 is configured to control whether the cascade output terminal GnC and the first signal output terminal GnA are conductive; the second output control circuit 3 is configured to control whether the cascade output terminal GnC and the second signal output terminal GnB are conductive or not.

The first compensation circuit 4 is configured to output a first compensation signal through the first signal output terminal GnA under the control of the control signal when the cascade output terminal GnC outputs the inactive level; a second compensation circuit 5 configured to output a second compensation signal through the second signal output terminal GnB under the control of the control signal when the cascade output terminal GnC outputs the inactive level; the first compensation signal and the second compensation signal have opposite potentials; in some embodiments, the first compensation signal and the second compensation signal are alternately output at a high level and a low level in one period.

In some embodiments, as shown in fig. 2, the shift register further comprises: a control sub-circuit 6; the control sub-circuit 6 is configured to generate and output a control signal to the first compensation circuit 4 and the second compensation circuit 5 under the control of the indication signal transmitted by the indication signal terminal D.

Fig. 3 is a schematic structural diagram of another shift register according to an embodiment of the present disclosure. Specifically, the structure is an embodiment alternative based on the structure shown in fig. 2, and in some embodiments, the structure can be divided into two parts, i.e., signal generation and bias compensation. As shown in fig. 3, the first compensation circuit 4 includes a fourteenth transistor M14, and the second compensation circuit 5 includes a fifteenth transistor M15.

A first pole of the fourteenth transistor M14 is connected to the first signal output terminal GnA, a second pole of the fourteenth transistor M14 is connected to the first compensation signal terminal CA, and a control pole of the fourteenth transistor M14 receives the control signal; a first pole of the fifteenth transistor M15 is connected to the second signal output terminal GnB, a second pole of the fifteenth transistor M15 is connected to the second compensation signal terminal CB, and a control pole of the fifteenth transistor M15 receives the control signal.

In some embodiments, as shown in fig. 3, the first output control circuit 2 includes a twelfth transistor M12, and the second output control circuit 3 includes a thirteenth transistor M13;

a first pole of the twelfth transistor M12 is connected to the first signal output terminal GnA, and a control pole and a second pole of the twelfth transistor M12 are respectively connected to the cascade output terminal GnC; a first pole of the thirteenth transistor M13 is connected to the second signal output terminal GnB, and a control pole and a second pole of the thirteenth transistor are respectively connected to the cascade output terminal GnC.

In some embodiments, as shown in fig. 3, the control circuit 6 includes a sixteenth transistor M16; a first electrode of the sixteenth transistor M16 is connected to the control electrode of the fourteenth transistor M16 and the control electrode of the fifteenth transistor M15, respectively, and a control electrode and a second electrode of the sixteenth transistor M16 are connected to the indication signal terminal D, respectively.

In some embodiments, as shown in fig. 2, the signal generating circuit 1 includes: an input sub-circuit 101, an output sub-circuit 104, at least one pull-down control sub-circuit 102, and a pull-down sub-circuit 103 corresponding to each pull-down control sub-circuit 102, the figure exemplarily showing a case where one pull-down control sub-circuit 102 and one pull-down sub-circuit 103 are provided.

Wherein the input sub-circuit 101 is configured to pre-charge the pull-up node PU under control of an input signal; the pull-up node PU is a connection node of the input sub-circuit 101 and the output sub-circuit 104.

A pull-down control sub-circuit 102 configured to write an active level signal into its corresponding pull-down node PD under control of the active level signal; the pull-down node PD is a connection node between one pull-down control sub-circuit 102 and a corresponding one of the pull-down sub-circuits 103.

The pull-down sub-circuit 103 is configured to write an inactive level signal to its corresponding pull-down node PD under control of the voltage of the pull-up node PU.

The output sub-circuit 104 is configured to output the clock signal as a gate drive signal to the cascade output GnC under control of the voltage of the pull-up node PU.

In some embodiments, as shown in fig. 3, the input sub-circuit 101 includes a first transistor M1; a first pole of the first transistor M1 is connected to the pull-up node PU, and a control pole and a second pole of the first transistor M1 are respectively connected to an Input signal terminal Input for transmitting an Input signal.

In some embodiments, as shown in fig. 3, the output sub-circuit 104 includes a third transistor M3 and a storage capacitor C1; a first pole of the third transistor M3 is connected to the cascade output terminal GnC, a second pole of the third transistor M3 is connected to the clock signal terminal CLK transmitting the clock signal, and a control pole of the third transistor M3 is connected to the pull-up node PU; a first terminal of the storage capacitor C1 is connected to the pull-up node PU, and a second terminal of the storage capacitor C1 is connected to the cascade output GnC.

In some embodiments, as shown in fig. 3, the signal generating circuit 1 further comprises a first reset sub-circuit 105; the first reset sub-circuit 105 is configured to reset the pull-up node PU and the cascade output GnC by an inactive level signal under the control of a first reset signal; the first reset sub-circuit 105 includes a second transistor M2 and a fourth transistor M4; a first pole of the second transistor M2 is connected to a non-active level signal terminal VGL transmitting a non-active level signal, a second pole of the second transistor M2 is connected to a pull-up node, and a control pole of the second transistor M2 is connected to a first Reset signal terminal Reset transmitting a first Reset signal; a first electrode of the fourth transistor M4 is connected to the non-active level signal terminal VGL, a second electrode of the fourth transistor M4 is connected to the output terminal GnC, and a control electrode of the fourth transistor M4 is connected to the first Reset signal terminal Reset.

In some embodiments, as shown in fig. 3, the signal generating circuit 1 further comprises a second reset sub-circuit 106; the second reset sub-circuit 106 is configured to reset the pull-up node PU and the cascade output terminal GnC by an inactive level signal under the control of a second reset signal (also called a frame reset signal); the second reset sub-circuit 106 includes a reset transistor M7' and a seventh transistor M7.

A first electrode of the reset transistor M7 ' is connected to the non-active level signal terminal VGL, a second electrode of the reset transistor M7 ' is connected to the pull-up node PU, and a control electrode of the reset transistor M7 ' is connected to a second reset signal terminal TotalReset for transmitting a second reset signal; a first electrode of the seventh transistor M7 is connected to the non-active level signal terminal VGL, a second electrode of the seventh transistor M7 is connected to the cascade output terminal GnC, and a control electrode of the seventh transistor M7 is connected to the second reset signal terminal TotalReset.

In some embodiments, as shown in FIG. 3, the pull-down control sub-circuit 102 includes a fifth transistor M5 and a ninth transistor M9; the pull-down sub-circuit 103 includes a sixth transistor M6 and an eighth transistor M8.

A first pole of the fifth transistor M5 is connected to the pull-down node PD, a second pole of the fifth transistor M5 is connected to the active level signal terminal VDD transmitting an active level signal, and a control pole of the fifth transistor M5 is connected to a first pole of the ninth transistor M9; a first pole of the sixth transistor M6 is connected to a non-active level signal terminal VGL transmitting a non-active level signal, a second pole of the sixth transistor M6 is connected to the pull-down node PD, and a control pole of the sixth transistor M6 is connected to the pull-up node PU; a first electrode of the eighth transistor M8 is connected to the non-active level signal terminal VGL, a second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9, and a control electrode of the eighth transistor M8 is connected to the pull-up node PU; the second and control electrodes of the ninth transistor M9 are respectively connected to the active level signal terminal VDD.

Fig. 4 is a schematic structural diagram of another shift register provided in the embodiment of the present disclosure, and fig. 5 is a schematic structural diagram of another shift register provided in the embodiment of the present disclosure. Specifically, the structure shown in fig. 4 is an embodied alternative embodiment based on the structure shown in fig. 3; in fig. 5, (a) is a TEG actual measurement image corresponding to the structure of fig. 4, and (B) is an enlarged image of a portion of the actual measurement image mutexcept for the signal generating circuit, which is referred to above for the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, and the sixteenth transistor M16, and is not described herein again, the first signal output terminal and the second signal output terminal thereof respectively output signals to the TFT gate a (TFT-a) and the gate B (TFT-B), and (B) identifies the non-display area (AA) corresponding to the gate a and the gate B. The signal generating circuit 1 includes a first pull-down control sub-circuit and a corresponding first pull-down sub-circuit, and a first pull-down node PDo, and a second pull-down control sub-circuit and a corresponding second pull-down sub-circuit, and a second pull-down node PDe; the active level signal terminal VDD includes: a first active level signal terminal VDDO corresponding to the first pull-down control sub-circuit, and a second active level signal terminal VDDE corresponding to the second pull-down control sub-circuit.

Wherein the first pull-down control sub-circuit comprises a transistor: m5o, M9o, the first pull-down sub-circuit includes transistors M6o, M8 o; the second pull-down control sub-circuit includes a transistor: m5e, M9e, and the second pull-down sub-circuit includes transistors M6e, M8 e. For the connection and operation of the corresponding transistors, reference may be made to the above description of the pull-down control sub-circuit 102 and the corresponding pull-down sub-circuit 103, which is not described herein again; the corresponding manner of only setting a single pull-down control sub-circuit 102 and a pull-down sub-circuit 103 corresponding to the pull-down control sub-circuit in fig. 3 is applicable to the situation with harsh frame requirements, and can effectively utilize the non-display area; the first pull-down control sub-circuit, the first pull-down sub-circuit, the second pull-down control sub-circuit and the second pull-down sub-circuit correspondingly arranged in fig. 4 can realize two sets of pull-down systems with odd-even alternation, so that the workload of the GOA circuit can be reduced, and the service life of the device can be prolonged.

In some embodiments, as shown in fig. 3, the signal generation circuit 1 further includes a noise reduction sub-circuit 107; the noise reduction sub-circuit 107 is configured to reduce noise on the pull-up node PU and the cascade output GnC by an inactive level signal under control of the voltage of the pull-down node PD. The noise reduction sub-circuit 107 includes a tenth transistor M10 and an eleventh transistor M11; a first pole of the tenth transistor M10 is connected to a non-active level signal terminal VGL transmitting a non-active level signal, a second pole of the tenth transistor M10 is connected to the pull-up node PU, and a control pole of the tenth transistor M10 is connected to the pull-down node PD; a first electrode of the eleventh transistor M11 is connected to the non-active level signal terminal VGL, a second electrode of the eleventh transistor M11 is connected to the cascade output terminal GnC, and a control electrode of the eleventh transistor M11 is connected to the pull-down node PD.

In some embodiments and as shown in fig. 4, the signal generation circuit 1 comprises a first noise reduction sub-circuit and a second noise reduction sub-circuit, corresponding to an odd-even alternating mode of operation; the first noise reduction sub-circuit includes transistors M10o, M11o corresponding to the first pull-down control sub-circuit, the first pull-down node PDo; the second noise reduction sub-circuit includes transistors M10e, M11e, which correspond to the second pull-down control sub-circuit, the second pull-down sub-circuit, and the second pull-down node PDe.

An embodiment of the present disclosure provides a shift register, including: the signal generating circuit, the first output control circuit, the second output control circuit, the first compensation circuit and the second compensation circuit can be used for outputting a grid driving signal corresponding to an effective level at two output ends when the cascade output end outputs the effective level, and outputting a first compensation signal and a second compensation signal under the control of a control signal when the cascade output end outputs a non-effective level, wherein the potentials of the first compensation signal and the second compensation signal are opposite, so that in the double-grid driving structure, two grids of a pixel unit TFT are respectively at a high level and a low level within a certain time, the bias voltage problem can be effectively avoided, and bias voltage elimination is realized.

The embodiment of the present disclosure further provides a gate driving circuit, which includes: a plurality of shift registers; the shift register is the shift register in any one of the above embodiments.

In some embodiments, a plurality of shift registers are cascaded; the indication signal end corresponding to the control circuit of the nth stage shift register is the cascade output end of the (n +4) th stage shift register, and n is a positive integer.

The embodiment of the present disclosure further provides a display device, which includes: a gate drive circuit as in any one of the above embodiments.

The shift register and the gate driver circuit provided by the embodiments of the present disclosure are described in detail below with reference to practical applications. The specific structure of the shift register can be seen in fig. 3 to 5, the following detailed description of the driving stages takes fig. 3 as an example, it should be noted that two groups of pull-down control sub-circuits and pull-down sub-circuits are arranged in the odd-even alternating working mode in fig. 4 and 5, and the signal change and signal processing flow of a single one of them in the working state is similar to the following flow, and therefore, the description is omitted.

Fig. 6 is a waveform diagram of an output of each signal terminal according to an embodiment of the disclosure. Specifically, it shows an output waveform of each signal terminal in one Frame (1Frame), which can be divided into a driving phase Display and a Blank phase Blank; in (a), it shows output waveforms corresponding to eight clocks (also called 8CLK, corresponding to CLK 1-CLK 8), first active level signal terminal VDDO, second active level signal terminal VDDE, second reset signal terminal TotalReset, and output waveforms corresponding to first compensation signal terminal CA and second compensation signal terminal CB; in (b), the output waveforms of the clock signal terminal CLKn, the cascade signal terminal GnC, the first signal output terminal GnA, and the second signal output terminal GnB corresponding to any one of the shift registers are shown.

Specifically, for the nth stage shift register, the driving stages thereof at least include an input stage, an output stage, and a reset stage. In the Input stage, for the signal generating circuit 1, when the Input signal inputted from the Input signal terminal Input is a high level signal, the first transistor M1 is turned on, and the Input signal is written into the pull-up node PU connected to the drain of the first transistor M1 via the source and the drain of the first transistor M1, so as to complete the pre-charging of the pull-up node PU; while the sixth transistor M6 and the eighth transistor M8 are turned on, the pull-down node PD between the fifth transistor M5 and the sixth transistor M6 is thus pulled low by the inactive level signal terminal VGL. Since the pull-down node PD controls the tenth transistor M10 and the eleventh transistor M11, the tenth transistor M10 and the eleventh transistor M11 are turned off to prevent leakage of the pull-up node PU and the cascade signal terminal GnC during the input stage.

In the output phase, with the signal generation circuit 1, since the first capacitor C1 is charged in the input phase, the potential of the pull-up node PU is further raised; at this time, the third transistor M3 is turned on, the clock signal inputted from the clock signal terminal CLK is a high level signal, the clock signal is written into the cascade output terminal GnC through the source and the drain of the third transistor M3, and at this time, the cascade output terminal GnC outputs the clock signal as a gate driving signal; at this time, the potential of the pull-down node PD remains low, and the tenth transistor M10 and the eleventh transistor M11 are turned off. For the first output control circuit 2 and the second output control circuit 3, the cascade output terminal GnC outputs an active level, and the twelfth transistor M12 and the thirteenth transistor M13 are turned on; with the control circuit 6, the first compensation circuit 4 and the second compensation circuit 5, since the cascade output terminal G (n +4) C of the shift register of the (n +4) th stage is not outputted, the sixteenth transistor M16 is turned off, so that the fourteenth transistor M14 and the fifteenth transistor M15 are turned off, the first compensation signal terminal CA and the second compensation signal terminal CB transmit the first compensation signal and the second compensation signal which cannot be supplied to the first signal output terminal GnA and the second signal output terminal GnB, and therefore the first signal output terminal GnA and the second signal output terminal GnB output the gate driving signal outputted from the cascade output terminal GnC, corresponding to the ta period in (b).

In the Reset phase, the first Reset signal input by the first Reset signal terminal Reset is a high level signal, the second transistor M2 and the fourth transistor M4 are turned on, and the inactive level signal input by the inactive level signal terminal VGL resets the pull-up node PU connected to the source of the second transistor M2 via the drain and the source of the second transistor M2; the inactive level signal inputted from the inactive level signal terminal VGL resets the cascade output terminal GnC connected to the source of the fourth transistor M4 via the drain and source of the fourth transistor M4; meanwhile, since the potential at the pull-up node PU is pulled low, the sixth transistor M6 and the eighth transistor M8 are turned off, the fifth transistor M5 and the ninth transistor M9 are turned on, and the potential of the pull-up node PU is raised; the tenth transistor M10 and the eleventh transistor M11 are turned on to reduce noise at the pull-up node PU and the cascade output GnC. The cascade output terminal GnC outputs an inactive level, the twelfth transistor M12 and the thirteenth transistor M13 are turned off, the cascade output terminal G (n +4) C of the shift register of the (n +4) th stage has an output, the sixteenth transistor M16 is turned on, so that the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the first compensation signal and the second compensation signal transmitted from the first compensation signal terminal CA and the second compensation signal terminal CB are supplied to the first signal output terminal GnA and the second signal output terminal GnB, corresponding to the tb period in (b).

Specifically, the waveform is in a state where high and low levels are alternated with each other, which does not cause leakage, and meanwhile, the gates a and B of the TFTs corresponding to the first signal output terminal GnA and the second signal output terminal GnB are both at the high level and the low level for a certain time, which effectively avoids the problem of bias voltage, and meanwhile, when the cascade output terminal G (n +4) C of the (n +4) -th shift register is pulled down to the low level due to the output of the cascade output terminal G (n +8) C of the (n +8) -th shift register, the control electrode of the sixteenth transistor M16 is turned off, and the control electrodes of the fourteenth transistor M14 and the fifteenth transistor M15 are kept at the high potential and are turned on normally.

In some embodiments, for the first compensation signal and the second compensation signal transmitted by the first compensation signal terminal CA and the second compensation signal terminal CB in (a), on the basis of ensuring that the duty ratio corresponding to the low level is at least 50%, the time period corresponding to the low level portion may be changed according to the requirement of actually eliminating the bias voltage, so as to achieve a better bias voltage elimination effect.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A shift register, comprising: the circuit comprises a signal generating circuit, a first output control circuit, a second output control circuit, a first compensating circuit and a second compensating circuit;

2. The shift register of claim 1, further comprising: a control circuit;

3. The shift register of claim 2, wherein the control circuit comprises: a sixteenth transistor;

4. The shift register of claim 1, wherein the first compensation circuit comprises: a fourteenth transistor;

the second compensation sub-circuit comprises: a fifteenth transistor;

5. The shift register of claim 1, wherein the first output control circuit comprises: a twelfth transistor;

the second output control circuit includes: a thirteenth transistor;

6. The shift register according to claim 1, wherein the signal generation circuit comprises: the pull-down circuit comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and a pull-down sub-circuit corresponding to each pull-down control sub-circuit;

7. The shift register of claim 6, wherein the input subcircuit comprises: a first transistor;

the output sub-circuit includes: a third transistor and a storage capacitor;

8. The shift register of claim 7, wherein the signal generation circuit further comprises a second reset sub-circuit; the second reset sub-circuit is configured to reset the pull-up node and the cascade output terminal by the inactive level signal under control of a second reset signal;

9. The shift register of claim 6, wherein the pull-down control subcircuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit comprises a sixth transistor and an eighth transistor;

10. The shift register of claim 9, wherein the signal generation circuit comprises: the first pull-down control sub-circuit and the corresponding first pull-down sub-circuit, the first pull-down node, the second pull-down control sub-circuit and the corresponding second pull-down sub-circuit, the second pull-down node;

11. The shift register of claim 6, wherein the signal generation circuit further comprises: a noise reduction sub-circuit; the noise reduction sub-circuit is configured to reduce noise on the pull-up node and the cascade output by the inactive level signal under control of a voltage of the pull-down node.

12. A gate driving circuit includes a plurality of shift registers; the shift register is the shift register according to any one of claims 1 to 11.

13. The gate driver circuit according to claim 12, wherein the plurality of shift registers are cascaded;

14. A display device, comprising: a gate drive circuit as claimed in claim 12 or 13.