CN114020666A - DMA transmission system and method applied to NVMe SSD - Google Patents
DMA transmission system and method applied to NVMe SSD Download PDFInfo
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- CN114020666A CN114020666A CN202111317698.6A CN202111317698A CN114020666A CN 114020666 A CN114020666 A CN 114020666A CN 202111317698 A CN202111317698 A CN 202111317698A CN 114020666 A CN114020666 A CN 114020666A
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- dma
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention utilizes the advantages of DMA in a hardware layer to enable the DMA descriptor to configure SQ Identifier, SQ Head Pointer and Command ID information at first, so that the DMA can automatically complete the message transmission after the data transmission is finished, the action that each NVME IO Command needs to independently start the DMA Engine is avoided, the firmware operation in a software layer is not needed, each Command can automatically reply the Completion message, the processing delay of each Command is greatly shortened, and the IOPS is improved.
Description
Technical Field
The invention belongs to the field of computer data transmission, and particularly relates to a network video disk (NVMe SSD) application method.
Background
NVMe SSD is a Solid State drive (Solid State Disk) that complies with the Non-Volatile Memory host controller interface specification (Non-Volatile Memory express). The SSD is composed of a controller and a memory. An excellent controller of NVMe SSD can make full use of the low latency and the parallelism of PCIE channels, greatly improves the read-write performance of the solid state disk under controllable storage cost, reduces the high latency caused by an AHCI interface, and completely liberates the extreme performance of the STAT time solid state disk.
In data interaction between NVMe SSD and Host, DMA is an indispensable data transmission mode. The way the controller DMA determines the performance of the SSD. In the traditional NVMe SSD Controller, a single NVME IO command is adopted to configure a single DMA, after DMA transmission is finished, a Completion message is replied to Host by firmware operation on a software level, the mode has larger time delay for command processing, and in addition, each NVME IO needs to be configured with DMA independently, continuous self-transmission cannot be realized, the utilization of bus bandwidth cannot be optimal, and the data transmission efficiency is low.
Disclosure of Invention
In order to solve the above problems, the present invention needs to provide a system and method that can significantly reduce the processing delay of commands and improve the performance of the entire disk.
The technical scheme provided by the invention is as follows:
a DMA transmission system applied to NVMe SSD comprises a host, equipment, a system bus and a DMA controller, wherein a DMA Descriptor (DMA Descriptor) of the DMA controller is configured with SQ Identifier, SQ Head Pointer and Command ID information before data transmission is initiated.
Preferably, the DMA descriptor is further configured with a host memory address, an SSD internal memory address, and transfer data length information before initiating the data transfer.
Preferably, the DMA descriptor is a DMA descriptor chain formed from a plurality of single DMA descriptors.
Preferably, Next Descriptor information is also configured in the DMA Descriptor chain.
A corresponding DMA transmission method applied to NVMe SSD comprises the following steps:
a) firstly configuring SQ Identifier, SQ Head Pointer and Command ID information by the DMA descriptor;
b) the DMA controller initiates data transmission of an NVMe IO command;
c) the DMA engine performs the transfer of the Completion message.
Preferably, step a) further comprises: the DMA descriptor configures a host memory address, an SSD internal memory address, and transfer data length information.
Preferably, step a) further comprises: next Descriptor information is configured at the last of DWORD;
the step b) further comprises: after the DMA engine finishes transmitting one DMA Descriptor, starting the transmission of the Next DMA Descriptor according to the Next Descriptor described by the DMA Descriptor, and stopping the DMA transmission until the Next Descriptor taken by the DMA engine is empty.
The invention utilizes the advantages of DMA at the hardware level to complete the priority configuration of the descriptor, so that the DMA can automatically complete the transmission of the message after the data transmission is finished, the action that each NVME IO command needs to independently start the DMA Engine is avoided, the firmware operation at the software level is not needed, each command can automatically reply the Completion message, the processing delay of each command is greatly shortened, and the IOPS is improved.
In addition, the invention can automatically transmit the data of the multiple NVME IO commands according to the setting of the descriptor chain, thereby improving the bus bandwidth utilization rate when the multiple NVME IO commands are parallel.
Drawings
FIG. 1 is a diagram showing the structure of a DMA descriptor in embodiment 2;
fig. 2 is a diagram illustrating the structure of a DMA descriptor chain in embodiment 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The invention provides a DMA (direct memory access) transmission method applied to an NVMe (network video disk) SSD, which is characterized in that before data transmission of an NVMe IO (input/output) Command is initiated, information such as PRP (priority protocol), Command ID (identity), SQ Identifier, SQ Head Pointer and the like is configured into a DMA descriptor (DMA descriptor) by DMA, the data transmission is carried out after the data transmission of the NVMe IO Command is initiated, after the data transmission of the DMA is completed, a Completion message is automatically sent to a Host, and the Completion message of the NVMe IO Command is initiated to the Host without using firmware after the DMA is completed.
Example 2
On the basis of embodiment 1, the DMA descriptor may be extended to a DMA descriptor chain (DMA description chain), as shown in fig. 2.
The configuration structure of each DMA Descriptor is shown in fig. 1, DWORD0 is configured as SQ Identifier, DWORD1 is configured as SQ Head Pointer, DWORD2 is configured as Command ID, DWORD3-4 and DWORD5-6 are respectively configured as PRP1 and PRP2 (Host memory address), DWORD7-8 is configured as local address (SSD internal memory address), DWORD9 is configured as Length (data Length to be transmitted), DWORD10-11 is configured as Next Descriptor, and the Next Descriptor content of the last ring of DMA Descriptor is empty.
When a descriptor is started, the DMA engine performs data transfer according to PRP1, PRP2, Local Address, and Length described in the descriptor, for example, an NVMe IO Read command, and the data transfer to be performed by the DMA engine is to Read data from the Local Address and write the data to the Host memory Address pointed by PRP1 and PRP2, and has a Length.
After the data transmission of the descriptor is completed, the DMA engine will transmit the Completion message according to the SQ Identifier, SQ Head Pointer, and Command ID.
After the DMA engine finishes transmitting one DMA Descriptor, the Next DMA Descriptor is transmitted according to the Next Descriptor described by the Descriptor, and the DMA transmission is stopped until the Next Descriptor taken by the DMA engine is empty.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111317698.6A CN114020666A (en) | 2021-11-09 | 2021-11-09 | DMA transmission system and method applied to NVMe SSD |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111317698.6A CN114020666A (en) | 2021-11-09 | 2021-11-09 | DMA transmission system and method applied to NVMe SSD |
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| CN114020666A true CN114020666A (en) | 2022-02-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12056072B1 (en) * | 2021-12-03 | 2024-08-06 | Amazon Technologies, Inc. | Low latency memory notification |
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| US20090100200A1 (en) * | 2007-10-16 | 2009-04-16 | Applied Micro Circuits Corporation | Channel-less multithreaded DMA controller |
| CN107992436A (en) * | 2016-10-26 | 2018-05-04 | 杭州华为数字技术有限公司 | A kind of NVMe data read-write methods and NVMe equipment |
| CN109471816A (en) * | 2018-11-06 | 2019-03-15 | 西安微电子技术研究所 | A kind of PCIE bus dma controller and data transfer control method based on descriptor |
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2021
- 2021-11-09 CN CN202111317698.6A patent/CN114020666A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090100200A1 (en) * | 2007-10-16 | 2009-04-16 | Applied Micro Circuits Corporation | Channel-less multithreaded DMA controller |
| CN107992436A (en) * | 2016-10-26 | 2018-05-04 | 杭州华为数字技术有限公司 | A kind of NVMe data read-write methods and NVMe equipment |
| CN109471816A (en) * | 2018-11-06 | 2019-03-15 | 西安微电子技术研究所 | A kind of PCIE bus dma controller and data transfer control method based on descriptor |
Non-Patent Citations (2)
| Title |
|---|
| AA508508: "二十二、DMA驱动", pages 1 - 3, Retrieved from the Internet <URL:https://blog.csdn.net/aa508508/article/details/102419185?ops_request_misc=%257B%2522request%255Fid%2522%253A%2522171803764116800226528317%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fall.%2522%257D&request_id=171803764116800226528317&biz_id=0&utm_medium=distribute.pc_search_result.none-task-blog-2~all~first_rank_ecpm_v1~rank_v31_ecpm-4-102419185-null-null.142^v100^pc_search_result_base3&utm_term=SGL%E6%8F%8F%E8%BF%B0%E7%AC%A6%20DMA%E6%8F%8F%E8%BF%B0%E7%AC%A6&spm=1018.2226.3001.4187> * |
| CHAOBOWX: "高速的、标准化的存储接口NVMe", pages 1 - 3, Retrieved from the Internet <URL:https://mp.weixin.qq.com/s/FGetbTOXj4lb9IALOmUTRw> * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12056072B1 (en) * | 2021-12-03 | 2024-08-06 | Amazon Technologies, Inc. | Low latency memory notification |
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Application publication date: 20220208 |
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