CN114006612A - High side gate drive circuit - Google Patents

Abstract

The application discloses high-voltage side grid driving circuit belongs to high-voltage power integrated circuit technical field. The circuit comprises: the circuit comprises a dynamic pulse generating circuit, a high-voltage level shifting circuit, a common-mode filter circuit, an RS trigger and an output stage buffer circuit which are connected in sequence; when the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the high-voltage side in a floating way. This application can avoid output signal by the mistake latch-up, promotes the reliability of chip.

Description

High side gate drive circuit

technical field

The embodiments of the present application relate to the technical field of high-voltage power integrated circuits, and in particular, to a high-voltage side gate drive circuit.

Background technique

In the high-voltage floating gate driver chip, a high-voltage level shift circuit is required to transfer the low-voltage domain signal to the high-voltage domain, as shown in Figure 1, _MH is the high-side switching device in the half-bridge topology, and _ML is a low-side switching device in a half-bridge topology. Usually a floating gate driver chip is used to effectively drive the high-side switching device _MH . The floating gate driver chip includes a low-voltage input logic, a high-voltage region gate driver circuit and a low-voltage region gate driver circuit. LIN is the input of the low-side channel. Signal, HIN is the input signal of the high-side channel, LIN and HIN are both connected to the low-voltage input logic, and the low-voltage input logic outputs IN_L and IN_H these two signals, where IN_L is output to the low-voltage region gate drive circuit, and IN_H is output to the high-voltage region gate. pole drive circuit. LO is the output signal of the low-side channel, connected to the gate of _ML , and HO is the output signal of the high-side channel, connected to the gate of _MH . The VCC to GND voltage domain supplies power to the low-voltage region circuit, the VB to VS floating voltage domain supplies power to the high-voltage region circuit, and the VS terminal is connected to the source of _MH and the drain of _ML . _The bootstrap diode DB and the bootstrap capacitor _CB are used to supply power for VB. When _ML is turned on, _VCC charges the bootstrap capacitor _CB through DB and supplies power to the gate drive circuit in the high voltage region; when _MH is turned on, the The lifting capacitor _CB undertakes the task of supplying power to the gate drive circuit in the high voltage region, and so on. One end of the inductor L is connected to the VS end and the other end is connected to the output voltage Vout. The capacitor C and the resistor R ₀ are connected in parallel, one end of which is connected to Vout and the other end is connected to GND. In a high-voltage floating gate driving chip, the low-voltage domain signal from VCC to GND needs to be transmitted to the high-voltage domain between VB and VS, so a high-voltage level shift circuit is required to achieve the above purpose. The traditional single-channel LDMOS (Laterally Diffused Metal Oxide Semiconductor) level shift circuit will turn on the LDMOS for a long time when it is turned on, which requires extremely high reliability of the integrated high-voltage lateral FET. While limiting the maximum working voltage of the chip, it will cause great power consumption and reliability problems.

In order to solve the above problems, the more commonly used signal transmission method is shown in Figure 2. The rising edge and falling edge of the input wide pulse signal are converted into a narrow pulse signal respectively, and the two channels are narrowed after the signal is transmitted to the high voltage area. The pulse signal is restored to a signal with the same width as the original signal by the RS flip-flop. This solution greatly reduces the turn-on time of the LDMOS, reduces the power consumption of the overall chip, and enables the LDMOS to work reliably and stably. With the rise of the current third-generation semiconductors, the switching frequency of power devices made of third-generation semiconductors, especially those made of gallium nitride materials, is extremely high, which puts forward higher requirements for the minimum pulse width that the chip can respond to. .

Figure 3 shows the output response of the chip when a wider input pulse and a narrower input pulse are input. When the input signal IN is a wider pulse (the left half of Fig. 3), the pulse generating circuit forms a narrow pulse signal at the _{PG_S} and PG_R ports with the rising and falling edges of the input signal at time _t1 and time t4 respectively. , the PG_S signal is transmitted to the HD_S port of the high-voltage region through the high-voltage level shift circuit, forming a low-level narrow pulse. At the same time, the driven MOS device in the high-voltage region turns on at time _t2 after a delay and causes VS The potential of the port is raised, which will cause the drain potential of the LDMOS to appear as a logic low potential (with VS as the reference zero point). Therefore, during the time period from t ₂ to t ₃ , the HD_S and HD_R ports both appear as a logic low potential , the common-mode low potential of HD_R and HD_S will be filtered out by the common-mode filter circuit. Therefore, during this time period, the voltages at the S and R terminals are both logic low levels. _At time t4, the PG_R signal is transmitted to the HD_R port of the high-voltage area through the high-voltage level shift circuit. After the common-mode filter circuit, a high-level narrow pulse signal is formed at the R terminal. After a period of delay, the HO changes to a low-voltage signal. level signal, and then the voltage at the VS terminal gradually drops to zero level. When the input signal IN is a narrow pulse (the right half in Figure 3), at time t6, the rising edge of the input signal IN forms a narrow pulse signal at the _{PG_S} port, which is transmitted to the high voltage through the high voltage level shift circuit After a delay, HO becomes a high level at time t7, and the power device of the high _- voltage bridge wall is turned on, and then the VS voltage starts to rise. It can be seen from the above description, When the VS voltage is rising, the potential of the LDMOS drain terminal shows a logic low level signal. Therefore, during the time period from t ₇ to t ₁₀ , the voltages at the HD_R and HD_S terminals show a logic low level. During this time period, all signals are will be filtered out by the common mode filter circuit. From time _t8 to time _t9 , the falling edge pulses caused by the input signal are all in the rising phase of VS, then the reset pulse signal will be lost, which will cause the high-voltage region output signal HO to remain in the latched state after the output becomes high. , cannot be turned off until the next falling edge pulse is effectively delivered to the high voltage region. At this stage, if the low-side signal outputs a high level and the low-side power device is turned on, it will cause the upper and lower bridge arms to pass through and damage the power device. Similarly, when the input signal IN exhibits a high duty cycle, that is, a narrow negative pulse, the HD_S signal will be drowned out in the falling phase of VS, and the HO output will lose waves.

SUMMARY OF THE INVENTION

The embodiment of the present application provides a high-voltage side gate drive circuit, which can solve the problem that the falling edge pulse of the high-level narrow pulse is in the rising phase of VS, causing the output signal to be falsely locked in a constant-high state and damaging the low-side power device. It can also solve the problem that the rising edge pulse of the low-level narrow pulse is in the rising phase of VS, which causes the output signal to be locked in a constant low state by mistake, and there is a problem of output wave loss. The technical solution is as follows:

In one aspect, a high voltage side gate drive circuit is provided, the high voltage side gate drive circuit includes a dynamic pulse generation circuit, a high voltage level shift circuit, a common mode filter circuit, an RS flip-flop and an output stage buffer circuit;

The input end of the dynamic pulse generation circuit is used as the input end of the high voltage side gate drive circuit, and the first output end of the dynamic pulse generation circuit is connected to the first input end of the high voltage level shift circuit, so the the second output end of the dynamic pulse generating circuit is connected with the second input end of the high voltage level shift circuit;

The two output ends of the high-voltage level shift circuit are respectively connected with the two input ends of the common mode filter circuit, and the two output ends of the common mode filter circuit are respectively connected with the set end of the RS flip-flop connected to the reset terminal;

The output end of the RS flip-flop is connected to the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit serves as the output end of the high-voltage side gate drive circuit;

the high voltage level shift circuit, the common mode filter circuit, the RS flip-flop and the output stage buffer circuit are respectively connected to the high voltage side power supply and the high voltage side floating ground;

When the input signal is a narrow pulse, the dynamic pulse generating circuit is configured to adjust the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the adjusted end time of the pulse is later than the high voltage The end time of the side-floating mutation.

In a possible implementation manner, the high-voltage level shift circuit includes: a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode, and a second diode;

The gate of the first LDMOS serves as the first input end of the high-voltage level shift circuit, the gate of the second LDMOS serves as the second input end of the high-voltage level shift circuit, and the first the sources of the LDMOS and the second LDMOS are grounded;

The drain of the first LDMOS, the first port of the first resistor, and the cathode of the first diode are connected to a first connection point, and the first connection point serves as the high-voltage level shift circuit the first output terminal of ;

The drain of the second LDMOS, the first port of the second resistor, and the cathode of the second diode are connected to a second connection point, and the second connection point serves as the high-voltage level shift circuit the second output terminal of ;

The second port of the first resistor and the second port of the second resistor are respectively connected to the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected to the high-voltage side. side floating connection.

In one possible implementation,

When the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is configured to control the falling edge pulse width of the high-level narrow pulse; or,

When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is configured to control the pulse width of the rising edge of the low-level narrow pulse; or,

When the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is used to control the pulse width of the falling edge of the high-level narrow pulse and the rise of the low-level narrow pulse edge pulse width.

In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source and a falling edge pulse edge pulse generation circuit;

The input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the dynamic pulse generating circuit the first output end of the pulse generating circuit, the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;

The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the falling edge pulse generating circuit;

The output terminal of the falling edge pulse generating circuit is used as the second output terminal of the dynamic pulse generating circuit.

In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, The first inverter, the second inverter, the first NOR gate, the second NOR gate, the third NOR gate and the fourth NOR gate;

The input terminal of the rising edge pulse generating circuit is connected with the input terminal of the falling edge pulse generating circuit and then used as the input terminal of the dynamic pulse generating circuit; the output terminal of the rising edge pulse generating circuit is used as the dynamic pulse generating circuit. the first output end of the circuit, the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit;

The output end of the delay circuit is respectively connected to the third connection point with the first input end of the first NOR gate and the second NOR gate;

The output end of the falling edge pulse generating circuit is respectively connected with the input end of the first inverter and the second input end of the fourth NOR gate to the fourth connection point; The output end is connected with the second input end of the first NOR gate; the output end of the first NOR gate is connected with the second input end of the second NOR gate; The output terminal is connected with the first input terminal of the third NOR gate; the output terminal of the third NOR gate is connected with the first input terminal of the fourth NOR gate; The output end is respectively connected with the input end of the second inverter and the second input end of the third NOR gate; the output end of the second inverter is used as the second output of the dynamic pulse generating circuit end.

In one possible implementation,

When the third connection point is high level and the fourth connection point is high level, the output of the second output terminal of the dynamic pulse generating circuit is high level;

When the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state;

When the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is an effective high level;

When the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is an invalid low level.

In a possible implementation, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit and controlled current source;

The first input terminal of the rising edge pulse generating circuit is connected with the input terminal of the falling edge pulse generating circuit and then used as the input terminal of the dynamic pulse generating circuit; the output terminal of the falling edge pulse generating circuit is used as the dynamic pulse generating circuit. a second output end of the pulse generating circuit, the output end of the falling edge pulse generating circuit is connected to the input end of the delay circuit;

The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the rising edge pulse generating circuit;

The output terminal of the rising edge pulse generating circuit is used as the first output terminal of the dynamic pulse generating circuit.

In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse a generating circuit, a first delay circuit, a second delay circuit, a first controlled current source and a second controlled current source;

The first input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the input end of the dynamic pulse generating circuit; The first output end of the dynamic pulse generation circuit, the output end of the rising edge pulse generation circuit is connected to the input end of the first delay circuit; the output end of the falling edge pulse generation circuit is used as the dynamic pulse generation a second output end of the circuit, the output end of the falling edge pulse generating circuit is connected to the input end of the second delay circuit;

The output end of the first delay circuit is connected to the input end of the first controlled current source, and the output end of the first controlled current source is connected to the second input end of the falling edge pulse generating circuit; The output end of the second delay circuit is connected to the input end of the second controlled current source, and the output end of the second controlled current source is connected to the second input end of the rising edge pulse generating circuit.

In one possible implementation,

The rising edge pulse generating circuit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate, when the rising edge pulse generating circuit When including one input end, the input end of the third inverter is used as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit includes two input ends, the third inverter The two input terminals of the inverter are respectively used as the first input terminal and the second input terminal of the rising edge pulse generating circuit; the output terminal of the third inverter is respectively connected with the input terminal of the fourth inverter and the The second input end of the fifth NOR gate is connected, the output end of the fourth inverter is connected to the positive electrode of the first capacitor and the input end of the fifth inverter respectively, and the output end of the first capacitor is connected to the The negative pole is grounded, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the first input end of the fifth NOR gate , the output end of the fifth NOR gate is used as the output end of the rising edge pulse generating circuit;

The falling edge pulse generating circuit includes a seventh inverter, an eighth inverter, a ninth inverter, a second capacitor and a sixth NOR gate, and when the falling edge pulse generating circuit includes an input terminal, The input end of the seventh inverter is used as the input end of the falling edge pulse generating circuit, and the input end of the falling edge pulse generating circuit is connected with the second input end of the sixth NOR gate; when the When the falling edge pulse generating circuit includes two input terminals, the two input terminals of the seventh inverter are respectively used as the first input terminal and the second input terminal of the falling edge pulse generating circuit, and the falling edge pulse generating circuit The first input end of the circuit is connected to the second input end of the sixth NOR gate; the output end of the seventh inverter is respectively connected to the positive electrode of the second capacitor and the input of the eighth inverter The negative terminal of the second capacitor is connected to the ground, the output terminal of the eighth inverter is connected to the input terminal of the ninth inverter, and the output terminal of the ninth inverter is connected to the sixth inverter. The first input end of the NOR gate is connected, and the output end of the sixth NOR gate is used as the output end of the falling edge pulse generating circuit;

The delay circuit includes a tenth inverter, an eleventh inverter and a third capacitor, the input end of the tenth inverter is used as the input end of the delay circuit, and the tenth inverter The output terminals of the inverter are respectively connected to the positive terminal of the third capacitor and the input terminal of the eleventh inverter, the negative terminal of the third capacitor is grounded, and the output terminal of the eleventh inverter is used as the delay terminal. The output terminal of the circuit;

When the dynamic pulse generating circuit further includes the controlled current source, the controlled current source includes a current source and a PMOS transistor, the current source is connected between the power supply and the source stage of the PMOS transistor, the The gate of the PMOS transistor serves as the input end of the controlled current source, and the drain of the PMOS transistor serves as the output end of the controlled current source.

In a possible implementation manner, the delay value of the delay circuit is determined according to the formula t _P +(ΔV _S × R _L ×C _DS )/(VB-Vth), where the VB is the the high-voltage side power supply, the R _L is the load resistance of the high-voltage level shift circuit, the C _DS is the drain-source parasitic capacitance of the LDMOS, the Vth is the threshold of the common-mode filter circuit, and the ΔV _S is the variation of the voltage of the high-side floating ground, and the t _P is the delay time from the LDMOS to the high-side output terminal.

The beneficial effects of the technical solutions provided by this application at least include:

1. The high-voltage side gate drive circuit in this application can dynamically adjust the pulse width of the rising edge and/or falling edge of the narrow pulse to prevent the output signal from being mistakenly locked in a constant high or constant low state, so as to ensure the reliability of the chip sex.

2. The maximum delay value of the pulse width comes from the minimum speed of LDMOS drain charge discharge, which ensures that the pulse signal will not be submerged in the VS voltage change stage.

3. Simple structure to avoid extra cost.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

Figure 1 shows a half-bridge topology using a high-voltage floating gate driver chip;

FIG. 2 is a high-voltage level shift circuit using dual-channel LDMOS in the prior art;

Fig. 3 is the waveform diagram of normal operation and fault operation of the double-pulse circuit shown in Fig. 2;

4 is a circuit diagram of a high-voltage side gate drive circuit according to the present application;

5 is a circuit diagram of a dynamic pulse generating circuit;

Fig. 6 is the working schematic waveform diagram of the circuit in Fig. 5;

FIG. 7 is a circuit diagram of the circuit in FIG. 5;

8 is a circuit diagram of another dynamic pulse generating circuit;

Fig. 9 is the working schematic waveform diagram of the circuit in Fig. 8;

10 is a circuit diagram of another dynamic pulse generating circuit;

FIG. 11 is a circuit diagram of another dynamic pulse generating circuit.

Detailed ways

In order to make the objectives, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Please refer to FIG. 4, which shows a high-side gate drive circuit provided by an embodiment of the present application, including a dynamic pulse generation circuit, a high-voltage level shift circuit, a common-mode filter circuit, an RS flip-flop, and an output stage buffer circuit (Buffer).

The input end of the dynamic pulse generation circuit is used as the input end of the high-voltage side gate drive circuit, the first output end of the dynamic pulse generation circuit is connected with the first input end of the high voltage level shift circuit, and the second output end of the dynamic pulse generation circuit is connected to the second input terminal of the high voltage level shift circuit. The input signal IN_H of the dynamic pulse generating circuit comes from the input signal of the high-voltage side channel, the output signal of the first output terminal of the dynamic pulse generating circuit is PG_S, and the output signal of the second output terminal is PG_R.

The two output ends of the high voltage level shift circuit are respectively connected with the two input ends of the common mode filter circuit, and the two output ends of the common mode filter circuit are respectively connected with the set end S and the reset end R of the RS flip-flop.

The output end of the RS flip-flop is connected to the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit serves as the output end of the high voltage side gate drive circuit. The output end of the output stage buffer circuit is the output port of the high-side channel.

The high voltage level shift circuit, the common mode filter circuit, the RS flip-flop and the output stage buffer circuit are respectively connected with the high voltage side power supply VB and the high voltage side floating ground VS. That is, the high voltage level shift circuit, the common mode filter circuit, the RS flip-flop and the output stage buffer circuit are connected between VB and VS.

When the input signal is a narrow pulse, the dynamic pulse generating circuit is used to adjust the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the adjusted end time of the pulse is later than the end time of the high-side floating ground VS sudden change . That is, when the input pulse width is narrow, the pulse width of the rising edge and/or the falling edge of the input signal can be adaptively adjusted to obtain the pulse block widths of PG_S and PG_R.

The narrow pulse refers to a pulse whose pulse width is smaller than a predetermined threshold. The predetermined threshold here is determined according to the formula t _P +(ΔV _S ×R _L ×C _DS )/(VB-Vth), where VB is the high-voltage side power supply, R _L is the load resistance of the high-voltage level shift circuit, C _DS is the drain-source parasitic capacitance of the LDMOS, Vth is the threshold of the common-mode filter circuit, _{ΔVS is the variation of the floating ground voltage on the high-voltage side, and t P is} the delay time from the LDMOS to the high-side output terminal.

As shown in FIG. 4 , the high voltage level shift circuit includes: a first LDMOS LD ₃ , a second LDMOS LD ₄ , a first resistor R ₁ , a second resistor R ₂ , a first diode D ₃ and a second diode tube D4 _;

The gate of the first LDMOS LD ₃ is used as the first input terminal of the high voltage level shift circuit, the gate of the second LDMOS LD ₄ is used as the second input terminal of the high voltage level shift circuit, the first LDMOS LD ₃ and the second The source of the LDMOS LD ₄ is grounded; the drain of the first LDMOS LD ₃ is connected to the first port of the first resistor R ₁ and the cathode of the first diode D ₃ is connected to the first connection point HD_S, and the first connection point HD_S serves as The first output terminal of the high-voltage level shift circuit; the drain of the second LDMOS LD ₄ is connected to the first port of the second resistor R ₂ , the cathode of the second diode D ₄ is connected to the second connection point HD_R, the second The connection point HD_R is used as the second output terminal of the high-voltage level shift circuit; the second port of the _first resistor R1 and the _second port of the second resistor R2 are respectively connected to the high-voltage side power supply VB, and the first diode _D3 and the anodes of the second diode D4 are respectively connected to the high _- voltage side floating ground VS.

The input of the first input terminal of the high voltage level shift circuit is PG_S, which acts on the gate of LD ₃ ; the input of the second input terminal of the high voltage level shift circuit is PG_R, which acts on the gate of LD ₄ . _The functions of the first diode _D3 and the second diode D4 are to clamp the voltages of HD_S and HD_R to protect the gate of the common mode filter circuit.

The form of dynamic pulse generation circuit can include the following three:

1) When the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is used to control the pulse width of the falling edge of the high-level narrow pulse.

2) When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is used to control the pulse width of the rising edge of the low-level narrow pulse. in,

3) When the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse and the rising edge pulse width of the low-level narrow pulse.

Among them, the high-level narrow pulse has a relatively low duty cycle, for example, the duty cycle is close to 0%. The low-level narrow pulse has a higher duty cycle, eg, the duty cycle is close to 100%.

The circuit structures of these three forms of dynamic pulse generating circuits are introduced separately below.

As shown in Figure 5, in the first implementation of the first form, when the dynamic pulse generating circuit is used to control the width of the falling edge pulse, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled Current source and falling edge pulse generation circuit.

The input terminal of the rising edge pulse generating circuit is connected with the first input terminal of the falling edge pulse generating circuit as the input terminal of the dynamic pulse generating circuit; the output terminal of the rising edge pulse generating circuit is the first output terminal of the dynamic pulse generating circuit. Among them, the input terminal of the rising edge pulse generation circuit and the first input terminal of the falling edge pulse generation circuit input IN_H, and the output terminal of the rising edge pulse generation circuit outputs PG_S.

The output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input of the falling edge pulse generating circuit terminals are connected to control the falling edge pulse width. The output terminal of the falling edge pulse generating circuit is used as the second output terminal of the dynamic pulse generating circuit. Among them, the output terminal of the falling edge pulse generating circuit outputs PG_R.

Figure 6 shows the working waveform of the dynamic pulse generating circuit in Figure 5. Similar to Figure 2, the working waveform can also be divided into a left half and a right half. The left half shows the input with a wider pulse width. Signal, the rising edge pulse signal and its delay signal and the falling edge pulse signal do not overlap, the circuit can work normally; the right half shows the input signal with a narrow pulse width, at this time, in order to prevent the falling edge pulse from being dV/dt Noise submerged, delay the falling edge pulse signal for a period of time, the delay time is determined by formula 2, assuming that the threshold of the response of the common mode filter circuit is Vth, then the expression of dV/dt that can make the common mode filter circuit respond can be obtained The formula is:

Among them, VB is the high-voltage side power supply, _RL is the load resistance of the high-level shift circuit, and C _DS is the drain-source parasitic capacitance of the LDMOS. It can be seen from formula 1 that when the dV/dt value is less than this value, the common mode filter circuit will not respond. Therefore, the delay value of the delay circuit can be obtained:

Among them, t _P is the delay time from the LDMOS to the high-side output terminal HO.

As shown in FIG. 7 , the structures of the rising edge pulse generating circuit, the falling edge pulse generating circuit, the delay circuit and the controlled current source are respectively described below.

The rising edge pulse generating circuit includes a third inverter INV ₈ , a fourth inverter INV ₉ , a fifth inverter INV ₁₀ , a sixth inverter INV ₁₁ , a first capacitor C ₁ and a fifth NOR gate NOR _3. The input end of the third inverter INV ₈ is used as the input end of the rising edge pulse generating circuit; the output end of the third inverter INV ₈ is respectively connected with the input end of the fourth inverter INV ₉ and the fifth NOR gate. The second input terminal of the NOR ₃ is connected to the second input terminal, the output terminal of the fourth inverter INV ₉ is connected to the positive terminal of the first capacitor C ₁ and the input terminal of the fifth inverter INV ₁₀ respectively, and the negative terminal of the first capacitor C ₁ is connected to the ground, The output end of the fifth inverter INV ₁₀ is connected to the input end of the sixth inverter INV ₁₁ , the output end of the sixth inverter INV ₁₁ is connected to the first input end of the fifth NOR gate NOR ₃ , the fifth The output terminal of the NOR gate NOR ₃ is used as the output terminal of the rising edge pulse generating circuit.

The falling edge pulse generating circuit includes a seventh inverter INV ₁₄ , an eighth inverter INV ₁₅ , a ninth inverter INV ₁₆ , a second capacitor C ₂ , a sixth NOR gate NOR ₄ , and a seventh inverter INV The two input terminals of ₁₄ are respectively used as the first input terminal and the second input terminal of the falling edge pulse generating circuit, and the first input terminal of the falling edge pulse generating circuit is connected with the second input terminal of the sixth NOR gate NOR ₄ ; The output terminal of the seven inverter INV ₁₄ is connected to the positive terminal of the second capacitor C ₂ and the input terminal of the eighth inverter INV ₁₅ respectively, the negative terminal of the second capacitor C ₂ is grounded, and the output terminal of the eighth inverter INV ₁₅ is connected to the input end of the ninth inverter INV ₁₆ , the output end of the ninth inverter INV ₁₆ is connected to the first input end of the sixth NOR gate NOR ₄ , and the output end of the sixth NOR gate NOR ₄ serves as a drop The output of the edge pulse generation circuit.

The delay circuit includes a tenth inverter INV ₁₂ , an eleventh inverter INV ₁₃ and a third capacitor C ₃ . The input end of the tenth inverter INV ₁₂ is used as the input end of the delay circuit, and the tenth inverter The output terminal of INV ₁₂ is connected to the positive terminal of the third capacitor C ₃ and the input terminal of the eleventh inverter INV ₁₃ , respectively, the negative terminal of the third capacitor C ₃ is grounded, and the output terminal of the eleventh inverter INV ₁₃ is used as a delay the output of the circuit.

The controlled current source includes a current source I ₁ and a PMOS transistor M ₁ , the current source I ₁ is connected between the power supply and the source stage of the PMOS transistor M ₁ , the gate of the PMOS transistor M ₁ serves as the input end of the controlled current source, and the PMOS _The drain of tube M1 serves as the output of the controlled current source.

As shown in Figure 8, in the second implementation of the first form, when the dynamic pulse generating circuit is used to control the width of the falling edge pulse, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse Pulse generating circuit, first inverter INV ₁₇ , second inverter INV ₁₈ , first NOR gate NOR ₅ , second NOR gate NOR ₆ , third NOR gate NOR ₇ and fourth NOR gate NOR ₈ .

The input end of the rising edge pulse generation circuit is connected with the input end of the falling edge pulse generation circuit as the input end of the dynamic pulse generation circuit; the output end of the rising edge pulse generation circuit is used as the first output end of the dynamic pulse generation circuit, the rising edge pulse The output end of the generating circuit is connected with the input end of the delay circuit. Among them, the input terminal of the rising edge pulse generating circuit and the input terminal of the falling edge pulse generating circuit input IN_H, and the output terminal of the rising edge pulse generating circuit outputs PG_S. The output terminals of the delay circuit are respectively connected with the first input terminals of the first NOR gate NOR ₅ and the second NOR gate NOR ₆ to the third connection point IN1. The output end of the falling edge pulse generating circuit is respectively connected with the input end of the first inverter INV ₁₇ and the second input end of the fourth NOR gate NOR ₈ to the fourth connection point IN2; the output end of the first inverter INV ₁₇ The terminal is connected with the second input terminal of the first NOR gate NOR ₅ ; the output terminal of the first NOR gate NOR ₅ is connected with the second input terminal of the second NOR gate NOR ₆ ; the output of the second NOR gate NOR ₆ The terminal is connected with the first input terminal of the third NOR gate NOR ₇ ; the output terminal of the third NOR gate NOR ₇ is connected with the first input terminal of the fourth NOR gate NOR ₈ ; the output of the fourth NOR gate NOR ₈ The terminals are respectively connected with the input terminal of the second inverter INV ₁₈ and the second input terminal of the third NOR gate NOR ₇ ; the output terminal of the second inverter INV ₁₈ is used as the second output terminal of the dynamic pulse generating circuit. The output terminal of the second inverter INV ₁₈ outputs PG_R.

For the rising edge pulse generating circuit and the delay circuit, reference may be made to the implementation in FIG. 6 . In addition, the falling edge pulse generating circuit in FIG. 6 has two input terminals, while the falling edge pulse generating circuit in FIG. 8 has one input terminal. Therefore, on the basis of the falling edge pulse generating circuit shown in FIG. 6 Make changes. After the modification, the input terminal of the seventh inverter INV14 is used as the input terminal of the falling edge pulse generating circuit, and the input terminal of the falling edge pulse generating circuit is connected with the second input terminal of the sixth NOR gate NOR4, and the rest of the structure remains unchanged.

In this embodiment, when the third connection point IN1 is at a high level and the fourth connection point IN2 is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at a high level; when the third connection point IN1 is at a high level When the fourth connection point IN2 is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state; when the third connection point IN1 is at a low level and the fourth connection point IN2 is at a high level, the dynamic The output of the second output terminal of the pulse generating circuit is a valid high level; when the third connection point IN1 is low level and the fourth connection point IN2 is low level, the output of the second output terminal of the dynamic pulse generating circuit is an invalid low level.

Simply put, in the state of IN1=1, IN2=1, the reset pulse PG_R outputs a high level; in the state of IN1=1, IN2=0, the PG_R signal keeps the previous state unchanged; in IN1=0, In the state of IN2=1, PG_R outputs an active high level; in the state of IN1=0 and IN2=0, PG_R outputs an inactive low level. In this way, when the end time of the rising edge pulse delay signal is later than the end time of the falling edge pulse, the PG_R maintains a valid signal until the end time of the rising edge pulse delay signal.

Figure 9 is a schematic waveform diagram of the circuit in Figure 8. The left half shows the input signal with a wider pulse width. It can be seen that the delay circuit has no effect on the operation of the circuit, and the circuit works normally; the right half shows It is an input signal with a narrow pulse width. IN1 is the delay signal of the rising edge pulse signal PG_S. According to the timing rules of the logic circuit, the falling edge starts when IN2 is high and keeps until the IN1 signal changes from high to low. Effective ground to prevent false triggering of the chip. Among them, the delay value of the delay circuit is determined according to the formula t _P +(ΔV _S ×R _L ×C _DS )/(VB-Vth), where VB is the high-voltage side power supply, and R _L is the high-voltage level shift The load resistance of the circuit, C _DS is the drain-source parasitic capacitance of the LDMOS, Vth is the threshold of the common mode filter circuit, _{ΔVS is the variation of the floating ground voltage on the high-voltage side, and t P is} the delay time from the LDMOS to the high-side output terminal.

As shown in Figure 10, in the second form, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit and a controlled current source.

The first input terminal of the rising edge pulse generating circuit is connected with the input terminal of the falling edge pulse generating circuit and then used as the input terminal of the dynamic pulse generating circuit; the output terminal of the falling edge pulse generating circuit is used as the second output terminal of the dynamic pulse generating circuit. Among them, the first input terminal of the rising edge pulse generating circuit and the input terminal of the falling edge pulse generating circuit input IN_H, and the output terminal of the falling edge pulse generating circuit outputs PG_R.

The output end of the falling edge pulse generating circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input of the rising edge pulse generating circuit The output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit. Among them, the output terminal of the rising edge pulse generating circuit outputs PG_S.

The delay circuit and the controlled current source may refer to the implementation in FIG. 6 , and the falling edge pulse generating circuit may refer to the implementation in FIG. 8 . In addition, the rising edge pulse generating circuit in FIG. 6 has one input terminal, while the rising edge pulse generating circuit in FIG. 10 has two input terminals. Therefore, on the basis of the rising edge pulse generating circuit shown in FIG. 6 Make changes. After the modification, the two input terminals of the third inverter INV ₈ are respectively used as the first input terminal and the second input terminal of the rising edge pulse generating circuit.

Among them, the delay value of the delay circuit is determined according to the formula t _P +(ΔV _S ×R _L ×C _DS )/(VB-Vth), where VB is the high-voltage side power supply, and R _L is the high-voltage level shift The load resistance of the circuit, C _DS is the drain-source parasitic capacitance of the LDMOS, Vth is the threshold of the common mode filter circuit, _{ΔVS is the variation of the floating ground voltage on the high-voltage side, and t P is} the delay time from the LDMOS to the high-side output terminal.

As shown in Figure 11, in the third form, when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a A delay circuit, a second delay circuit, a first controlled current source and a second controlled current source.

The first input terminal of the rising edge pulse generating circuit is connected with the first input terminal of the falling edge pulse generating circuit as the input terminal of the dynamic pulse generating circuit; the output terminal of the rising edge pulse generating circuit is used as the first output terminal of the dynamic pulse generating circuit The output end of the rising edge pulse generation circuit is connected with the input end of the first delay circuit; the output end of the falling edge pulse generation circuit is used as the second output end of the dynamic pulse generation circuit, and the output end of the falling edge pulse generation circuit is connected with the second output end of the dynamic pulse generation circuit. The input terminals of the delay circuit are connected. Among them, the first input terminal of the rising edge pulse generation circuit and the first input terminal of the falling edge pulse generation circuit input IN_H, the output terminal of the rising edge pulse generation circuit outputs PG_S, and the output terminal of the falling edge pulse generation circuit outputs The one is PG_R.

The output end of the first delay circuit is connected with the input end of the first controlled current source, the output end of the first controlled current source is connected with the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit It is connected with the input end of the second controlled current source, and the output end of the second controlled current source is connected with the second input end of the rising edge pulse generating circuit.

The rising edge pulse generation circuit can refer to the implementation of the rising edge pulse generation circuit in Figure 10, and the falling edge pulse generation circuit can refer to the implementation of the falling edge pulse generation circuit in Figure 6. The first delay circuit and the second delay circuit can be Referring to the implementation of the delay circuit in FIG. 6 , the first controlled current source and the second controlled current source may refer to the implementation of the controlled current source in FIG. 6 .

Among them, the delay value of the delay circuit is determined according to the formula t _P +(ΔV _S ×R _L ×C _DS )/(VB-Vth), where VB is the high-voltage side power supply, and R _L is the high-voltage level shift The load resistance of the circuit, C _DS is the drain-source parasitic capacitance of the LDMOS, Vth is the threshold of the common mode filter circuit, _{ΔVS is the variation of the floating ground voltage on the high-voltage side, and t P is} the delay time from the LDMOS to the high-side output terminal.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, etc.

The above is not intended to limit the embodiments of the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included within the protection scope of the embodiments of the present application.

Claims (10)

1. A high-voltage side gate drive circuit is characterized by comprising a dynamic pulse generation circuit, a high-voltage level shift circuit, a common mode filter circuit, an RS trigger and an output stage buffer circuit;

the input end of the dynamic pulse generating circuit is used as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected with the first input end of the high-voltage level shifting circuit, and the second output end of the dynamic pulse generating circuit is connected with the second input end of the high-voltage level shifting circuit;

two output ends of the high-voltage level shift circuit are respectively connected with two input ends of the common-mode filter circuit, and two output ends of the common-mode filter circuit are respectively connected with a set end and a reset end of the RS trigger;

the output end of the RS trigger is connected with the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit is used as the output end of the high-voltage side gate driving circuit;

the high-voltage level shift circuit, the common-mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected with a high-voltage side power supply and a high-voltage side floating ground;

when the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the high-voltage side in a floating mode.

2. The circuit of claim 1, wherein the high voltage level shifting circuit comprises: the power supply comprises a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode and a second diode;

the grid electrode of the first LDMOS is used as a first input end of the high-voltage level shift circuit, the grid electrode of the second LDMOS is used as a second input end of the high-voltage level shift circuit, and the source electrodes of the first LDMOS and the second LDMOS are grounded;

the drain electrode of the first LDMOS, the first port of the first resistor and the cathode of the first diode are connected to a first connecting point, and the first connecting point is used as a first output end of the high-voltage level shift circuit;

the drain of the second LDMOS, the first port of the second resistor and the cathode of the second diode are connected to a second connection point, and the second connection point is used as a second output end of the high-voltage level shift circuit;

and the second port of the first resistor and the second port of the second resistor are respectively connected with the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected with the high-voltage side in a floating mode.

3. The circuit of claim 1,

when the input signal comprises a high-level narrow pulse, the dynamic pulse generating circuit is used for controlling the falling edge pulse width of the high-level narrow pulse; or,

when the input signal comprises a low-level narrow pulse, the dynamic pulse generating circuit is used for controlling the pulse width of the rising edge of the low-level narrow pulse; or,

when the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generation circuit is configured to control a falling edge pulse width of the high-level narrow pulse and a rising edge pulse width of the low-level narrow pulse.

4. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a delay circuit, a controlled current source, and a falling edge pulse generating circuit;

the input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then is used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;

the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the falling edge pulse generating circuit;

and the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit.

5. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter, a second inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a fourth NOR gate;

the input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;

the output end of the delay circuit is respectively connected with the first input ends of the first NOR gate and the second NOR gate at a third connection point;

the output end of the falling edge pulse generating circuit is respectively connected with the input end of the first inverter and the second input end of the fourth NOR gate at a fourth connection point; the output end of the first inverter is connected with the second input end of the first NOR gate; the output end of the first NOR gate is connected with the second input end of the second NOR gate; the output end of the second NOR gate is connected with the first input end of the third NOR gate; the output end of the third NOR gate is connected with the first input end of the fourth NOR gate; the output end of the fourth nor gate is respectively connected with the input end of the second inverter and the second input end of the third nor gate; and the output end of the second inverter is used as the second output end of the dynamic pulse generating circuit.

6. The circuit of claim 5,

when the third connection point is at a high level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at a high level;

when the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output end of the dynamic pulse generating circuit is the same as the last state;

when the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at an effective high level;

when the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is at an invalid low level.

7. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit, and a controlled current source;

the first input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the falling edge pulse generating circuit is used as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the delay circuit;

the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the rising edge pulse generating circuit;

and the output end of the rising edge pulse generating circuit is used as a first output end of the dynamic pulse generating circuit.

8. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source;

the first input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the first delay circuit; the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the second delay circuit;

the output end of the first delay circuit is connected with the input end of the first controlled current source, and the output end of the first controlled current source is connected with the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected with the input end of the second controlled current source, and the output end of the second controlled current source is connected with the second input end of the rising edge pulse generating circuit.

9. The circuit according to any one of claims 4 to 7,

the rising edge pulse generating circuit comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate, and when the rising edge pulse generating circuit comprises one input end, the input end of the third inverter is used as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit comprises two input ends, the two input ends of the third inverter are respectively used as a first input end and a second input end of the rising edge pulse generating circuit; the output end of the third inverter is connected with the input end of the fourth inverter and the second input end of the fifth nor gate respectively, the output end of the fourth inverter is connected with the anode of the first capacitor and the input end of the fifth inverter respectively, the cathode of the first capacitor is grounded, the output end of the fifth inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the fifth nor gate, and the output end of the fifth nor gate is used as the output end of the rising edge pulse generating circuit;

when the falling edge pulse generating circuit comprises one input end, the input end of the seventh inverter is used as the input end of the falling edge pulse generating circuit, and the input end of the falling edge pulse generating circuit is connected with the second input end of the sixth NOR gate; when the falling edge pulse generating circuit comprises two input ends, the two input ends of the seventh inverter are respectively used as a first input end and a second input end of the falling edge pulse generating circuit, and the first input end of the falling edge pulse generating circuit is connected with the second input end of the sixth nor gate; an output end of the seventh inverter is connected with an anode of the second capacitor and an input end of the eighth inverter respectively, a cathode of the second capacitor is grounded, an output end of the eighth inverter is connected with an input end of the ninth inverter, an output end of the ninth inverter is connected with a first input end of the sixth nor gate, and an output end of the sixth nor gate is used as an output end of the falling edge pulse generating circuit;

the delay circuit comprises a tenth inverter, an eleventh inverter and a third capacitor, wherein the input end of the tenth inverter is used as the input end of the delay circuit, the output end of the tenth inverter is respectively connected with the anode of the third capacitor and the input end of the eleventh inverter, the cathode of the third capacitor is grounded, and the output end of the eleventh inverter is used as the output end of the delay circuit;

when the dynamic pulse generating circuit further comprises the controlled current source, the controlled current source comprises a current source and a PMOS (P-channel metal oxide semiconductor) tube, the current source is connected between a power supply and a source stage of the PMOS tube, a grid electrode of the PMOS tube is used as an input end of the controlled current source, and a drain electrode of the PMOS tube is used as an output end of the controlled current source.

10. According toA circuit as claimed in any one of claims 4 to 7, characterized in that the delay value of the delay circuit is according to the formula t_P+（ΔV_S×R_L×C_DS) (VB-Vth), where VB is the high side power supply and R is_LIs a load resistance of the high voltage level shift circuit, C_DSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and DeltaV_SIs the variation of the voltage of the floating ground on the high-voltage side, t_PThe delay time of the LDMOS to the high-side output terminal.

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