CN114005748A

CN114005748A - Surface planarization method of semiconductor device

Info

Publication number: CN114005748A
Application number: CN202111267168.5A
Authority: CN
Inventors: 卜毅; 罗湘; 曾琪; 曾凯; 何逸涛; 冯宇
Original assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Current assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-02-01

Abstract

The invention relates to a surface planarization method of a semiconductor device, which comprises the following steps of depositing an oxide layer and silicon nitride on a silicon substrate; oxidizing the opening region to form a terminal region oxide layer; depositing a hard mask layer; photoetching is carried out, and then the hard mask layer is etched; using the hard mask layer as an etching barrier layer to etch the active region groove; removing the damaged layer in the trench, and then growing a gate oxide layer; depositing polycrystalline silicon on the surface, and filling all the grooves with the polycrystalline silicon; performing CMP grinding to realize wafer surface planarization; synchronously etching the silicon nitride and the oxide layer, and staying on the oxide layer of the cellular area; etching the polysilicon and the oxide layer which are higher than the silicon plane in the groove of the cellular area, and staying on the surface of the silicon substrate to realize planarization; the method avoids polysilicon residue in the terminal area, does not need to introduce an extra process to remove the hard mask layer, has simple process, can accurately realize the capture of the end point signal, realizes the planarization effect and ensures the uniformity of the product.

Description

Surface planarization method of semiconductor device

Technical Field

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a surface planarization method of a semiconductor device.

Background

In the existing submicron fine trench power device process, a step is formed after an oxide layer of a terminal area is generated as shown in fig. 1, and then after polysilicon deposition, the step is shown in fig. 2; as shown in fig. 3, a CMP polishing process is performed on polysilicon, and then a CMP polishing process is performed on an oxide layer in a terminal area, so as to finally achieve global planarization of a wafer and prepare for a subsequent small line width process.

The technical schemes which are close to the invention are as follows:

(1) application No.: CN201710733237.4 discloses a method for manufacturing a three-dimensional memory, which adopts dry etching and comprises: etching the top polysilicon layer to stay on the nitride; the hard mask SiN layer is then etched to rest on the oxide. By using dry etching, the use of CMP is reduced.

Application No.: CN201410459207.5 discloses a method for manufacturing a super junction semiconductor device, wherein a deep groove is formed on the surface of a wafer by etching; filling P-type monocrystalline silicon in the deep trench; and removing the P-type polysilicon on the surface of the hard mask layer by CMP, and performing P-type impurity injection by taking the residual hard mask layer as a mask to form a P-type layer.

Application No.: CN201210496251.4 discloses a super-junction epitaxial CMP process method, which is to directly complete the processes of trench etching and trench epitaxial growth without etching back after the polysilicon trench gate is manufactured, and then to complete the CMP process after the epitaxial growth is finished.

Application No.: CN201710761488.3 discloses a CMP method for interlayer insulating oxide layer of 3D NAND core region, comprising: providing a substrate; depositing a NO stack on a substrate; depositing a SiON layer on the NO laminated layer and carrying out ISSG treatment; depositing an oxide layer on the SiON layer treated by the ISSG; etching the step structure to complete the core region; depositing an interlayer insulating oxide layer in the core region, wherein the interlayer insulating oxide layer at least fills the peripheral region of the step structure; and performing CMP treatment on the substrate structure deposited with the core region interlayer insulating oxide layer, wherein the SiON layer treated by ISSG is used as a grinding stop layer. By using the SiON layer processed by ISSG as the grinding stop layer, the grinding selection ratio of the grinding stop layer is improved, the thickness of the mask stop layer is reduced, and the step height after the grinding stop layer is removed is further reduced. The CMP method can improve the uniformity of the oxidation thickness of the channel hole plug and reduce the variation of the characteristics of the memory device.

However, the above method does not treat the polysilicon residue in the termination region and does not solve the planarization problem of the termination region.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a surface planarization method of a semiconductor device, which avoids polysilicon residue in a terminal area, does not need to introduce an extra process to remove a hard mask layer, has a simple process, can accurately realize end point signal capture, realizes a planarization effect, and can ensure the uniformity of products in mass production.

The invention relates to a method for planarizing the surface of a semiconductor device, comprising the following steps,

1) depositing an oxide layer and silicon nitride on a silicon substrate;

2) oxidizing the opening region to form a terminal region oxide layer;

3) depositing a hard mask layer;

4) photoetching is carried out, then the hard mask layer is etched, and due to the material characteristics of the hard mask layer, the hard grinding side faces are kept consistent when the groove etching is carried out, so that the CD (compact disc) of the groove can be accurately controlled;

5) using the hard mask layer as an etching barrier layer to etch the active region groove;

6) removing the damaged layer in the trench, and then growing a gate oxide layer;

7) depositing polycrystalline silicon on the surface, and filling all the grooves with the polycrystalline silicon;

8) performing CMP grinding, namely grinding the surface polysilicon, and then grinding the hard mask layer and the oxide layer at the LOCOS position to realize the surface planarization of the wafer;

9) synchronously etching the silicon nitride and the oxide layer, and staying on the oxide layer of the cellular area;

10) and etching the polycrystalline silicon and the oxide layer which are higher than the silicon plane in the groove of the cellular area, and staying on the surface of the silicon substrate to finally realize planarization.

Preferably, the thickness of the oxide layer deposited on the silicon substrate is 270-330A (i.e., 300 + -30A), and the thickness of the silicon nitride layer is 900-1100A (i.e., 1000 + -100A).

Preferably, the termination region oxide layer is formed by a LOCOS process.

Preferably, the hard mask layer comprises two layers, wherein the bottom layer is made of silicon oxide and the surface layer is made of silicon nitride. The thickness of the hard mask layer is 6000-6800A (namely 6400 +/-400A), the stress can be reduced due to the fact that the bottom oxide layer grows thinner, the high-temperature process avoided by the growth of the thinner oxide layer is less, and the stress problem can be relieved obviously.

Preferably, the method for removing the damaged layer in the trench is dry etching, and a dry etching machine is generally used for removing the damaged layer.

Preferably, the method for synchronously etching the silicon nitride and the oxide layer is to select a substance with a similar etching speed to the silicon nitride and the oxide layer to etch the silicon nitride and the oxide layer, wherein the etching substance is generally F-based etching gas.

The invention has the beneficial effect that the invention is applicable to any semiconductor device requiring CMP and hard mask etching. In particular to a power semiconductor device, which can realize the stable mass production scheme and the surface Planarization CMP (Chemical Mechanical Planarization) process step, and the technical scheme can be directly compatible with the hard mask control groove CD technology without introducing a hard mask removing process, and finally realizes the good Planarization effect of the wafer surface.

The terminal layer oxide layer forms a bird's beak, the polycrystalline silicon of the invention is directly deposited on the hard mask oxide layer, the terminal oxide layer is raised, and the polycrystalline silicon residue is not easy to be caused at the position where the bird's beak is formed; meanwhile, the hard mask layer is added, so that the size of the groove is ensured, and the hard mask layer is removed without introducing an extra process, thereby achieving the purpose of simplifying the process.

When the terminal area oxide layer is ground, due to the existence of the silicon nitride stop layer, the terminal signal can be accurately grabbed, the planarization effect is realized, and the uniformity of products can be ensured by mass production.

The invention can realize the grinding in a mode of catching the end point through the CMP process on the basis of keeping the original process scheme, can realize large-scale mass production, simultaneously ensure the uniformity of products, and realize better compatibility to the subsequent process.

The invention integrates the groove hard mask layer to control the CD technology, realizes the accurate control of the key dimension, does not need to additionally introduce a hard mask removing process, and reduces the introduction of other process steps.

The product of the invention can be a power device and also can be in the field of integrated circuits using a CMP process.

Drawings

FIG. 1 is a schematic diagram of a prior art termination region deposited oxide layer structure.

Fig. 2 is a schematic diagram of a prior art structure for depositing polysilicon.

FIG. 3 is a schematic diagram of a prior art structure after a CMP polishing process is performed.

FIGS. 4-13 illustrate the process steps from step 1) to step 10), respectively, of the present invention.

FIG. 14 is a flow chart of the process steps of the present invention.

In the figure, 1 silicon substrate, 2 cell region oxide layers, 3 silicon nitride, 4 terminal region oxide layers, 5 hard mask layers, 6 active region trenches, 7 gate oxide layers after removal of damage layers, and 8 polysilicon.

Detailed Description

Example 1

A method for planarizing the surface of a semiconductor device includes the steps of,

step 1: as shown in fig. 4, a cell region oxide layer 2 and silicon nitride 3 are deposited on a silicon substrate 1;

step 2: as shown in fig. 5, the opening region formed by etching is oxidized to form a termination region oxide layer 4;

and 3, step 3: as shown in fig. 6, a hard mask layer 5 is deposited;

and 4, step 4: as shown in fig. 7, firstly, performing photolithography, and then etching the hard mask layer 5, the silicon nitride 3 and the cell region oxide layer 2;

and 5, step 5: as shown in fig. 8, an active region trench 6 is formed using the hard mask layer as an etching stopper;

and 6, step 6: as shown in fig. 9, removing the damaged layer in the trench by using dry etching, then performing gate oxide oxidation after removing the damaged layer to obtain a gate oxide layer 7 after removing the damaged layer;

and 7, step 7: as shown in fig. 10, polysilicon 8 is deposited on the surface of the device, and all the trenches are filled with the polysilicon;

and 8, step 8: as shown in fig. 11, CMP polishing is performed to polish the surface polysilicon, and then polish the hard mask layer and the oxide layer at LOCOS to planarize the surface of the wafer;

step 9: as shown in fig. 12, the silicon nitride and the oxide layer have similar etching selectivity and stay on the thin oxide layer in the cell region;

step 10: as shown in fig. 13, the polysilicon and the thin oxygen above the silicon plane in the trenches of the cell area are etched to stay on the surface of the silicon substrate, and finally, planarization is achieved.

The process method comprises the following steps: the oxide layer generation and filling process is unchanged, the hard mask deposition process after the original LOCOS oxide layer is added, and simultaneously, the hard mask layer etching process and the trench etching process taking the hard mask layer as a barrier layer are added. And removing the damaged layer formed on the side wall after the groove is etched by using a method with stronger chemical etching in dry etching. And (3) carrying out a planarization CMP (chemical mechanical polishing) process on the surface of the device after the deposition of the polysilicon, grinding the polysilicon firstly, then grinding the oxide layer, and stopping on the surface of the silicon nitride, wherein the CMP process can easily grab the EDP curve at the silicon nitride dielectric layer, and the final planarization is realized by using dry etching.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the spirit of the present disclosure, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments in this application as described above, which are not provided in detail for the sake of brevity.

It is intended that the one or more embodiments of the present application embrace all such alternatives, modifications and variations as fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of one or more embodiments of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A method for planarizing the surface of a semiconductor device, comprising the steps of,

1) depositing an oxide layer and silicon nitride on a silicon substrate;

2) oxidizing the opening region to form a terminal region oxide layer;

3) depositing a hard mask layer;

4) photoetching is carried out, and then the hard mask layer is etched;

2. The method as claimed in claim 1, wherein the oxide layer deposited on the silicon substrate has a thickness of 270A-330A.

3. The method as claimed in claim 1, wherein the silicon nitride deposited on the silicon substrate has a thickness of 900-1100A.

4. The method for planarizing the surface of the semiconductor device as claimed in claim 1, wherein the termination region oxide layer is formed by a LOCOS process.

5. The method of planarizing the surface of the semiconductor device as claimed in any of claims 1 to 4, wherein the hard mask layer comprises two layers, a bottom layer of silicon oxide and a top layer of silicon nitride.

6. The method as claimed in claim 5, wherein the hard mask layer has a thickness of 6000-6800A.

7. The method for planarizing the surface of the semiconductor device as claimed in any of claims 1 to 4, wherein the method for removing the damaged layer in the trench is dry etching.

8. The method for planarizing the surface of the semiconductor device as claimed in any of claims 1 to 4, wherein the silicon nitride and the oxide layer are simultaneously etched by selectively etching the silicon nitride and the oxide layer at a rate similar to each other.