CN114003365A - Fast interrupt system for RISC-V architecture - Google Patents
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Abstract
The invention discloses a quick interrupt system for RISC-V architecture, belonging to the technical field of processor interrupt processing. The invention includes an interrupt controller and a RISC-V processor system adopting Harvard architecture, the interrupt controller is used for receiving interrupt source signals and sending interrupt type codes and interrupt request signals to a processor core of the RISC-V processor system according to a vector interrupt mode of a CLIC interrupt mechanism, in the RISC-V processor system, after the processor core receives the interrupt request signals from the interrupt controller, the on-site protection and the vector table address fetching are carried out in parallel through hardware. Meanwhile, the invention adopts a hardware shielding circuit to realize the shielding of the global interrupt enabling signal, so that the processor does not need to close the global interrupt enabling when entering the interrupt, and does not need to open the global interrupt enabling again by software. The design of the whole interrupt system of the invention does not need the overhead of software in the aspect of interrupt flow, and can automatically support the on-site protection, recovery and interrupt nesting.
Description
Technical Field
The invention belongs to the technical field of processor interrupt processing, and particularly relates to a rapid interrupt technology for a RISC-V architecture.
Background
Interrupt mechanisms are one of the basic mechanisms in modern computer systems, which is the reaction of a CPU to some event occurring at some point in the system. The event that causes the Interrupt is called an Interrupt Source (Interrupt Source). Typically, the interrupt source is primarily from the peripheral hardware device. The Request from the Interrupt source to the CPU is called an Interrupt Request (Interrupt Request). After receiving an Interrupt request from an Interrupt source, the CPU suspends the currently executing program and processes a sudden event, i.e., an Interrupt Service Routine (ISR).
When the interruption occurs, the point at which the program is paused is called a Breakpoint (Breakpoint), and after the CPU executes the interruption service function, the CPU needs to return to the Breakpoint to continue executing the program. In order to enable the CPU to smoothly return to the breakpoint, a protection field, called a protection field, is required before the interrupt service function is executed. Similarly, after the CPU has processed the interrupt service function, the program site before the interrupt occurs needs to be restored, which is called a restoration site. The time spent from the interruption of the interrupt source to the formal processing of the specific contents in the interrupt service function by the CPU is referred to as the interrupt response time.
To address the low Interrupt response time and Interrupt nesting requirements of embedded applications, RISC-V authorities supplement the Core-Local Interrupt Controller (Core-Local Interrupt Controller) in the standard architecture. The CLIC may be compatible with and replace a previously existing CLINT Interrupt mechanism (Core-Local Interrupt). Compared with the CLINT interrupt mechanism, the CLIC interrupt mechanism improves the interrupt processing performance and reduces the interrupt response time.
At present, an embedded RISC-V processor mainly adopts a scheme of a CLIC interrupt mechanism and software operation to complete an interrupt processing process, and uses CLIC mode vector interrupt to achieve higher interrupt response speed. The full interrupt response time contains both hardware overhead and software overhead. Firstly, an interrupt source sends an interrupt signal to an interrupt controller, and after arbitration, the interrupt controller sends an interrupt ID and an interrupt request signal which meet the conditions (the interrupt enable of the interrupt is opened, the interrupt level is the highest, and if interrupt preemption occurs, the interrupt level of the interrupt is required to be higher than the current interrupt level) to a CPU. After receiving the interrupt request signal, the CPU will refresh the relevant CSR register according to the CLIC interrupt mechanism, at the same time, in the vector interrupt mode, according to the interrupt ID, read the corresponding interrupt service function entry from the interrupt vector table, and jump to the destination address. This portion is the hardware overhead of interrupt response time. Secondly, before executing the effective codes in the interrupt processing function, the CPU needs to execute a series of software programs to support interrupt return and nesting, wherein the system mainly comprises two parts, namely field protection, including the storage of general registers, the storage of an mcause register and a mepc register, and the restart of the global interrupt enable by using software instructions. This portion is the software overhead of interrupt response time.
In the vector interrupt mode of the RISC-V architecture CLIC interrupt mechanism, the interrupt response flow includes two parts, namely hardware overhead and software overhead, so that the interrupt response time is long, and how to shorten the interrupt response time is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention aims to solve the problem of overlong response time of a vector interrupt mode of a RISC-V architecture CLIC interrupt mechanism in the prior art, and provides a quick interrupt system, a processor and a computer device for the RISC-V architecture.
The invention adopts the following specific technical scheme:
the invention provides a rapid interrupt system for RISC-V Architecture, which comprises an interrupt controller and a RISC-V processor system adopting Harvard Architecture (Harvard Architecture);
the interrupt controller is used for receiving an interrupt source signal and sending an interrupt type code and an interrupt request signal to a processor core of the RISC-V processor system according to a vector interrupt mode of a CLIC interrupt mechanism;
in the RISC-V processor system, after the processor kernel receives the interrupt request signal from the interrupt controller, the on-site protection and the vector table address fetching are carried out in parallel through hardware, wherein, when the on-site protection is carried out, the data channel is accessed through the bus, the register to be protected is stored into the data memory through the register stack according to the stack pointer, and when the vector table address fetching is carried out, the instruction channel is accessed through the bus, and the interrupt service function entry address is read from the interrupt vector table stored in the program memory according to the received interrupt type code; after the register is pushed, the processor core jumps to an interrupt service function inlet according to the read address; after the interrupt processing is finished and the mret instruction is decoded, the processor kernel accesses the data channel through the bus again according to the stack pointer and reads back the register to be protected from the data memory through register popping, and the field recovery is completed;
and a shielding circuit is arranged in the interrupt controller, and the shielding circuit shields the global interrupt enable signal by shielding an MIE domain in the mstatus register, so that the global interrupt enable cannot be closed when the kernel of the processor enters the interrupt.
Preferably, the interrupt system is provided with an interrupt tail chain, and when the processor core finishes executing the current interrupt handler, if there is a pending interrupt waiting response, the stack-out and stack-in of the register are skipped, and the pending interrupt is directly processed.
Preferably, the interrupt controller includes an interrupt request generator, an interrupt preemption support unit, and an interrupt vector table, wherein the interrupt request generator is configured to perform priority arbitration on an interrupt source signal, and send an interrupt type code and an interrupt request signal to the processor core according to the priority obtained by the arbitration, and the interrupt preemption support unit is configured to update a mcp register, an mcause register, and an mstatus register that are necessary when an interrupt occurs.
Preferably, the registers to be protected comprise general registers, mcause registers and mepc registers.
Preferably, the effective masking time of the masking circuit is the period from the time when the processor core receives the interrupt request signal to the end of the register stacking, and the period from the time when the mret instruction is detected to the end of the register stacking
Preferably, the data storage is a RAM.
Preferably, the program memory is a ROM.
Preferably, in the processor core, the entry address of the target interrupt service function in the vector table is calculated by the interrupt vector table base address and the interrupt type code provided by the mtvt register.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts a mechanism of protecting the site and recovering the site by hardware, can reduce the interrupt response time, and can reduce the storage time of an mcause register and a mepc register from 2 cycles to 1 cycle in a Harvard storage system architecture processor system.
2. In the invention, the stack saving register and the vector table address fetching are realized through hardware, and the parallel execution can be realized in a Harvard storage system architecture processor system, so that the interrupt response time is further reduced compared with the two-step serial execution.
3. The invention adopts the hardware shielding circuit to realize the shielding of the global interrupt enabling signal, so that the processor does not need to close the global interrupt enabling when entering the interrupt, and does not need to open the global interrupt enabling again by software.
4. The design of the whole interrupt system of the invention does not need the overhead of software in the aspect of interrupt flow, and can automatically support the on-site protection, recovery and interrupt nesting.
Drawings
FIG. 1 is an interrupt system architecture;
FIG. 2 is a diagram of the interrupt request generator logic structure;
FIG. 3 is a diagram depicting register update of an interrupt preemption support unit;
FIG. 4 is a CLIC vector mode interrupt vector table;
FIG. 5 is a flow diagram of hardware push (i.e., push) protection and pop restore register execution;
FIG. 6 is a circuit diagram of a global interrupt enable mask circuit prior to ISR execution;
FIG. 7 is a circuit diagram of a global interrupt enable mask circuit after ISR execution;
FIG. 8 is a timing diagram of an interrupt system entering an interrupt;
FIG. 9 is a timing diagram of interrupt tail chain behavior.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The technical characteristics in the embodiments of the present invention can be combined correspondingly without mutual conflict.
In the conventional CLIC interrupt mechanism, the interrupt response flow includes two parts, namely hardware overhead and software overhead. The software part needs to complete with a csr instruction and a sw instruction for saving the interrupt field and enabling the global interrupt, and compared with the operation of a register directly inside a processor, the interrupt response time is increased. In the interrupt response flow, the hardware overhead part of the CPU mainly accesses the instruction channel, the software overhead part mainly accesses the data channel, and the two parts of operations are theoretically independent from each other. Therefore, for the processor system with the harvard architecture, if the part of the software overhead in the interrupt response flow is also realized by hardware, so that the processor fetches the address from the interrupt vector table and stores the address and the register at the same time, the interrupt response time can be further shortened, the interrupt response speed can be improved, the software operation in the interrupt service function can be reduced, and the stable interrupt response time can be realized.
Based on the above inventive concept, the present invention provides a fast interrupt system for RISC-V architecture, which includes an interrupt controller and a RISC-V processor system adopting Harvard architecture.
The interrupt controller is used for receiving an interrupt source signal and sending an interrupt type code (namely interrupt ID) and an interrupt request signal to a processor core of the RISC-V processor system according to a vector interrupt mode of a CLIC interrupt mechanism. The RISC-V processor system of the invention comprises a RISC-V processor, a data memory and a program memory, wherein the RISC-V processor can simultaneously access a data channel and an instruction channel through a bus so as to respectively access the data memory and the program memory.
As a specific implementation form of the present invention, the interrupt controller includes an interrupt request generator, an interrupt preemption support unit, and an interrupt vector table, where the interrupt request generator is configured to perform priority arbitration on an interrupt source signal, and send an interrupt type code and an interrupt request signal to a processor core according to a priority obtained by the arbitration, and the interrupt preemption support unit is configured to update three state registers necessary for interrupt occurrence, and each of the three state registers is: a mcp register, an mcause register, and an mstatus register.
In the RISC-V processor system, after the processor kernel receives the interrupt request signal from the interrupt controller, the on-site protection and the vector table address fetching are carried out in parallel through hardware, wherein, when carrying out the on-site protection, the data channel is accessed through the bus and the register to be protected is stored into the data memory (adopting the RAM) through the register stacking (namely the push stack) according to the stack pointer (sp), and when carrying out the vector table address fetching, the instruction channel is accessed through the bus and the interrupt service function entry address is read from the interrupt vector table stored in the program memory (adopting the ROM) according to the received interrupt type code; after the register is pushed, the processor core jumps to an interrupt service function inlet according to the read address; after the interrupt processing is finished and the mret instruction is decoded, the processor kernel accesses the data channel through the bus again according to the stack pointer (sp) and reads back the register to be protected from the data memory through register unstacking, and the field recovery is completed. It should be noted that the field protection of the register and the address fetching operation of the interrupt vector table are implemented by hardware, and no software overhead is required in terms of interrupt flow.
After receiving the interrupt request signal, the processor core refreshes the relevant register according to the CLIC interrupt mechanism, so that the register to be protected needs to be determined according to the actual situation. Generally, registers to be protected include three classes, general purpose registers, mcause registers, and mepc registers, where the general purpose registers specifically select general purpose registers that will be flushed in the CLIC interrupt mechanism.
In order to prevent the information of the related register of the original interrupt from being covered by other interrupts before the interrupt state is saved, the invention also arranges an MIE hardware shielding circuit in the interrupt controller, and the shielding circuit shields the global interrupt enabling signal by shielding the MIE domain in the mstatus register, thereby preventing the global interrupt enabling from being closed when the processor kernel enters the interrupt. Generally, the mask effective time of the mask circuit is the period from the time the processor core receives the interrupt request signal to the end of the register pop, and the period from the time the mret instruction is detected to the end of the register pop. The shielding circuit may be implemented using conventional electronic circuitry, so long as the corresponding function is achieved. After the shielding circuit shields the two periods, the whole interrupt process does not need software to reset mstatus.
To further illustrate the specific implementation of the above-described fast interrupt system of the present invention, a preferred embodiment will be described below to facilitate better understanding of the present invention for those skilled in the art.
In the preferred embodiment, the system architecture for a RISC-V architecture fast interrupt system is shown in FIG. 1, which is based on a generic CLIC interrupt mechanism and extends some interrupt-related control within the processor. The entire interrupt system includes a RISC-V processor system employing a Harvard architecture and a CLIC interrupt controller. The CLIC interrupt controller is responsible for sampling and arbitrating the interrupt source signal and sending the results to the processor cores in the RISC-V processor system. The processor core in the RISC-V processor system is responsible for hardware stack pressing, stack pulling and vector table address fetching. Because the whole system adopts a Harvard architecture, the processor simultaneously accesses the instruction channel and the data channel through the bus by the internal instruction fetching module and the memory access module.
In the preferred embodiment, the CLIC interrupt controller includes three parts, an interrupt request generator, an interrupt preemption support unit, and an interrupt vector table. Fig. 2 is a logical structural diagram of an interrupt request generator. It is responsible for 32 external interrupt sources local to the processor and sends the interrupt signal arbitration result to the RISC-V processor core. Each interrupt source has Interrupt Pending (IP), Interrupt Enable (IE) and Interrupt Level (IL) registers. They are both read-write registers. When the module detects the rising edge of the interrupt signal, the interrupt pending register is set to 1. When the interrupted interrupt service function is executed, the interrupt pending register is cleared. In addition, an interrupt enable register and an interrupt level register are used to configure the interrupt enable and interrupt level, respectively. All interrupt signals which are waiting for response and are enabled arbitrate the interrupt signal with the highest grade through a five-grade comparator, and if the interrupt grade of the interrupt is larger than a threshold (mth) register, the interrupt request signal and the interrupt ID are sent to the RISC-V kernel. The threshold register may be configured to mask interrupts. The interrupt preemption support unit is primarily to update the three Control State Registers (CSRs) necessary for interrupt generation, as described in detail in fig. 3. Wherein the MPIE field of the mcause register does not need to be updated. The MIE field of the mstatus register does not need to be updated in other CSR registers. The interrupt vector table design for CLIC vector mode is shown in FIG. 4. The CLIC vector mode provides the ability to use an interrupt vector table. The processor obtains the entry address of the 32-bit interrupt service function from the embedded vector table in the memory, and the position of the target interrupt in the vector table is calculated mainly through the vector table base address and the interrupt ID number provided by the mtvt register. The processor then sets the PC to the jump address.
In the preferred embodiment, the specific interrupt control design for the processor core is as follows:
A. hardware push protection and pop restore registers:
in order to reduce the software overhead in the interrupt response process, in this embodiment, a mechanism for hardware stack entry protection and stack exit recovery registers applied to the interrupt system is designed, which is used to protect general purpose registers used in ISRs, and a mcp register and an mcause register. Taking the example of a 32-bit E instruction set processor, there are 10 calller attribute registers (ra, t0, t1, t2, a0, a1, a2, a3, a4, a5) in the 16 general purpose registers, which are not reserved throughout the call. Thus, when the processor receives an interrupt request, the design automatically pushes 12 registers to the stack memory and then pops out in order when the ISR completes. The execution flow of the hardware push and pull is shown in fig. 5. During the push, the Stack Pointer (SP) is decremented by 48, preparing enough space for the 12 registers in the stack memory. Then, the ra, t0, t1, t2, a0, a1, a2, a3, a4, a5 registers are pushed onto the stack from bottom to top through the data path of the bus. In the process of popping, the processor writes data in the stack memory back to a5, a4, a3, a2, a1, a0, t2, t1, t0 and ra registers from top to bottom in sequence. Finally SP plus 48 is restored to the original position. However, the above 10 attribute registers are only an example and are not limiting, and in other embodiments, the registers that need to be stacked need to be determined according to the registers that the actual processor flushes in the interrupt mechanism.
B. Global interrupt enabled hardware mask design:
in the embodiment, the global interrupt enable bit is subjected to hardware shielding design, software reset mstatus. The design starts masking the MIE domain upon receiving an interrupt request, and once the hardware push protection register is completed, the masking is released, and the circuit that can be used in this embodiment is shown in FIG. 6. In addition, after the execution of the interrupt service function is finished, when an mret instruction is detected, the mask of the MIE domain is started, and once the hardware pop recovery register is finished, the mask is released, and a hardware mask circuit which can be adopted in the embodiment is shown in fig. 7. The effect of the hardware mask design is to prevent preemption by other interrupts before the interrupt state is saved, resulting in the information of the original interrupt related registers being overwritten. The MIE and MPIE fields of the mstatus register do not require hardware operations under other conditions of the present system.
C. The hardware stack protection register and the vector table address fetch are executed in parallel:
in this embodiment, when the processor receives an interrupt request, the hardware push protection register and the processor start to fetch an address from the interrupt vector table at the same time. After the hardware stack register is finished, the processor sets the PC as the address acquired in the interrupt vector table and jumps to the ISR entry. The interrupt entry timing of the present interrupt system is shown in fig. 8.
D. Designing an interrupted tail chain:
in addition, in this embodiment, an interrupt tail chain design may also be added to the interrupt system. When the processor finishes executing the current interrupt processing program, if the suspended interrupt waits for response, the processor does not restore the registers from the stack immediately and then pushes the registers into the stack again, but skips the steps of popping and pushing the stack and directly processes the suspended interrupt. Thus, the time interval between two interrupt handlers is greatly reduced. The behavior of a tail-chain interrupt in this system is shown in fig. 9.
The above-described embodiments are merely preferred embodiments of the present invention, which should not be construed as limiting the invention. Various changes and modifications may be made by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present invention. Therefore, the technical scheme obtained by adopting the mode of equivalent replacement or equivalent transformation is within the protection scope of the invention.
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| CN115858020A (en) * | 2023-02-24 | 2023-03-28 | 北京国科环宇科技股份有限公司 | Interrupt processing method, device, equipment and processor |
| CN117251393A (en) * | 2023-11-17 | 2023-12-19 | 北京智芯微电子科技有限公司 | Processor interrupt response method, device, chip, computer equipment and media |
| CN118819638A (en) * | 2024-09-18 | 2024-10-22 | 山东云海国创云计算装备产业创新中心有限公司 | Interrupt processing system, method, readable storage medium and program product |
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