CN114003289B - Application program running method, computing device and storage medium - Google Patents
Application program running method, computing device and storage medium Download PDFInfo
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- CN114003289B CN114003289B CN202111287804.0A CN202111287804A CN114003289B CN 114003289 B CN114003289 B CN 114003289B CN 202111287804 A CN202111287804 A CN 202111287804A CN 114003289 B CN114003289 B CN 114003289B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
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Abstract
The invention discloses an application program running method, a computing device and a storage medium, and the method comprises the following steps: acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first access instruction, and when the processor executes the first access instruction, the processor generates a data access exception message because the memory address of the first access instruction cannot normally execute the first access instruction; acquiring a second access instruction from an instruction storage section of the internal memory, wherein the second access instruction is suitable for storing or reading data to be stored or read by the first access instruction, and the processor does not generate a data access exception message when executing the second access instruction; according to the acquired second memory access instruction, replacing a first memory access instruction in the first instruction stream of the application to obtain a second instruction stream; and submitting the second instruction stream to the processor, and executing the second instruction stream through the processor to run the application. The invention saves the time of carrying out exception handling every time and improves the operation efficiency of the application.
Description
Technical Field
The present invention relates to the field of operating systems, and in particular, to an application program running method, a computing device, and a storage medium.
Background
With the continued development of computer technology, more and more applications are being developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is also more and more important, and the operation speed of the key application program is directly influenced. When data is stored, special storage conditions often occur, and when the processor is applied to accessing the stored data, the processor does not support special access instructions for the data, the situation that errors occur can occur, and the processor cannot directly process the access instructions to read the data.
In the prior art, in order to enable the application to read data normally, a method of changing the data storage mode is adopted, so that an instruction for accessing the data is changed into a normal instruction, and a processor can execute the data reading.
For this reason, a new application running method is required.
Disclosure of Invention
To this end, the present invention provides an application running method in an effort to solve or at least alleviate the above-presented problems.
According to one aspect of the present invention, there is provided an application program running method adapted to be executed in a computing device including an internal memory and an external memory, and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory with a storage address in the storage space, the method comprising the steps of: acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first access instruction, and when the processor executes the first access instruction, the processor generates a data access exception message because the memory address of the first access instruction cannot normally execute the first access instruction; acquiring a second access instruction from an instruction storage section of the internal memory, wherein the second access instruction is suitable for storing or reading data to be stored or read by the first access instruction, and the processor does not generate a data access exception message when executing the second access instruction; according to the acquired second memory access instruction, replacing a first memory access instruction in the first instruction stream of the application to obtain a second instruction stream; and submitting the second instruction stream to the processor, and executing the second instruction stream through the processor to run the application.
Optionally, in the method according to the present invention, the computing device further includes an external memory, and the external memory stores an application file, and the method further includes the steps of: generating an executable file of the application program according to the application file; loading an executable file of the application program into an internal memory; and running the application according to the executable file stored in the internal memory.
Optionally, in the method according to the invention, the executable file comprises a code section, and running the application according to the executable file stored in the internal memory comprises the steps of: a first instruction stream of the application is obtained from the code segment.
Optionally, in the method according to the present invention, further comprising: when the second memory access instruction is not stored in the internal memory, submitting a first instruction stream of the application to the processor, wherein the first instruction stream comprises a first memory access instruction suitable for accessing data in the internal memory; when the processor cannot normally execute the first access instruction due to the memory address of the first access instruction, generating a second access instruction according to the data access exception message generated by the processor, and executing the second access instruction by the processor to store or read data in the internal memory; and setting an instruction storage section in a code section of the executable file of the application, and storing a second memory access instruction in the instruction storage section so as to run the application, and loading the second memory access instruction into the internal memory from the instruction storage section when the code section of the executable file is loaded.
Optionally, in the method according to the present invention, replacing the first memory instruction in the first instruction stream of the application according to the acquired second memory instruction, and obtaining the second instruction stream includes the steps of: judging whether a second access instruction which is not read exists in the instruction storage section; if the second access instruction which is not read exists, the second access instruction is read, and the first access instruction in the first instruction stream of the application is replaced.
Optionally, in the method according to the present invention, the first memory instruction comprises a non-demarcation memory instruction and the data memory exception message comprises a non-demarcation data memory exception message.
Optionally, in the method according to the invention, the second memory instruction comprises a store-to-world instruction.
Optionally, in the method according to the present invention, generating the second memory access instruction according to the processor-generated data memory access exception message includes the steps of: generating a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, wherein the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address; and taking the first half storage instruction and the second half storage instruction as second storage instructions.
Optionally, in the method according to the present invention, generating the second memory access instruction according to the processor-generated data memory access exception message includes the steps of: calculating a storage address and an offset according to a first target address of a first access instruction; generating a second target address according to the storage address and the offset; and generating a second storage instruction according to the second target address.
According to another aspect of the present invention, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing an application program execution method according to the present invention.
According to yet another aspect of the present invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method of an application program execution method according to the present invention.
The application program running method of the present invention is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory, and one or more applications are run, the storage area of the internal memory is mapped into a storage space, and the applications read and write data in the internal memory by using storage addresses in the storage space, the method comprises the steps of: firstly, acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first access instruction, and when the processor executes the first access instruction, the processor generates a data access exception message because the memory address of the first access instruction cannot normally execute the first access instruction; then, a second access instruction is obtained from an instruction storage section of the internal memory, the second access instruction is suitable for storing or reading data to be stored or read by the first access instruction, and a processor does not generate a data access abnormal message when executing the second access instruction; and then, according to the acquired second memory access instruction, replacing the first memory access instruction in the first instruction stream of the application to obtain a second instruction stream. Finally, the second instruction stream is submitted to the processor for execution of the application. According to the invention, the second memory access instruction which does not generate the data access abnormal information is obtained from the internal memory, and the first memory instruction in the instruction stream is replaced, so that the second instruction stream which does not generate the data access abnormal information and can be normally executed by the processor can be obtained, the time for carrying out abnormal processing each time is saved, and the running efficiency of the application is improved.
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To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which set forth the various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to fall within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Like reference numerals generally refer to like parts or elements throughout the present disclosure.
FIG. 1 illustrates a schematic diagram of the structure of an external memory and an internal memory according to an exemplary embodiment of the present invention;
FIG. 2 illustrates a block diagram of a computing device 200 according to an exemplary embodiment of the invention;
FIG. 3 illustrates a flow diagram of an application running method 300 according to an exemplary embodiment of the invention; and
FIG. 4 illustrates a schematic diagram of inserting a second memory instruction into a code section according to an exemplary embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.
Fig. 1 illustrates a schematic structure of an external memory and an internal memory according to an exemplary embodiment of the present invention. As shown in FIG. 1, computing device 200 includes internal memory 230 and external memory 210, and is running an operating system 220. The invention is not limited in the nature of the operating system 220. One or more applications (not shown) are running based on operating system 220. The external memory 210 stores therein an application file 211. The manner in which the application files 211 are stored in the external memory 210 shown in fig. 1 is merely exemplary, and the present invention does not limit the number of application files stored in the external memory 210.
The application file 211 may be implemented as an application file of any kind of application program, and the kind of application program and the type of application file are not limited in the present invention. According to one embodiment of the invention, the application file 211 is adapted to be compiled, assembled, linked, etc. by the operating system 220 to obtain an executable file of the application program, which is finally loaded into the internal memory 230.
When storing an executable file of an application, the internal memory 230 allocates memory space for the executable file. The memory space allocated by the internal memory 230 includes a plurality of different memory segments, and the executable files are stored in the internal memory 230 in the form of the memory segments. The internal memory 230 divides the memory space into memory sections including a heap section, a stack section, a code section, an initialized data section, and an uninitialized data section. The memory segments are partitioned in internal storage 230 by the operating system at the time the process is created. Wherein the code segment is adapted to store instructions of an application program.
The specific structure of computing device 200 in fig. 1 is shown in fig. 2. FIG. 2 illustrates a block diagram of a computing device 200 according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.
Depending on the desired configuration, the processor 204 may be any type of processing including, but not limited to: a microprocessor (μp), a microcontroller (μc), a digital information processor (DSP), or any combination thereof. Processor 204 may include one or more levels of cache, such as a first level cache 210 and a second level cache 212, a processor core 214, and registers 216. The example processor core 214 may include an Arithmetic Logic Unit (ALU), a Floating Point Unit (FPU), a digital signal processing core (DSP core), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations, the memory controller 218 may be an internal part of the processor 204.
Depending on the desired configuration, system memory 206 may be any type of memory including, but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some implementations, the program 222 may be arranged to execute instructions 223 of the method 300 according to the present invention on an operating system by the one or more processors 204 using the program data 228.
Computing device 200 may also include a storage interface bus 234. Storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to base configuration 202 via bus/interface controller 230. At least a portion of operating system 220, programs 222, and data 224 may be stored on removable storage 236 and/or non-removable storage 238, and when the program 222 is powered up or is to be executed by the computing device 200, loaded into the system memory 206 via storage interface bus 234 and executed by the one or more processors 204.
Computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to basic configuration 202 via bus/interface controller 230. The example output device 242 includes a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices, such as a display or speakers, via one or more a/V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 258. The example communication device 246 may include a network controller 260 that may be arranged to communicate with one or more other computing devices 262 over a network communication link via one or more communication ports 264.
The network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media in a modulated data signal, such as a carrier wave or other transport mechanism. A "modulated data signal" may be a signal that has one or more of its data set or changed in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or special purpose network, and wireless media such as acoustic, radio Frequency (RF), microwave, infrared (IR) or other wireless media. The term computer readable media as used herein may include both storage media and communication media.
In computing device 200 according to the present invention, program 222 includes program instructions of application execution method 300 that may instruct processor 204 to perform some of the steps of application execution method 300 that are executed in computing device 200 according to the present invention, so that portions of computing device 200 execute the application by executing application execution method 300 according to the present invention.
Computing device 200 may be implemented as a server, such as file server 240, database 250, a server, an application server, etc., such as a Personal Digital Assistant (PDA), a wireless web-browsing device, an application-specific device, or a hybrid device that may include any of the above functions. May be implemented as a personal computer including desktop and notebook computer configurations, and in some embodiments, computing device 200 is configured to apply method 300.
Fig. 3 shows a flow diagram of an application running method 300 according to an exemplary embodiment of the invention. The application running method 300 of the present invention is adapted to be executed in a computing device and is further adapted to be executed in a computing device 100 as shown in fig. 1. The computing device includes a processor (not shown) and an internal memory 230, and runs one or more applications, the memory area of the internal memory 230 is mapped to a memory space, and the applications read and write data in the internal memory 230 with memory addresses in the memory space. As shown in fig. 3, the instruction execution method 300 starts in step S310, a first instruction stream of an application is obtained, the first instruction stream includes a first memory access instruction, and when the processor executes the first memory access instruction, a data memory access exception message is generated because a memory address of the first memory access instruction cannot normally execute the first memory access instruction. The first access instructions include first access instructions and first store instructions, respectively, adapted to read and store data in the internal memory 230. The first memory access instruction includes a non-demarcation memory access instruction. The first access instruction includes an out-of-bounds access instruction and the first store instruction includes an out-of-bounds store instruction. The data access exception message includes a data access exception message and a data storage exception message. When the first access instruction is a first access instruction, the data access exception message is a data access exception message; when the first access instruction is a first storage instruction, the data access exception message is a data storage exception message.
According to one embodiment of the present invention, the computing device further includes an external memory 210, where the external memory 210 stores an application file 211, and the first instruction stream of the application is obtained by:
First, an executable file of an application program is generated from the application file 211. The application files 211 stored in the external memory 210 cannot be directly loaded into the internal memory 230 without preprocessing. According to one embodiment of the invention, the application file 211 requires steps such as compiling, assembling, and linking it by the operating system 130 to obtain an executable file of the application program. The invention is not limited by the steps and methods by which the operating system 130 pre-processes the application file 211.
The executable file of the application is then loaded into internal memory 230. Specifically, storage information stored in the internal memory 230 by the application program is determined from the executable file of the application program, and the storage information includes section information of a heap section, a stack section, a code section, an initialized data section, and an uninitialized data section allocated in the internal memory 230. The first storage information is determined according to file information of the application executable file, and the section information is divided in the internal memory 230 according to the first memory information.
When determining storage information stored in the internal memory 230 by an application program based on an executable file of the application program, a section size and alignment information of each section allocated in the internal memory 230 are determined based on the executable file. Determining the size of each section according to the data in the executable file; the application alignment of the executable file stored in the internal memory 230 is then determined as alignment information based on the processor's fingering. The alignment information indicates which alignment boundary the start address of each data segment should start (e.g., 2, 4, 8, 32 byte alignment, etc.), and determines the start position of each data segment, specifically, the instruction type of the processor. The section size and alignment information then generates section information for the data section, the section information including the section size and alignment information.
Then, storage information is generated based on the section information, and the section information of each data section is used as the storage information. Each data section includes a heap section, a stack section, a code section, an initialized data section, and an uninitialized data section.
The application is then run according to the executable file stored in the internal memory 230. When the application is run, a first instruction stream of the application is obtained according to the code section.
Subsequently, step S320 is performed, where a second memory access instruction is obtained from the instruction storage section of the internal memory 230, the second memory access instruction is adapted to store or read the data to be stored or read by the first memory access instruction, and the processor does not generate a data memory access exception message when executing the second memory access instruction. The second access instructions include a second access instruction and a second store instruction, respectively, adapted to read or store data in the internal memory 230. The second memory instruction includes a store to bound instruction. The second access instruction includes a store-to-bound instruction and the second store instruction includes a store-to-bound instruction.
According to one embodiment of the invention, when the second memory access instruction is not stored in the internal memory 230, a first instruction stream of the application is submitted to the processor, the first instruction stream comprising the first memory access instruction adapted to access data in the internal memory 230. The internal memory 230 storing the second memory access instruction means that when the application is running for the first time, the first memory access instruction is not yet converted into the second memory access instruction. When the application is executed for the first time, a first instruction stream of the application is obtained according to the code section.
When the processor cannot normally execute the first access instruction due to the memory address of the first access instruction, generating a second access instruction according to the data access exception message generated by the processor. When the first access instruction is the first access instruction, converting the first access instruction into a second access instruction; when the first access instruction is a first storage instruction, the first access instruction is converted into a second access instruction.
When data is stored in the internal memory 230 in a special case, the processor 150 cannot execute the special operation instruction, and a data access exception message is generated. According to one embodiment of the present invention, when the data to be read by the application 110 is stored in the internal memory 230 without the bound, the first operation instruction is an instruction with the bound memory access, and the data access exception message is an exception with the bound memory access. The non-alignment is that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type sequentially stored in the memory. For example, a certain 32-bit register, when data is normally stored, the register completely stores 32-bit data, and the first address of the data storage is the first address of the register. However, when the storage is not bounded, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is stored in the next register along with it. An unbounded memory access exception refers to directly accessing the unbounded data on a processor 150 that does not support direct access to the unbounded data, which would cause the processor 150 to throw the exception. The processor 150 cannot completely fetch the 32-bit data stored in the memory according to one instruction, so that the processor 150 throws an exception and issues a data access exception message.
According to one embodiment of the invention, when the second memory access instruction is generated according to the data memory access exception message generated by the processor, the address and the offset can be calculated according to the first target address of the first memory access instruction, the second target address is generated according to the address and the offset, and finally the second storage instruction is generated according to the second target address.
According to one embodiment of the present invention, the first access instruction is load Ra.32, disp1 (Rb 1.32), and the first access instruction is an instruction to load a 32-bit integer having a first target address of Rb1+disp1 into the register Ra. Where Rb1 represents the first address of register Rb and disp1 is the offset of a 32-bit integer on the first address of register Rb.
To fetch the 32-bit data separated in two consecutive registers, the number of bits of the first operation instruction needs to be doubled, i.e., each consecutive two 32-bit registers in the internal memory 230 are regarded as one whole to operate. For example: the 0 th 32-bit register and the 1 st 32-bit register are regarded as one 64-bit register to operate, and the subsequent registers are analogized.
When the second target address of the second access instruction is calculated, the address of the original register Rb, namely the memory address, is calculated according to the merging condition. The original register Rb is the ith register, when i is an odd number, the original register Rb and the next register are combined to be regarded as a whole to obtain a combined register Rb, and the address Rb1 of the original register Rb is still the address Rb2 of the combined register Rb. When i is even, the original register Rb and the previous register are combined to be regarded as a whole to obtain a combined register Rb, and the storage address of the original register Rb is added with the operation bit number, namely Rb1+32 is used as the address Rb2 of the combined register Rb.
When calculating the offset of the second operation instruction, the offset is calculated using the following formula:
disp2＝(Rb1+disp1)-(Rb1+disp1)％64
and generating a second target address Rb2+disp2 according to the storage address and the offset.
And generating a second access instruction according to the second target address: load Ra.64, disp2 (Rb 2.32), the second memory access instruction indicates that the second target address is a 32-bit integer of Rb2+ disp2, read from the 64-bit aligned register into register Ra. The second memory access instruction is then executed by the processor to store or read data in the internal memory 230, where execution of the second memory access instruction by the processor does not raise a data memory access exception.
According to one embodiment of the present invention, when the second memory access instruction is generated according to the data memory access exception message generated by the processor, a first half memory instruction and a second half memory instruction may also be generated according to the memory address of the first memory instruction, where the first half memory instruction and the second half memory instruction are respectively adapted to store data according to the first half address and the second half address, and then the first half memory instruction and the second half memory instruction are used as the second memory instruction. When reading data, executing a first half section reading instruction by the processor, and reading the stored first half section data according to the first half section address; executing the second-half instruction by the processor, and reading out the stored second-half data according to the second-half address; and then combining the first half segment data read from the first half segment address with the second half segment data read from the second half segment address to obtain data. When the first half data and the second half data are combined and arranged, the obtained first half data and the second half data are subjected to shift, AND or equal logic bit operation according to the data structures of the first half data and the second half data, and the needed data are intercepted and aligned from the data obtained by the access instruction.
Finally, an instruction storage section is provided in the code section of the executable file of the application, and the second memory access instruction is stored in the instruction storage section, so that when the application is operated and the code section of the executable file is loaded, the second memory access instruction is loaded into the internal memory 230 from the instruction storage section. FIG. 4 illustrates a schematic diagram of inserting a second memory instruction into a code section according to an exemplary embodiment of the present invention.
As shown in fig. 4, an instruction storage section is inserted in the code section 413 to obtain a code section 423, and the code section 423 includes an instruction storage section 424 for storing a second memory instruction.
Currently, there is no way for an application to change its behavior after it has been compiled into a binary, unless its source code is modified and recompiled. However, in some application scenarios, we cannot modify the source code of the application program, and other technical means are needed to change the behavior of the application program. Although the instruction sequence of the application program can be modified during the running process, since the binary file of the application program is not modified, the instruction sequence needs to be modified again during the next running process of the application program to ensure that the newly added function is unchanged.
And, in each running application, the non-access to the interface memory exception generated by the application instruction stream is required to be processed, the non-access to the interface instruction is converted into the access to the interface instruction, and the computer resource is consumed. Therefore, the invention persists the instruction sequence dynamically modified in the running process, and the instruction code does not need to be modified once again when the application program runs again next time, thereby reducing the overall cost of the system.
Then, step S330 is executed to replace the first memory access instruction in the first instruction stream of the application according to the obtained second memory access instruction, thereby obtaining the second instruction stream. And replacing the corresponding first access instruction in the first instruction stream every time a second access instruction is acquired.
According to one embodiment of the present invention, after each replacement, it is determined whether there is an unread second memory access instruction in the instruction storage section, and if there is an unread second memory access instruction, the second memory access instruction is read to replace the first memory access instruction in the first instruction stream of the application. Therefore, replacement of all first access instructions of the first instruction stream of the application is guaranteed, and after all first access instructions are replaced by second access instructions, a second instruction stream comprising a plurality of second access instructions is obtained.
Finally, step S340 is executed to submit the second instruction stream to the processor, and execute the second instruction stream through the processor to run the application. At this time, the processor executing the second instruction stream will not generate a data access exception.
The application program running method of the present invention is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory, and one or more applications are run, the storage area of the internal memory is mapped into a storage space, and the applications read and write data in the internal memory by using storage addresses in the storage space, the method comprises the steps of: firstly, acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first access instruction, and when the processor executes the first access instruction, the processor generates a data access exception message because the memory address of the first access instruction cannot normally execute the first access instruction; then, a second access instruction is obtained from an instruction storage section of the internal memory, the second access instruction is suitable for storing or reading data to be stored or read by the first access instruction, and a processor does not generate a data access abnormal message when executing the second access instruction; and then, according to the acquired second memory access instruction, replacing the first memory access instruction in the first instruction stream of the application to obtain a second instruction stream. Finally, the second instruction stream is submitted to the processor for execution of the application. According to the invention, the second memory access instruction which does not generate the data access abnormal information is obtained from the internal memory, and the first memory instruction in the instruction stream is replaced, so that the second instruction stream which does not generate the data access abnormal information and can be normally executed by the processor can be obtained, the time for carrying out abnormal processing each time is saved, and the running efficiency of the application is improved.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim.
Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into a plurality of sub-modules.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or groups of embodiments may be combined into one module or unit or group, and furthermore they may be divided into a plurality of sub-modules or sub-units or groups. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
Furthermore, some of the embodiments are described herein as methods or combinations of method elements that may be implemented by a processor of a computer system or by other means of performing the functions. Thus, a processor with the necessary instructions for implementing the described method or method element forms a means for implementing the method or method element. Furthermore, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is for carrying out the functions performed by the elements for carrying out the objects of the invention.
The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions of the methods and apparatus of the present invention, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to execute the application running method of the present invention according to instructions in said program code stored in the memory.
By way of example, and not limitation, computer readable media comprise computer storage media and communication media. Computer-readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules, or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.
As used herein, unless otherwise specified the use of the ordinal terms "first," "second," "third," etc., to describe a general object merely denote different instances of like objects, and are not intended to imply that the objects so described must have a given order, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of the above description, will appreciate that other embodiments are contemplated within the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the appended claims.
Claims (10)
1. An application program running method, suitable for executing in a computing device, the computing device comprising a processor and an internal memory, and running one or more applications, the memory area of the internal memory being mapped to a memory space, and the applications reading and writing data in the internal memory with memory addresses in the memory space, the method comprising the steps of:
Acquiring a first instruction stream of the application, wherein the first instruction stream comprises a first memory access instruction, and when the processor executes the first memory access instruction, the processor generates a data memory access abnormal message because a memory address of the first memory access instruction cannot normally execute the first memory access instruction;
Acquiring a second memory access instruction from an instruction storage section of the internal memory, wherein the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor does not generate a data memory access abnormal message when executing the second memory access instruction;
According to the acquired second access instruction, replacing a first access instruction in the first instruction stream of the application to obtain a second instruction stream;
Submitting the second instruction stream to the processor, executing the second instruction stream by the processor, and running the application;
the method further comprises the steps of:
Submitting a first instruction stream of the application to the processor when no second access instructions are stored in the internal memory, the first instruction stream comprising first access instructions adapted to access data in the internal memory;
when the processor cannot normally execute the first access instruction due to the memory address of the first access instruction, generating a second access instruction according to the data access exception message generated by the processor,
Executing, by the processor, the second access instruction to store or read data in the internal memory;
And setting an instruction storage section in a code section of an executable file of the application, and storing the second memory access instruction in the instruction storage section so as to run the application, and loading the second memory access instruction into the internal memory from the instruction storage section when loading the code section of the executable file.
2. The method of claim 1, wherein the computing device further comprises an external memory having application files stored therein, the method further comprising the steps of:
Generating an executable file of the application program according to the application file;
Loading an executable file of the application program into the internal memory;
and running the application according to the executable file stored in the internal memory.
3. The method of claim 2, wherein the executable file includes a code section, and the running the application from the executable file stored in the internal memory includes the steps of:
and obtaining a first instruction stream of the application according to the code section.
4. The method as claimed in claim 1, wherein said replacing the first memory instruction in the first instruction stream of the application according to the acquired second memory instruction, to obtain the second instruction stream comprises the steps of:
Judging whether the unread second access instruction exists in the instruction storage section;
And if the second access instruction which is not read exists, reading the second access instruction, and replacing the first access instruction in the first instruction stream of the application.
5. The method of any of claims 1-4, wherein the first memory instruction comprises a non-exclusive memory access instruction and the data memory exception message comprises a non-exclusive data access exception message.
6. The method of claim 5, wherein the second memory instruction comprises a store-to-world instruction.
7. The method of claim 6, wherein the generating a second memory access instruction from the processor-generated data memory access exception message comprises the steps of:
Generating a first half storage instruction and a second half storage instruction according to the storage address of the first access instruction, wherein the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address;
and taking the first half storage instruction and the second half storage instruction as second storage instructions.
8. The method of claim 6, wherein the generating a second memory access instruction from the processor-generated data memory access exception message comprises the steps of:
Calculating a storage address and an offset according to a first target address of the first access instruction;
generating a second target address according to the storage address and the offset;
and generating a second storage instruction according to the second target address.
9. A computing device, comprising:
One or more processors;
A memory; and
One or more apparatuses comprising instructions for performing the method of any of claims 1-8.
10. A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform the method of any of claims 1-8.
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| CN113535451A (en) * | 2021-07-12 | 2021-10-22 | 广州翼辉信息技术有限公司 | Processing method, device, storage medium and computing device for abnormal processor access |
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| CN113535451A (en) * | 2021-07-12 | 2021-10-22 | 广州翼辉信息技术有限公司 | Processing method, device, storage medium and computing device for abnormal processor access |
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