CN114002909A - Contact hole pattern mask, method for making the same, and semiconductor device - Google Patents
Contact hole pattern mask, method for making the same, and semiconductor device Download PDFInfo
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- CN114002909A CN114002909A CN202010737832.7A CN202010737832A CN114002909A CN 114002909 A CN114002909 A CN 114002909A CN 202010737832 A CN202010737832 A CN 202010737832A CN 114002909 A CN114002909 A CN 114002909A
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- contact hole
- hole pattern
- pattern mask
- drain
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本公开提供一种接触孔图案掩模、其制作方法及半导体器件。所述接触孔图案掩模用于制造掩埋沟道阵列晶体管的漏极接触孔图案，所述漏极接触孔为连接两个所述晶体管之漏极的漏极线与每个所述晶体管漏极的接触孔；其中，本公开的接触孔图案掩模为椭圆形。所述椭圆形长轴与所述漏极线之间的夹角小于等于45度。所述方法包括：根据要接触孔图案规格，确定接触孔图案掩模的光学临近校正模型；确定套刻裕度；根据所述套刻裕度制作椭圆形的接触孔图案掩模。籍由长轴导致的面积增加，本公开扩大了长轴的套刻裕度，其产生的重叠的分布比较稳定，使得接触孔的不良减少，从而使得接触孔制造的良率上升。
The present disclosure provides a contact hole pattern mask, a manufacturing method thereof, and a semiconductor device. The contact hole pattern mask is used to fabricate a drain contact hole pattern of a buried channel array transistor, and the drain contact hole is a drain line connecting the drains of the two transistors and the drain of each transistor The contact hole; wherein, the contact hole pattern mask of the present disclosure is oval. The included angle between the long axis of the ellipse and the drain line is less than or equal to 45 degrees. The method includes: determining an optical proximity correction model of the contact hole pattern mask according to the specification of the contact hole pattern; determining an overlay margin; and making an elliptical contact hole pattern mask according to the overlay margin. Due to the area increase caused by the long axis, the present disclosure expands the overlay margin of the long axis, and the resulting overlapping distribution is relatively stable, so that the defects of the contact holes are reduced, and the yield of the contact holes is increased.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a contact hole pattern mask, a manufacturing method thereof and a semiconductor device.
Background
As the pattern size of Dynamic Random Access Memory (DRAM) becomes smaller, the overlap (Overlay) between the patterns becomes increasingly important.
Currently, the industry is looking for a solution to reduce Overlay error (Overlay error) and a method to improve Overlay margin (Overlay margin). As DRAM patterns become smaller, the overlay margin also becomes smaller. For example, an overlay is required between the pre-process and the post-process of the DRAM manufacturing, but the contact area between the patterns is reduced due to the overlay error, which results in poor yield of the DRAM, and thus how to increase the overlay margin becomes relatively important.
As shown in fig. 1, BCAT is a Buried Channel Array Transistor (BCAT), a Drain Line Contact (DLC) used at present is circular, and an overlay margin thereof is small.
Disclosure of Invention
An object of the present disclosure is to provide a contact hole pattern mask, a method of fabricating the same, and a semiconductor device.
A first aspect of the present disclosure provides a contact hole pattern mask for manufacturing a drain contact hole pattern of a buried channel array transistor, the drain contact hole being a contact hole connecting a drain line of drain electrodes of two of the transistors and a drain electrode of each of the transistors; wherein the contact hole pattern mask has an elliptical shape.
A second aspect of the present disclosure provides a method for manufacturing a contact hole pattern mask, including:
determining an optical proximity correction model of the contact hole pattern mask according to the specification of the contact hole pattern to be contacted;
determining an alignment margin according to the optical proximity correction model; (ii) a
And manufacturing an elliptical contact hole pattern mask according to the alignment margin.
This disclosure compares advantage with prior art and lies in: the overlapping distribution is stable, so that the defects of the contact holes are reduced, and the yield of the contact hole manufacture is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a prior art schematic;
FIG. 2 is a schematic view of a first contact hole pattern mask shape according to the present disclosure;
FIG. 3 is a schematic view of a second contact hole pattern mask shape according to the present disclosure;
FIG. 4 is a schematic diagram of drain line contact for a buried channel array transistor made using the contact hole pattern mask of the present disclosure;
FIG. 5 is a schematic diagram illustrating the concept of improving overlay margin after using the contact hole pattern mask of the present disclosure.
Fig. 6 is a flowchart of a method of making a contact hole pattern mask according to the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a contact hole pattern mask and a method for manufacturing the contact hole pattern mask, which are described below with reference to the accompanying drawings.
The main invention of the present disclosure is to change the contact hole pattern mask from a circle to an ellipse, and the adopted technical means is to change the shape of the mask by Optical Proximity Correction (OPC), and the included angle between the major axis of the ellipse and the drain line can be plus or minus 45 degrees.
FIG. 2 is a schematic view of a first contact hole pattern mask shape according to the present disclosure; a contact hole pattern mask for manufacturing a drain contact hole pattern of the buried channel array transistor, the contact hole being a contact hole connecting a drain line of the drains of the two transistors and the drain of each transistor; by changing the shape of the mask using optical proximity correction, changing the contact hole pattern mask from a circular shape to an elliptical shape, the horizontal angle between the major axis of the elliptical shape and the drain line can be positive 45 degrees. The contact hole pattern manufactured through the circular contact hole pattern mask is circular, and has an area of: π r ^2(nm ^2) where r is the radius of the circle. In this embodiment, the contact hole pattern manufactured by the elliptical contact hole pattern mask is elliptical, and has an area of: π ra (nm ^2) where r is the minor axis radius, corresponding to the radius of the original circular mask, and a is the major axis radius.
Since the length of the major axis of the ellipse is greater than the minor axis, the area of the elliptical contact hole pattern mask, π ra, is greater than the area of the circular contact hole pattern mask, π r ^2, resulting in the area of the elliptical contact hole pattern being made greater than the area of the circular contact hole pattern. Therefore, due to the increase of the area caused by the long axis, the overlay margin of the long axis is enlarged, the generated overlay distribution is stable, the defect of the contact hole is reduced, and the yield of the contact hole manufacture is improved.
The elliptical contact hole pattern of the present embodiment has major and minor axis dimensions of 40nm or less.
The included angle between the major axis of the ellipse and the drain line is preferably 45 degrees, but the technical effect of the present disclosure can be better implemented when the included angle is less than 45 degrees. However, the case of more than 45 degrees is not generally adopted because the margin generated in the lateral direction is gradually reduced, resulting in poor technical effect of implementing the invention.
FIG. 3 is a schematic view of a second contact hole pattern mask shape according to the present disclosure; a contact hole pattern mask for manufacturing a drain contact hole pattern of the buried channel array transistor, the contact hole being a contact hole connecting a drain line of the drains of the two transistors and the drain of each transistor; by changing the shape of the mask using optical proximity correction, changing the contact hole pattern mask from circular to elliptical, the horizontal angle between the major axis of the ellipse and the drain line can be negative 45 degrees. The contact hole pattern manufactured through the circular contact hole pattern mask is circular, and has an area of: π r ^2(nm ^2) where r is the radius of the circle. In this embodiment, the contact hole pattern manufactured by the elliptical contact hole pattern mask is elliptical, and has an area of: π ra (nm ^2) where r is the minor axis radius, corresponding to the radius of the original circular mask, and a is the major axis radius.
FIG. 4 is a schematic diagram of drain line contact for a buried channel array transistor made using the contact hole pattern mask of the present disclosure; in fig. 4, drain lines DL connect the drains of two rows of BCATs, and contact holes, two rows of contact holes DLC1 and DLC2 respectively, are formed at each contact of the drain lines with the BCATs. Both rows of contact hole patterns may be generated using the contact hole pattern mask of the present disclosure, or only one row of contact hole patterns selected may be generated using the contact hole pattern mask of the present disclosure.
Since the major axis length of the ellipse is greater than the minor axis, the area of the elliptical contact hole pattern mask is greater than that of the circular contact hole pattern mask, resulting in the preparation of an elliptical contact hole pattern having an area greater than that of the circular contact hole pattern. Therefore, due to the increase of the area caused by the long axis, the overlay margin of the long axis is enlarged, the generated overlay distribution is stable, the defect of the contact hole is reduced, and the yield of the contact hole manufacture is improved.
The elliptical contact hole pattern of the present embodiment has major and minor axis dimensions of 40nm or less.
FIG. 5 is a schematic diagram illustrating the concept of improving overlay margin after using the contact hole pattern mask of the present disclosure. Since the major axis length of the ellipse is greater than the minor axis, the area of the elliptical contact hole pattern mask is greater than that of the circular contact hole pattern mask, resulting in the preparation of an elliptical contact hole pattern having an area greater than that of the circular contact hole pattern. Therefore, due to the increase of the area caused by the long axis, the overlay margin of the long axis is enlarged, the generated overlay distribution is stable, the defect of the contact hole is reduced, and the yield of the contact hole manufacture is improved. The included angle between the major axis of the ellipse and the drain line is preferably minus 45 degrees in this embodiment, however, the technical effect of the present disclosure can be better implemented when the included angle is less than 45 degrees. However, the case of more than 45 degrees is not generally adopted because the margin generated in the lateral direction is gradually reduced, resulting in poor technical effect of implementing the invention.
Fig. 6 is a flowchart of a method for manufacturing a contact hole pattern mask according to the present disclosure, which includes the following steps:
s1, determining an optical proximity correction model of the contact hole pattern mask according to the specification of the contact hole pattern to be prepared;
s2, determining an alignment margin according to the optical proximity correction model; in this step, it can be further verified whether the overlay margin meets the design requirement;
and S3, manufacturing an elliptical contact hole pattern mask according to the overlay margin. In this step, first, the major and minor axis dimensions of the contact hole pattern mask are determined according to the overlay margin; then, an elliptical contact hole pattern mask is fabricated according to the major and minor axis dimensions.
Further, according to the practical use effect of the contact hole pattern mask, embodiments of the present disclosure may further include the steps of:
and S4, correcting the optical proximity correction model according to the wafer-level quality of the contact hole pattern mask.
In the above method flow, the composition of the contact hole pattern is determined by steps S1, S2. The method is suitable for the objects including the manufacture of contact hole patterns and the process of fusing all the objects.
Therefore, the method of the present disclosure expands the overlay margin of the long axis due to the increase of the area caused by the long axis, and the overlay distribution thereof is stable, so that the defects of the contact hole are reduced, thereby increasing the yield of the contact hole manufacturing.
In the present disclosure, there is also provided a semiconductor device including a buried channel array transistor, a drain contact hole pattern of the transistor being prepared using the above elliptical contact hole pattern mask.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.
Claims (10)
1. A contact hole pattern mask, characterized in that,
the contact hole pattern mask is used for manufacturing a drain contact hole pattern of a buried channel array transistor, and the drain contact hole is a contact hole for connecting a drain line of the drains of two transistors and the drain of each transistor; wherein,
the contact hole pattern mask is elliptical.
2. The contact hole pattern mask according to claim 1,
and the included angle between the long axis of the ellipse and the drain line is less than or equal to 45 degrees.
3. The contact hole pattern mask according to claim 2,
the contact hole pattern has major and minor axis dimensions within 40 nm.
4. A method of making a contact hole pattern mask, comprising:
determining an optical proximity correction model of a contact hole pattern mask according to the specification of the contact hole pattern;
determining an alignment margin according to the optical proximity correction model;
and manufacturing an elliptical contact hole pattern mask according to the alignment margin.
5. The method of claim 4, further comprising, after the step of forming the elliptical contact hole pattern mask:
and correcting the optical proximity correction model according to the wafer-level quality of the contact hole pattern mask.
6. The method of manufacturing according to claim 4,
the contact hole pattern has major and minor axis dimensions of 40nm or less.
7. The method of claim 4, further comprising, after determining an overlay margin according to the OPC model:
verifying the overlay margin.
8. The method of manufacturing according to claim 7,
and the included angle between the long axis of the ellipse and the drain line is less than or equal to 45 degrees.
9. The method of manufacturing according to claim 4,
the method for manufacturing the elliptical contact hole pattern mask according to the overlay margin comprises the following steps:
determining the sizes of a long axis and a short axis of the contact hole pattern mask according to the overlay margin;
and manufacturing an elliptical contact hole pattern mask according to the sizes of the long axis and the short axis.
10. A semiconductor device, characterized in that,
comprising a buried channel array transistor, the drain contact hole pattern of which is prepared using the contact hole pattern mask of any one of claims 1-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010737832.7A CN114002909A (en) | 2020-07-28 | 2020-07-28 | Contact hole pattern mask, method for making the same, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010737832.7A CN114002909A (en) | 2020-07-28 | 2020-07-28 | Contact hole pattern mask, method for making the same, and semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN114002909A true CN114002909A (en) | 2022-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010737832.7A Pending CN114002909A (en) | 2020-07-28 | 2020-07-28 | Contact hole pattern mask, method for making the same, and semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252266B1 (en) * | 1998-08-26 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with comb electrodes and via holes |
| US20080023772A1 (en) * | 2006-07-25 | 2008-01-31 | Elpida Memory, Inc. | Semiconductor device including a germanium silicide film on a selective epitaxial layer |
| CN101126892A (en) * | 2006-08-11 | 2008-02-20 | 东部高科股份有限公司 | Mask for forming contact holes |
| KR20090109353A (en) * | 2008-04-15 | 2009-10-20 | 주식회사 하이닉스반도체 | Drain contact hole formation method of flash memory device |
| CN111324003A (en) * | 2018-12-14 | 2020-06-23 | 夏泰鑫半导体(青岛)有限公司 | Method for correcting photomask pattern |
-
2020
- 2020-07-28 CN CN202010737832.7A patent/CN114002909A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252266B1 (en) * | 1998-08-26 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with comb electrodes and via holes |
| US20080023772A1 (en) * | 2006-07-25 | 2008-01-31 | Elpida Memory, Inc. | Semiconductor device including a germanium silicide film on a selective epitaxial layer |
| CN101126892A (en) * | 2006-08-11 | 2008-02-20 | 东部高科股份有限公司 | Mask for forming contact holes |
| KR20090109353A (en) * | 2008-04-15 | 2009-10-20 | 주식회사 하이닉스반도체 | Drain contact hole formation method of flash memory device |
| CN111324003A (en) * | 2018-12-14 | 2020-06-23 | 夏泰鑫半导体(青岛)有限公司 | Method for correcting photomask pattern |
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