CN113992201A - A level conversion circuit and its layout structure, standard unit and chip - Google Patents

Abstract

The embodiment of the invention discloses a level conversion circuit and a layout structure, a standard unit and a chip thereof, relates to the technical field of semiconductors, and can improve the integration level of the circuit. The circuit comprises: the processing part is powered by a power supply of a target voltage domain through a preset voltage following device, and the voltage following device is driven by the power supply of the target voltage domain to apply preset voltage of a source voltage domain to the processing part; and the conversion part is respectively connected with the signal to be converted and the processing part and outputs a converted signal according to the signal to be converted and the inverted signal to be converted, wherein the logic level of the signal to be converted belongs to the source voltage domain, the logic level of the converted signal belongs to the target voltage domain, and the conversion part is powered by a power supply of the target voltage domain.

Description

Level conversion circuit and layout structure, standard unit and chip thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a level conversion circuit, a layout structure thereof, a standard unit and a chip.

Background

In digital circuits, a binary number of 1 or 0 can be represented by a high level or a low level, thereby providing a basis for various operations. However, due to the complex and various application scenarios, a digital circuit often includes a plurality of circuit modules, and different circuit modules also often correspond to different power supply voltages, i.e., each circuit module has a different voltage domain. Due to the difference of the voltage domains, the high level potential and/or the low level potential corresponding to each circuit module are also different, for example, for a circuit module with a power supply voltage of 1.2V, 1.2V is high, while for a circuit module with a power supply voltage of 2V, 1.2V is considered as low, and if the two circuit modules are directly connected, a logic error may be generated.

In order to enable signal transmission between circuit blocks having different power supply voltages, a Level shift circuit may be provided between the circuit blocks having different power supply voltages. The level conversion circuit can convert an input signal of a first voltage domain into a signal of a second voltage domain and output the signal, so that a bridge is established between the first voltage domain and the second voltage domain.

However, in a semiconductor process implementation of a level shifter circuit, for a P-substrate circuit, the separation distance between the N-well for carrying PMOS (P-type MOS) in the first voltage domain and the N-well for carrying PMOS in the second voltage domain needs to be greater than a prescribed threshold. Similarly, for an N-substrate circuit, the distance between the P-well for carrying NMOS (N-type MOS) in the first voltage domain and the P-well for carrying NMOS in the second voltage domain needs to be greater than a prescribed threshold. Therefore, in order to achieve the minimum pitch requirement, the area of the level shift circuit is often increased, and the integration degree is correspondingly reduced.

Disclosure of Invention

In view of this, embodiments of the present invention provide a level shift circuit, and a layout structure, a standard cell, and a chip thereof, which can effectively reduce the area of the level shift circuit and greatly improve the integration level of the circuit.

In a first aspect, an embodiment of the present invention provides a level shift circuit, including: the processing part is used for logically inverting the signal to be converted to obtain an inverted signal to be converted, wherein the processing part is powered by a power supply of a target voltage domain through a preset voltage following device, and the voltage following device is used for applying preset voltage of a source voltage domain to the processing part under the driving of the power supply of the target voltage domain; and the conversion part is respectively connected with the signal to be converted and the processing part and is used for outputting a converted signal according to the signal to be converted and the inverted signal to be converted, wherein the logic level of the signal to be converted belongs to the source voltage domain, the logic level of the converted signal belongs to the target voltage domain, and the conversion part is powered by a power supply of the target voltage domain.

Optionally, the processing portion includes an inverter, a first end of the inverter is connected to the signal to be converted, a second end of the inverter is connected to the converting portion, a third end of the inverter is connected to the voltage follower, and a fourth end of the inverter is grounded.

Optionally, a first end of the voltage follower is connected to the preset voltage, a second end of the voltage follower is connected to the power supply of the destination voltage domain, and a third end of the voltage follower is connected to the processing unit, where a voltage of the third end is less than or equal to a voltage of the first end.

Optionally, the voltage follower means comprises a transistor.

Optionally, the level shift circuit is disposed on a P-type substrate, and the voltage follower device includes an N-type transistor; or the level conversion circuit is arranged on an N-type substrate, and the voltage following device comprises a P-type transistor.

Optionally, a voltage stabilizing buffer device is further disposed between the preset voltage of the target voltage domain and the voltage follower device.

In a second aspect, an embodiment of the present invention further provides a layout structure of a level shifter circuit, including: the processing part layout structure, the conversion part layout structure and the voltage follower layout structure; the processing part layout structure comprises a first well graph and a first circuit graph, and at least one part of the first circuit graph is positioned in the coverage range of the first well graph; the switching part layout structure comprises a second well graph and a second circuit graph, and at least one part of the second circuit graph is positioned in the coverage range of the second well graph; the spacing distance between the first trap graph and the second trap graph is smaller than a preset distance threshold value; the first well pattern and the second well pattern are connected with a power supply pattern of a target voltage domain through a first wiring pattern; the first circuit pattern is connected with the voltage follower layout structure, and the voltage follower layout structure is connected with the power supply pattern of the target voltage domain through a second wiring pattern; the second circuit pattern is connected with the power supply pattern of the target voltage domain through a third wiring pattern; the voltage follower layout structure is also connected with a fourth wiring pattern, and the fourth wiring pattern extends from the source voltage domain.

Optionally, the voltage follower layout structure is a transistor layout structure.

Optionally, the transistor layout structure includes a first pole pattern, a second pole pattern, and a third pole pattern; the first pole pattern is connected to the fourth wiring pattern, the second pole pattern is connected to a power supply pattern of the destination voltage domain, and the third pole pattern is connected to the first circuit pattern.

Optionally, a contact hole pattern is provided on the first well pattern or the second well pattern, the first wiring pattern at least partially covers the contact hole pattern, and the first well pattern and the second well pattern are connected together.

Optionally, the first circuit pattern includes a first CMOS pattern, and the second circuit pattern includes a second CMOS pattern.

Optionally, the line width of the fourth wiring pattern is smaller than a preset line width threshold.

Optionally, the layout structure of the level shifter circuit further includes a voltage stabilization buffer layout structure, and the fourth wiring pattern extends from the source voltage domain and is sequentially connected to the voltage stabilization buffer layout structure and the voltage follower layout structure.

In a third aspect, an embodiment of the present invention further provides a standard cell, including at least one level shift circuit provided in an embodiment of the present invention; and each level conversion circuit receives the signal to be converted and converts the signal to be converted into a corresponding converted signal to be output.

Optionally, the power supply voltages of the source voltage domains to which the signals to be converted received by the level conversion circuits belong are the same or different; the power supply voltages of the target voltage domains to which the converted signals output by the level conversion circuits belong are the same.

Optionally, the source voltage of the source voltage domain to which each signal to be converted received by each level conversion circuit belongs is the same, and the voltage follower of each level conversion circuit is connected to the same preset voltage.

In a fourth aspect, the embodiment of the present invention further provides a chip, where any one of the level shift circuits provided by the embodiment of the present invention is disposed in the chip, or any one of the standard cells provided by the embodiment of the present invention is disposed in the chip.

According to the level conversion circuit, the layout structure, the standard unit and the chip, the processing part is powered by the power supply of the target voltage domain through the preset voltage following device, and the conversion part is also powered by the power supply of the target voltage domain, so that the voltage conversion circuit provided by the embodiment of the invention is substantially powered by the power supply of the target voltage domain only, does not need the power supply of the source voltage domain, does not need to consider the problem of well isolation among different voltage domains, and further effectively reduces the area of the voltage conversion circuit. In addition, the voltage follower device can apply the preset voltage of the source voltage domain to the processing part under the driving of the power supply of the target voltage domain, so that the actual working voltage of the processing part conforms to the voltage range of the source voltage domain to realize level conversion.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a circuit schematic of a prior art level shift circuit;

fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a level shift circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a structure of a circuit for generating the predetermined voltage VDDSCR _ TIEH in the level shifter circuit shown in fig. 3;

FIG. 5 is another circuit schematic of a level shifting circuit provided by an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a layout structure of a level shift circuit according to an embodiment of the present invention;

fig. 7 is a partial schematic diagram of a layout structure of a level shifter circuit in an embodiment of the present invention;

fig. 8 is another partial schematic diagram of a layout structure of a level shifter circuit in an embodiment of the present invention;

fig. 9 is a partial schematic diagram of a layout structure of the level shifter circuit shown in fig. 3;

fig. 10 is a partial schematic diagram of a layout structure of the level shifter circuit shown in fig. 1 in the related art.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As mentioned in the background, the level shift circuit in the related art is mainly used for shifting a level signal between different voltage domains, so that the operating range usually spans at least two voltage domains and is powered by at least two different power sources. When the level shift circuit has an N-well structure or a P-well structure in these voltage domains, it is necessary to connect these N-wells or P-wells to the power supplies in the respective voltage domains in order to prevent latch-up. Because the voltage domains of the power supplies connected with the N-wells or the P-wells are different, in order to ensure stable chip performance, during layout Design, a certain distance is required to be separated between several N-wells in different voltage domains or between several P-wells in different voltage domains, otherwise DRC (Design Rule Check) cannot pass.

For example, fig. 1 is a schematic structural diagram of a level shift circuit disposed on a P substrate. As shown in fig. 1, a is an input terminal of the level shifter, and Q is an output terminal of the level shifter. VDDSRC is the source voltage domain power supply and VDDST is the destination voltage domain power supply. Circuit block Part1 is powered by VDDSRC and circuit block Part2 is powered by VDDDST. The N-well for carrying the PMOS in the circuit module Part1 and the N-well for carrying the PMOS in the circuit module Part2 need to be separated by a predetermined distance or more, which results in a relatively increased area of the level shifter circuit and a corresponding decrease in integration level.

In order to solve the above problems, the inventor has found in research that the level shift circuit can realize level shift by some elaborate designs under the condition of using only one power supply to supply power. Therefore, the P substrate originally positioned between the N wells in different voltage domains or the N substrate originally positioned between the P wells in different voltage domains can be in the same voltage domain, so that a specified distance does not need to be spaced, and the integration level is effectively improved.

Technical ideas, embodiments and advantageous technical effects of the embodiments of the present invention will be described in detail below with reference to specific examples in order to enable those skilled in the art to better understand the technical ideas, embodiments and advantageous technical effects of the examples.

As shown in fig. 2, an embodiment of the present invention provides a level shift circuit, which may include:

the processing unit 1, one end of which is connected to the signal B to be converted, and the other end of which is connected to the converting unit 2, is configured to perform logical inversion on the signal B to be converted to obtain an inverted signal Binv to be converted, where the processing unit 1 is powered by a power supply VDDDST in a target voltage domain through a preset voltage follower VFollower, and the voltage follower VFollower is configured to apply a preset voltage VDDSRC _ TIEH in a source voltage domain to the processing unit 1 under the driving of the power supply VDDDST in the target voltage domain;

and the conversion part2 is respectively connected with the signal B to be converted and the processing part1 and is used for outputting a converted signal C according to the signal B to be converted and the inverted signal Binv to be converted, wherein the logic level of the signal B to be converted belongs to a source voltage domain, the logic level of the converted signal C belongs to a target voltage domain, and the conversion part2 is powered by a power supply VDDST of the target voltage domain.

The level shift circuit provided by the embodiment of the present invention may include a processing portion 1 and a converting portion 2, where one end of the processing portion 1 is connected to a signal B to be converted, and the other end is connected to the converting portion 2, and may perform logical inversion on the signal B to be converted to obtain an inverted signal Binv to be converted; the conversion part2 is respectively connected with the signal B to be converted and the processing part1, and can output a converted signal C according to the signal B to be converted and the inverted signal Binv to be converted, wherein the logic level of the signal B to be converted belongs to a source voltage domain, and the logic level of the converted signal C belongs to a target voltage domain, so that level conversion is realized. In this way, since the processing unit 1 is powered by the power supply VDDDST of the destination voltage domain via the preset voltage follower VFollower, and the converting unit 2 is also powered by the power supply VDDDST of the destination voltage domain, the voltage converting circuit provided by the embodiment of the present invention is substantially powered only by the power supply VDDDST of the destination voltage domain, and does not need a power supply of the source voltage domain, and does not need to consider the problem of well isolation between different voltage domains, thereby effectively reducing the area of the voltage converting circuit. Moreover, the voltage follower VFollower can apply the preset voltage VDDSRC _ TIEH of the source voltage domain to the processing unit 1 under the driving of the power supply VDDDST of the destination voltage domain, so that the actual operating voltage of the processing unit 1 conforms to the voltage range of the source voltage domain to implement level conversion.

Specifically, the processing unit 1 may have various circuit configurations capable of performing a logical inversion operation on the signal to be converted B, for example, as shown in fig. 3, in an embodiment of the present invention, the processing unit 1 may include an inverter, and the inverter may be formed by transistors T1 and T2. The first end of the inverter can be connected with the signal B to be converted, the second end of the inverter can be connected with the converting part2, the third end of the inverter can be connected with the voltage follower VFollower, and the fourth end of the inverter can be grounded.

Alternatively, the conversion unit 2 may have any configuration of a conventional level conversion circuit as long as it can convert the logic level of the source voltage domain into the logic level of the destination voltage domain. For example, as shown in fig. 3, in an embodiment of the present invention, the circuit Part3 implements a core function of outputting the converted signal C according to the signal B to be converted and the inverted signal Binv to be converted. Of course, in other embodiments of the present invention, Part3 may have other implementation forms, and the embodiments of the present invention do not limit this.

As mentioned above, the voltage follower VFollower can apply the preset voltage VDDSRC _ TIEH of the source voltage domain to the processing portion 1 under the driving of the power supply VDDDST of the destination voltage domain. Alternatively, the specific structure of the voltage follower VFollower is not limited as long as the above circuit connection and functions can be realized. Specifically, in one embodiment of the present invention, a first terminal of the voltage follower VFollower may be connected to the preset voltage VDDSRC _ TIEH, a second terminal may be connected to the power supply VDDDST of the destination voltage domain, and a third terminal may be connected to the processing unit 1, wherein a voltage of the third terminal is less than or equal to a voltage of the first terminal, that is, a voltage of the third terminal "follows" a voltage of the first terminal.

In a specific implementation, the voltage follower device VFollower may include a voltage follower formed by various transistors (e.g., depletion/enhancement MOS, triode, finfet MOS, etc.), such as a source follower or an emitter follower. The first terminal may be a base or a gate of the transistor, the second terminal may be a collector or a drain of the transistor, and the third terminal may be an emitter or a source of the transistor. Wherein the emitter (or source) follower is a kind of negative feedback amplifier. The transistor is connected to a common collector (or a common drain) amplifier. The signal can be input from the base (or gate) electrode and output from the emitter (or source) electrode, so it is also called emitter (or source) electrode follower. The voltage amplification of the emitter (or source) pole follower is constantly less than and close to 1. In this way, the voltage follower including the transistor as a core may be connected to the power supply VDDDST of the destination voltage domain through the collector (or the drain), and the predetermined voltage VDDSRC _ TIEH of the source voltage domain connected to the base (or gate) electrode may be applied to the processing unit 1 by the emitter (or source) electrode following action under the driving of the power supply VDDDST of the destination voltage domain.

Considering that the transistors are divided into N-type transistors and P-type transistors, the transistors of the appropriate type can be selected as the voltage follower VFollower according to the specific structure and process implementation of the level shift circuit. For example, in one embodiment of the present invention, the level shifter circuit is disposed on a P-type substrate, the voltage follower device may comprise an N-type transistor; or the level shifter circuit is disposed on an N-type substrate, the voltage follower device may include a P-type transistor.

It is understood that, in the embodiment of the present invention, although the processing part1 and the converting part2 are both supplied by the power supply VDDDST of the destination voltage domain, the preset voltage VDDSRC _ TIEH is also introduced from the source voltage domain to the destination voltage domain through the voltage follower device VFollower to ensure that the processing part1 operates normally. Specifically, in order to ensure that the actual operating voltage of the processing unit 1 conforms to the voltage range of the source voltage domain, in the embodiment of the present invention, the preset voltage VDDSRC _ TIEH is specifically defined. For example, in one embodiment of the present invention, the absolute value of the difference between the preset voltage VDDSRC _ TIEH and the power supply voltage VDDSRC of the source voltage domain may be less than the preset threshold. The preset threshold may be a small value, for example, 0.1V, 0.2V, and may be specifically set according to different circuit parameters. That is, in the embodiment of the present invention, a preset voltage VDDSRC _ TIEH equal to or approximately equal to the source-voltage domain power voltage VDDSRC may be introduced from the source-voltage domain into the destination-voltage domain by the voltage follower VFollower, and applied to the processing portion 1, so that the processing portion 1 operates normally.

Further, since the predetermined voltage VDDSRC _ TIEH is from the source voltage domain and may be far from the destination voltage domain, in order to reduce or eliminate interference and loss of the predetermined voltage VDDSRC _ TIEH during transmission, in an embodiment of the present invention, a voltage stabilizing buffer device may be further disposed between the predetermined voltage VDDSRC _ TIEH of the destination voltage domain and the voltage follower device VFollower, so that the predetermined voltage VDDSRC _ TIEH from the far source voltage domain is kept stable, thereby avoiding excessive fluctuation and further stabilizing circuit functions. Optionally, the voltage stabilizing buffer may include various types of capacitors, such as a gate capacitor of a MOS transistor.

It should be noted that, the level shift circuit provided in the embodiment of the present invention can shift a level signal of a source voltage domain into a level signal of a destination voltage domain, where the voltage levels of the source voltage domain and the destination voltage domain are not particularly limited, that is, the power voltage of the destination voltage domain may be higher than the power voltage of the source voltage domain, or the power voltage of the destination voltage domain may also be equal to the power voltage of the source voltage domain, or the power voltage of the destination voltage domain may also be lower than the power voltage of the source voltage domain.

It should be noted that the level shift circuit provided in the embodiment of the present invention is a level system shift, but the output signal itself may be the same logic as the input signal or the opposite logic to the input signal, that is, the logic level of the shifted signal may be the same as or opposite to the logic level of the signal to be shifted. For example, the input signal B may be at a high level of a 1.2V voltage domain, and the output signal C may be at a high level of a 2.0V voltage domain, or at a low level of a 2.0V voltage domain.

Furthermore, after the signal of the source voltage domain is converted into the signal of the target voltage domain, the signal output side of the level conversion circuit can be conveniently spliced with other circuits or units of the target voltage domain, and various circuit functions are realized.

The level shift circuit provided by the embodiment of the present invention is described in detail by specific embodiments below.

As shown in fig. 3, the level shift circuit provided by the embodiment of the present invention may include a processing unit 1 and a converting unit 2, where the processing unit 1 may include an inverter formed by connecting a P-type transistor T1 and an N-type transistor T2, an input end of the inverter receives a signal B to be converted, and an output end of the inverter obtains an inverted signal Binv to be converted. The processing unit 1 is supplied with power from the power supply VDDDST of the destination voltage domain via the N-type transistor T3 (i.e., the voltage follower device T3), and the N-type transistor T3 can apply the preset voltage VDDSRC _ TIEH of the source voltage domain to the source of the P-type transistor T1 in the processing unit 1 under the driving of the power supply VDDDST of the destination voltage domain. The conversion part2 may include six transistors T4, T5, T6, T7, T8 and T9, where T4, T5, T6, T7, T8 and T9 form a symmetrical structure, gates of T5 and T6 receive the inverted signal Binv, gates of T8 and T9 receive the converted signal B, a gate of T4 receives a drain of T8, and a gate of T7 receives a drain of T5.

When the signal B to be converted is 1, the signal Binv to be converted is 0, T9 is on, T5 is on, T6 is off, T8 is off, point F is at a low level, so that T4 is on, i.e., T4 and T5 are both on, the point E voltage is at a high level, so that T7 is off, i.e., T7 and T8 are both off, so that point F is stabilized at a low level, i.e., C is 0, and C is equal to the logical negation of B.

When the signal B to be converted is equal to 0, the inverted signal Binv to be converted is equal to 1, T9 is turned off, T5 is turned off, T6 is turned on, T8 is turned on, point E is at a low level, so that T7 is turned on, that is, T7 and T8 are both turned on, and the point F voltage is at a high level, so that T4 is turned off, that is, T4 and T5 are both turned off, point E is stabilized at a low level, and point F is stabilized at a high level, that is, point C is equal to 1, and C is also equal to the logical negation of B.

If the signal C at the F end is taken as the output, the level conversion circuit performs the inversion operation on the signal to be converted while realizing the level conversion, namely the logic level output by the level conversion circuit is opposite to the logic level of the signal to be converted, if the logic level output by the level conversion circuit is expected to be the same as the logic level of the signal to be converted, an inverter can be connected to the F end to obtain Q, and the Q is taken as the output of the level conversion circuit, so that the Q is equal to B.

Optionally, the preset voltage VDDSRC _ TIEH of the source voltage domain may be obtained by directly connecting to the power supply voltage VDDSRC of the source voltage domain, or may be obtained by connecting to the power supply voltage VDDSRC of the source voltage domain through a resistor, a transistor, and the like, which is not limited in the embodiment of the present invention. For example, the predetermined voltage VDDSRC _ TIEH of the source voltage domain may be obtained as shown in fig. 4.

In order to reduce or eliminate the interference and loss of the predetermined voltage VDDSRC _ TIEH during transmission, in an embodiment of the invention, a transistor T10 (i.e., a voltage stabilizing buffer device) may be further disposed between the predetermined voltage VDDSRC _ TIEH of the destination voltage domain and the voltage follower device T3, a source and a drain of T10 are grounded, and a gate is connected to the predetermined voltage VDDSRC _ TIEH, so that the predetermined voltage VDDSRC _ TIEH coming from a far channel of the source voltage domain is stabilized by the voltage stabilizing effect of a gate capacitor of the transistor T10, and excessive fluctuation is avoided.

The level shifter circuit shown in fig. 3 is a P-substrate-based level shifter circuit, but the embodiment of the present invention is not limited thereto, and the level shifter circuit may be an N-substrate-based level shifter circuit. For example, the N-substrate based level shift circuit can be as shown in fig. 5, where VSSSRC _ TIEL is a preset voltage of a source voltage domain, and the basic principle is similar to that of the P-substrate level shift circuit, and is not described herein again.

Correspondingly, the embodiment of the invention also provides a layout structure of the level conversion circuit, which can effectively reduce the area of the level conversion circuit and greatly improve the integration level of the circuit.

As shown in fig. 6, the layout structure of the level shifter circuit provided by the embodiment of the present invention may include:

a processing part layout structure 3, a conversion part layout structure 4 and a voltage follower layout structure 5;

the processing part layout structure 3 comprises a first well pattern WEL1 and a first circuit pattern CIR1, and at least one part of the first circuit pattern CIR1 is positioned in the coverage range of the first well pattern WEL 1; the switching part layout structure 4 comprises a second well pattern WEL2 and a second circuit pattern CIR2, and at least one part of the second circuit pattern CIR2 is positioned in the coverage range of the second well pattern WEL 2; the separation distance between the first well pattern WEL1 and the second well pattern WEL2 is less than a preset distance threshold;

the first well pattern WEL1 and the second well pattern WEL2 are connected to the power supply pattern sharedddst of the destination voltage domain through the first wiring pattern LINE 1; the first circuit graph CIR1 is connected with the voltage follower layout structure 5, and the voltage follower layout structure 5 is connected with a power supply graph ShapeVDST of a target voltage domain through a second wiring graph LINE 2; the second circuit pattern CIR2 is connected to the power supply pattern sharedddst of the destination voltage domain through the third wiring pattern LINE 3; the voltage follower layout structure 5 is also connected to a fourth wiring pattern LINE4, which extends from the source voltage domain, LINE 4.

In the layout structure of the level shifter circuit provided by the embodiment of the invention, because the first circuit pattern CIR1 is connected with the voltage follower layout structure 5, the voltage follower layout structure 5 is connected with the power supply pattern sharedddst of the destination voltage domain through the second wiring pattern LINE2, the second circuit pattern CIR2 is connected with the power supply pattern sharedddst of the destination voltage domain through the third wiring pattern LINE3, the first well pattern WEL1 and the second well pattern WEL2 can be connected with the power supply pattern sharedddst of the destination voltage domain through the first wiring pattern LINE1, and therefore, the corresponding level shifter circuit is not provided with a power supply of the source voltage domain, and the problem of well isolation between different voltage domains does not need to be considered, so that the area of the voltage shifter circuit is effectively reduced. Moreover, the voltage follower layout structure 5 is also connected with the fourth wiring pattern LINE4, and the fourth wiring pattern LINE4 extends from the source voltage domain, so that the preset voltage of the source voltage domain can be applied to the processing part, the actual working voltage of the processing part conforms to the voltage range of the source voltage domain, the level conversion function is guaranteed, the circuit area can be effectively reduced, and the integration level of the circuit is greatly improved.

Optionally, by using the layout structure of the level shift circuit provided by the embodiment of the present invention, the corresponding level shift circuit may be fabricated on a semiconductor substrate. According to different process requirements, the substrate may be a P-type substrate or an N-type substrate, which is not limited in the embodiments of the present invention.

Specifically, the layout structure of the level shifter circuit provided by the embodiment of the present invention may include a processing unit layout structure 3, a converting unit layout structure 4, and a voltage follower layout structure 5. The processing unit layout structure 3 may be used to fabricate a processing unit of a level shifter circuit, the converting unit layout structure 4 may be used to fabricate a converting unit of a level shifter circuit, and the voltage follower layout structure 5 may be used to fabricate a voltage follower of a level shifter circuit. The specific structures and functions of the processing section, the converting section and the voltage following device can be referred to the related descriptions of the foregoing embodiments.

In one embodiment of the present invention, a first well pattern WEL1 and a first circuit pattern CIR1 may be included in the processing portion layout structure 3, wherein the first circuit pattern CIR1 may be used to form a first circuit structure, and the first well pattern WEL1 may be used to form a first well, the first circuit structure being capable of implementing specific circuit logic and functions, at least a portion of the first circuit structure being disposed in the first well. Similarly, the conversion section layout structure 4 may include a second well pattern WEL2 and a second circuit pattern CIR2, wherein the second circuit pattern CIR2 may be used to form a second circuit structure, and the second well pattern WEL2 may be used to form a second well, the second circuit structure being capable of implementing specific circuit logics and functions, at least a part of the second circuit structure being disposed in the second well.

Alternatively, the first circuit pattern and the second circuit pattern may be layout patterns corresponding to various circuit structures based on various processes, for example, various transistor patterns, resistor patterns, capacitor patterns, and the like. In one embodiment of the present invention, the first circuit pattern may include a first CMOS (Complementary Metal-Oxide-Semiconductor) pattern, and the second circuit pattern may include a second CMOS pattern.

As can be seen from the foregoing embodiments, since the first well pattern WEL1 and the second well pattern WEL2 can be connected to the power supply pattern sharedvdsdst of the destination voltage domain through the first wiring pattern LINE1, the corresponding level shifter circuit does not need to be provided with a power supply of the source voltage domain, and thus, there is no need to consider the problem of well isolation between different voltage domains, that is, the first well pattern WEL1 and the second well pattern WEL2 can be separated by any small distance (as shown in fig. 7, for example) or even connected together without a distance (as shown in fig. 8, for example). Specifically, in fig. 8, the first well pattern WEL1 and the second well pattern WEL2 may be formed together and connected together in one piece without a space, so that a circuit area can be saved to the maximum extent.

Furthermore, a power supply VDDSRC of a source voltage domain is not required to be arranged in the corresponding level conversion circuit, metal wiring related to the VDDSRC can be effectively reduced, the circuit area is further saved, and the circuit integration level is improved. In addition, when the first well pattern WEL1 and the second well pattern WEL2 are connected to each other, they can be connected to the power supply VDDDST of the target voltage domain through the same contact hole and the same metal line, thereby further saving the contact hole area and the metal wiring area.

For example, referring to fig. 8 again, in an embodiment of the present invention, the first well pattern WEL1 may be provided with a contact hole pattern hole thereon, the first wiring pattern LINE1 at least partially covers the contact hole pattern hole, and the first well pattern WEL1 is connected to the second well pattern WEL 2. Of course, the contact hole pattern hole may be disposed on the second well pattern WEL 2. Thus, the first well pattern WEL1 and the second well pattern WEL2 are connected to the power supply VDDDST (not shown) of the destination voltage domain through the same contact hole and the same metal line, thereby further saving a contact hole area and a metal wiring area.

In an embodiment of the present invention, the voltage follower layout 5 may be a transistor layout, and the transistor layout may include a first pole pattern, a second pole pattern, and a third pole pattern; the first pole pattern may be connected to the fourth wiring pattern LINE4, the second pole pattern may be connected to the power pattern sharedddst of the destination voltage domain, and the third pole pattern may be connected to the first circuit pattern CIR 1.

Optionally, the fourth wiring pattern LINE4 may be a signal metal type wiring, and a LINE width of the signal metal type wiring may be smaller than a LINE width of the power supply metal type wiring, that is, a LINE width of the fourth wiring pattern LINE4 may be smaller than a preset LINE width threshold, so that an area of the metal wiring may be effectively reduced, and an integration level of the circuit may be further improved.

The effect of reducing the circuit area can be obviously seen from the layout corresponding to the level conversion circuit. For example, in an embodiment of the present invention, the partial layout of the level shifter circuit shown in fig. 3 may be as shown in fig. 9, and the partial layout of the level shifter circuit shown in fig. 1 in the prior art may be as shown in fig. 10. As can be seen from comparison between fig. 9 and fig. 10, the level shift circuit provided in the embodiment of the present invention omits the space between the N-well (NW) of the source voltage domain and the N-well of the destination voltage domain, connects the two NW into one, and also omits a metal line and a contact hole (TAP) required for connecting the source voltage domain power supply VDDSRC, thereby greatly reducing the circuit area (by about 50%), and effectively improving the circuit integration.

Further, the layout structure of the level shifter circuit provided by the embodiment of the present invention may further include a voltage regulation buffer layout structure, and the fourth wiring pattern LINE4 may extend from the source voltage domain and be sequentially connected to the voltage regulation buffer layout structure and the voltage follower layout structure, so as to stably introduce the signal of the source voltage domain into the level shifter circuit.

Accordingly, embodiments of the present invention also provide a standard cell, in which any one of the level shift circuits provided in one or more of the foregoing embodiments may be disposed; each level shift circuit may receive the signal to be shifted, and convert the signal to be shifted into a corresponding shifted signal, respectively, for output, so that corresponding beneficial technical effects may also be produced.

Optionally, in the standard cell provided in the embodiment of the present invention, the power voltages of the source voltage domains to which the signals to be converted received by the level conversion circuits belong may be the same or different; the power supply voltages of the destination voltage domains to which the converted signals output by the level conversion circuits belong are the same. That is, in the standard cell provided by the embodiment of the present invention, signals of a plurality of same or different source voltage domains may be converted into signals of the same destination voltage domain, for example, signals of power voltages of 1.0V, and 2.0V in the source voltage domain may be converted into signals of power voltages of 1.8V in the destination voltage domain, respectively. In this way, since the target voltage domains corresponding to the level shift circuits are the same, the wells in the standard cells do not need to be spaced by a predetermined distance, so that the area of the standard cells can be effectively reduced, and the integration level of the standard cells can be improved.

Optionally, in an embodiment of the present invention, the power voltages of the source voltage domains to which the signals to be converted received by the level shift circuits belong are the same, and the voltage follower devices of the level shift circuits may be connected to the same preset voltage, so as to further reduce the area of the metal wiring.

Accordingly, an embodiment of the present invention further provides a chip, where any one of the level shift circuits provided in the embodiment of the present invention is disposed in the chip, or any one of the standard units provided in the embodiment of the present invention is disposed in the chip, so that corresponding beneficial technical effects can also be produced.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.

In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (17)

1. A level shift circuit, comprising:

the processing part is used for logically inverting the signal to be converted to obtain an inverted signal to be converted, wherein the processing part is powered by a power supply of a target voltage domain through a preset voltage following device, and the voltage following device is used for applying preset voltage of a source voltage domain to the processing part under the driving of the power supply of the target voltage domain;

and the conversion part is respectively connected with the signal to be converted and the processing part and is used for outputting a converted signal according to the signal to be converted and the inverted signal to be converted, wherein the logic level of the signal to be converted belongs to the source voltage domain, the logic level of the converted signal belongs to the target voltage domain, and the conversion part is powered by a power supply of the target voltage domain.

2. The circuit according to claim 1, wherein the processing unit comprises an inverter, a first terminal of the inverter is connected to the signal to be converted, a second terminal of the inverter is connected to the converting unit, a third terminal of the inverter is connected to the voltage follower, and a fourth terminal of the inverter is grounded.

3. The circuit of claim 1, wherein the voltage follower device has a first terminal connected to the preset voltage, a second terminal connected to a power source of the destination voltage domain, and a third terminal connected to the processing unit, wherein a voltage of the third terminal is less than or equal to a voltage of the first terminal.

4. The level shift circuit of claim 3, wherein the voltage follower means comprises a transistor.

5. The level shift circuit of claim 4, wherein the level shift circuit is disposed on a P-type substrate, and the voltage follower device comprises an N-type transistor; or the level conversion circuit is arranged on an N-type substrate, and the voltage following device comprises a P-type transistor.

6. The circuit of claim 1, wherein a voltage stabilizing buffer is further disposed between the preset voltage of the destination voltage domain and the voltage follower.

7. A layout structure of a level shifter circuit, comprising:

the processing part layout structure, the conversion part layout structure and the voltage follower layout structure;

the processing part layout structure comprises a first well graph and a first circuit graph, and at least one part of the first circuit graph is positioned in the coverage range of the first well graph; the switching part layout structure comprises a second well graph and a second circuit graph, and at least one part of the second circuit graph is positioned in the coverage range of the second well graph; the spacing distance between the first trap graph and the second trap graph is smaller than a preset distance threshold value;

the first well pattern and the second well pattern are connected with a power supply pattern of a target voltage domain through a first wiring pattern; the first circuit pattern is connected with the voltage follower layout structure, and the voltage follower layout structure is connected with the power supply pattern of the target voltage domain through a second wiring pattern; the second circuit pattern is connected with the power supply pattern of the target voltage domain through a third wiring pattern; the voltage follower layout structure is also connected with a fourth wiring pattern, and the fourth wiring pattern extends from the source voltage domain.

8. The layout structure according to claim 7, wherein the voltage follower layout structure is a transistor layout structure.

9. The layout structure according to claim 8, wherein the transistor layout structure comprises a first pole pattern, a second pole pattern, a third pole pattern; the first pole pattern is connected to the fourth wiring pattern, the second pole pattern is connected to a power supply pattern of the destination voltage domain, and the third pole pattern is connected to the first circuit pattern.

10. The layout structure of claim 7, wherein a contact hole pattern is provided on said first well pattern or on said second well pattern, said first wiring pattern at least partially covers said contact hole pattern, and said first well pattern and said second well pattern are connected together.

11. The layout structure according to claim 7, wherein the first circuit pattern comprises a first CMOS pattern, and the second circuit pattern comprises a second CMOS pattern.

12. The layout structure according to claim 7, wherein the line width of the fourth wiring pattern is smaller than a preset line width threshold value.

13. The layout structure of claim 7, further comprising a voltage stabilization buffer layout structure, said fourth wiring pattern extending from said source voltage domain and being connected to said voltage stabilization buffer layout structure and said voltage follower layout structure in sequence.

14. A standard cell comprising at least one level shifting circuit of any one of claims 1-6; and each level conversion circuit receives the signal to be converted and converts the signal to be converted into a corresponding converted signal to be output.

15. The standard cell of claim 14, wherein the power supply voltages of the source voltage domains to which the signals to be converted received by the level conversion circuits belong are the same or different; the power supply voltages of the target voltage domains to which the converted signals output by the level conversion circuits belong are the same.

16. The standard cell of claim 14, wherein the voltage follower of each level shifter circuit is connected to the same predetermined voltage, and the voltage follower of each level shifter circuit receives the same power supply voltage of the source voltage domain to which each signal to be converted belongs.

17. A chip, characterized in that the chip is provided with a level shift circuit as claimed in any one of claims 1 to 6 or with a standard cell as claimed in any one of claims 14 to 16.

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