CN113991722B - Multi-input DC short-circuit ratio calculation method, device, storage medium and computing equipment - Google Patents

Abstract

The invention discloses a multi-feed direct current short circuit ratio calculation method, a device, a storage medium and calculation equipment.

Description

Multi-input DC short-circuit ratio calculation method, device, storage medium and computing equipment

Technical Field

The invention relates to a method, a device, a storage medium and a computing device for calculating a multi-input direct current short-circuit ratio, and belongs to the technical field of power system automation.

Background technique

With the construction of power grids, high-voltage direct current transmission has become an important form of regional interconnection and long-distance large-capacity power transmission. In many regions, a grid structure has been formed in which multiple DC high-power feeds are fed into the receiving AC power grid. The interaction between multi-feed DC transmission systems has a great impact on the safe and stable operation of the entire power grid. The electrical distance between multiple DC inverter stations in a multi-feed DC system is often small. Faults on the AC side can easily cause simultaneous commutation failures in multiple DC systems. When the voltage support capacity of the AC power grid is insufficient, the dynamic reactive power demand of DC will cause oscillation and hysteresis of DC power recovery, thereby increasing the risk of transient voltage instability and power angle instability in the system, threatening the safe operation of AC and DC power grids.

In practical engineering applications, the multi-infeed short circuit ratio (MISCR) is generally used to evaluate the supporting capacity of the AC system for the AC bus voltage of the DC converter station in the multi-infeed DC transmission system. The traditional multi-infeed DC short circuit ratio mainly calculates the multi-infeed short circuit ratio by establishing the equivalent circuit of the AC system through the Thevenin equivalent. As the scale of the power grid increases, when the power grid operation mode is adjusted, the calculation of the Thevenin equivalent circuit takes too long, and it cannot adapt to the fast calculation considering the N-1 line disconnection, and cannot meet the needs of fast analysis and decision-making in large-scale power grids.

Summary of the invention

The present invention provides a method, device, storage medium and computing equipment for calculating a multi-input DC short-circuit ratio, which solve the problems disclosed in the background technology.

In order to solve the above technical problems, the technical solution adopted by the present invention is:

A method for calculating a multi-input DC short-circuit ratio is provided, comprising:

Obtain the primary equipment model, telemetering information and telemetering information of the power grid;

Acquire a node admittance matrix of a power grid electrical island according to the primary equipment model, the telesignaling measurement information and the telemetry measurement information;

According to the node admittance matrix, a node impedance matrix in a ground state is calculated in a multi-threaded parallel manner;

Correcting the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state to obtain the node impedance matrix when the grid line N-1 is disconnected;

According to the node impedance matrix when the power grid line N-1 is disconnected, the multi-infeed DC short-circuit ratio considering the line N-1 is calculated.

The primary equipment model includes primary equipment component parameters and connection relationships between primary equipment components, and the telemetered measurement information includes transformer gear measurement information; according to the primary equipment model, the telemetered measurement information and the telemetered measurement information, the node admittance matrix of the power grid electrical island is obtained, and the specific process is:

According to the connection relationship between the telemetering measurement information and the primary equipment components, an electrical island-node-branch model of the power grid is obtained;

A node admittance matrix of the electrical island of the power grid is obtained according to the electrical island-node-branch model, the primary equipment component parameters and the transformer gear measurement information.

The elements in the node admittance matrix are stored in a sparse format based on an associative container, and non-zero elements and their indexes are stored.

According to the node admittance matrix, a node impedance matrix in the base state is calculated in a multi-threaded parallel manner. The specific process may be:

Performing LDU factor decomposition on the node admittance matrix to obtain a factor table;

According to the factor table, a node impedance matrix in a ground state is calculated in a multi-threaded parallel manner.

Perform LDU factor decomposition on the node admittance matrix to obtain a factor table, including:

Reordering the node numbers of the node admittance matrix using a minimum degree node sorting method;

The node admittance matrix after the node numbers are reordered is subjected to LDU factor decomposition to obtain a factor table.

The relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state are corrected to obtain the node impedance matrix when the grid line N-1 is disconnected. The specific process may be:

The branch addition method is used to correct the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state, so as to obtain the node impedance matrix when the power grid line N-1 is disconnected.

The formula for correcting the node impedance matrix elements in the base state is:

Among them, _Zij is the element of the i-th row and j-th column in the node impedance matrix in the base state; _Z′ij is the element after correction of _Zij ; _Zaa is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zbb is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zab is the element of the a-th row and b-th column in the node impedance matrix in the base state; _zab is the impedance of the disconnected line between node a and node b; _Zia is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zaj is the element of the a-th row and j-th column in the node impedance matrix in the base state; _Zbj is the element of the b-th row and j-th column in the node impedance matrix in the base state.

The formula for calculating the multi-infeed DC short-circuit ratio considering line N-1 is:

Where, BS _DC is the set of AC bus nodes of the DC converter station in the multi-infeed DC system, MSCR _i is the short-circuit ratio of the DC feed-in commutation bus of the i-th loop, U _i is the voltage of the commutation bus node i, P _di is the i-th DC transmission power, P _dj is the j-th DC transmission power, is the element in row i and column i in the node impedance matrix when line N-1 is disconnected,/> is the element in the i-th row and j-th column of the node impedance matrix when line N-1 is disconnected.

A multi-input DC short-circuit ratio calculation device is provided, comprising:

An acquisition module is used to acquire the primary equipment model, telemetering information and telemetering information of the power grid;

A node admittance matrix module, used for obtaining a node admittance matrix of a power grid electrical island according to the primary equipment model, the telesignaling measurement information and the telemetry measurement information;

A node impedance matrix module, used to calculate the node impedance matrix in a ground state in a multi-threaded parallel manner according to the node admittance matrix;

A correction module, used to correct the relevant elements involved in the multi-input DC short-circuit ratio calculation in the node impedance matrix under the base state, and obtain the node impedance matrix when the power grid line N-1 is disconnected;

The short-circuit ratio calculation module is used to calculate the multi-input DC short-circuit ratio considering line N-1 according to the node impedance matrix when the power grid line N-1 is disconnected.

The correction module is used to: adopt a branch addition method to correct the relevant elements involved in the multi-input DC short-circuit ratio calculation in the node impedance matrix in the base state, and obtain the node impedance matrix when the line N-1 is disconnected.

The formula of the correction element of the correction module is:

Among them, _Zij is the element of the i-th row and j-th column in the node impedance matrix in the base state; _Z′ij is the element after correction of _Zij ; _Zaa is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zbb is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zab is the element of the a-th row and b-th column in the node impedance matrix in the base state; _zab is the impedance of the disconnected line between node a and node b; _Zia is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zaj is the element of the a-th row and j-th column in the node impedance matrix in the base state; _Zbj is the element of the b-th row and j-th column in the node impedance matrix in the base state.

A storage medium is provided, which is a computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device executes a multi-input DC short-circuit ratio calculation method.

A computing device is provided, comprising one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing a multi-infeed DC short-circuit ratio calculation method.

The beneficial effects achieved by the present invention are as follows: based on a primary equipment model, telesignaling measurement information and telemetering measurement information, the present invention obtains a node admittance matrix of a power grid electrical island, and according to the node admittance matrix, a node impedance matrix in a ground state is solved in a multi-threaded parallel manner, thereby realizing fast calculation of the node impedance matrix in the ground state, correcting relevant elements involved in the calculation of multi-input DC short-circuit ratio in the node impedance matrix in the ground state, and obtaining the node impedance matrix in the case where line N-1 is disconnected, thereby realizing fast calculation of the multi-input DC short-circuit ratio considering line N-1.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a method for calculating a multi-input DC short-circuit ratio;

FIG2 is a flowchart of solving the node impedance matrix in the base state in a multi-threaded parallel manner;

FIG3 is a structural block diagram of a multi-input DC short-circuit ratio calculation device.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

As shown in FIG1 , the method for calculating the multi-input DC short-circuit ratio includes the following steps:

Step 1, obtaining the primary equipment model, telemetering measurement information and telemetering measurement information of the power grid;

Step 2, obtaining the node admittance matrix of the power grid electrical island according to the primary equipment model, telesignaling measurement information and telemetering measurement information;

Step 3, according to the node admittance matrix, a node impedance matrix in the base state is calculated in a multi-threaded parallel manner;

The node is an AC system bus node including a commutation bus node where a DC system feeds into an AC system;

Step 4, correcting the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state, and obtaining the node impedance matrix when the grid line N-1 is disconnected;

Step 5: Calculate the multi-infeed DC short-circuit ratio of line N-1 based on the node impedance matrix when the grid line N-1 is disconnected.

The above method obtains the node admittance matrix of the power grid electrical island based on the primary equipment model, telesignaling measurement information and telemetry measurement information. According to the node admittance matrix, the node impedance matrix in the ground state is solved in a multi-threaded parallel manner to realize the fast calculation of the node impedance matrix in the ground state. The relevant elements involved in the calculation of the multi-infeed DC short-circuit ratio in the node impedance matrix in the ground state are corrected to obtain the node impedance matrix when the line N-1 is disconnected, thereby realizing the fast calculation of the multi-infeed DC short-circuit ratio considering the line N-1.

The above-mentioned primary equipment models can be directly obtained from the grid model service of the dispatching control system, including the parameters of primary equipment components such as generators, transformers, AC lines, converters, capacitors, reactors, busbars, and the connection relationship between primary equipment components. The grid model service provided by the control system support platform can obtain the primary equipment model from the dispatching control system database. Through the grid model service, the grid model can be obtained across multiple levels of dispatching centers and dispatching systems, realizing wide-area acquisition of the grid model.

The above-mentioned telesignaling measurement information and telemetered measurement information can be directly obtained from the measurement service of the dispatching control system, and the power grid measurement information can be obtained across multiple levels of dispatching centers and dispatching systems to achieve wide-area acquisition of measurement information; among them, the telemetered measurement information includes transformer gear measurement information and DC pole power, and the telesignaling measurement information includes the telesignaling status of the circuit breaker and the disconnector, and the obtained measurement information is associated with the primary equipment model.

According to the primary equipment model, telemetering measurement information and telemetering measurement information, the node admittance matrix of the power grid electrical island is obtained. The specific process can be:

11) Based on the remote signaling measurement information and the connection relationship between the primary equipment components, perform network topology analysis to obtain the electrical island-node-branch model of the power grid;

In the actual normal operation of the power grid, the status of the circuit breaker and disconnector rarely changes. When the status of the circuit breaker and disconnector in this calculation has not changed compared with the telesignal status in the last calculation, there is no need to perform topological analysis; when only part of the telesignal status changes, only the local network topology analysis is performed according to the voltage level for the plant and station where the telesignal status changes to improve the calculation speed;

12) Obtain the node admittance matrix Y of the power grid electrical island according to the electrical island-node-branch model, primary equipment component parameters and transformer gear measurement information;

In order to improve the calculation speed, the elements in the node admittance matrix Y are stored in a sparse format based on an associative container, and only non-zero elements and their indexes are stored.

The sparse matrix structure defined based on the associative container map is defined as:

typedef std::map<int,float>SparseRowMap;

typedef std::map<int,SparseRowMap>SparseMatrixMap;

The SparseMatrixMap structure is used to store sparse matrices, where SparseRowMap sparsely stores a row of non-zero elements, the column number is represented by an int-type key index, and the sparse matrix non-zero elements are represented by float-type associated values.

Since the order of node numbers in the node admittance matrix directly affects the sparsity of the node admittance matrix factor table and has a direct impact on the computational efficiency, after obtaining the node admittance matrix, the minimum degree node sorting method is used according to the non-zero element structure to reorder the node numbers of the node admittance matrix.

The minimum degree node sorting method is used to reorder the node numbers to reduce the number of injected elements in the factor decomposition process. In the process of node number reordering, only the changes in the power grid network structure are processed, and the floating-point number operations in the simulated Gaussian elimination method are not performed.

The Gaussian elimination method is used to decompose the LDU factor of the reordered node admittance matrix to obtain the factor table. Then, based on the factor table, the node impedance matrix Z in the ground state is solved in a multi-threaded parallel manner.

When it is necessary to calculate the multi-infeed DC short-circuit ratio of multiple DC drop points and the multi-infeed DC short-circuit ratio when line N-1 is disconnected, since the solutions of each row/column of the node impedance matrix are independent of each other, multi-threaded parallel calculation of the node impedance matrix is adopted for large-scale power grids to improve the calculation speed of the node impedance matrix. The specific process is shown in Figure 2. Each thread uses the continuous back substitution method to calculate a row of values of Z, and the final results are aggregated into the node impedance matrix Z.

The disconnection of line N-1 means removing a branch from the power grid, which is equivalent to adding a negative impedance branch. Therefore, the branch addition method is used to modify some elements of the node impedance matrix in the base state to obtain the node impedance matrix when line N-1 is disconnected.

In the actual power grid, there are multiple high-voltage direct current transmission lines connected to the power grid structure in the same area. These DC systems with close electrical distances and the AC power grids they feed into form a multi-infeed DC system. In the actual DC system, there are multiple converter poles in the same converter station. The AC sides of different converter poles may be the same topological bus or different topological nodes. These nodes form a set BS _DC , that is, BS _DC represents the set of AC bus nodes of the DC converter station in the multi-infeed DC system. Since the calculation of the short-circuit ratio of the multi-infeed DC only involves the self-impedance and mutual impedance of each node in the set BS _DC , in order to improve the calculation speed, only the elements of the row where the nodes are located in the DC landing node set BS _DC in the node impedance matrix need to be corrected, and other elements do not need to be calculated.

Assuming that the end nodes of the disconnected line a-b (i.e., the line between node a and node b) are a and b respectively, the formula for correcting the node impedance matrix elements in the base state is:

Wherein, _Zij is the mutual impedance between node i and node j, which is the element of the i-th row and j-th column in the node impedance matrix in the base state; _Zi′ij is the element after the correction of _Zij ; _Zaa is the self-impedance of node a at the end of the disconnected line ab, which is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zibb is the self-impedance of node b at the end of the disconnected line ab, which is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node a and node b, which is the element of the a-th row and b-th column in the node impedance matrix in the base state; Zib is the disconnected line impedance between node a and node b; _Zia is the mutual impedance between node i and node a, which is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node i and node b, which is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node i and node b, which is the element of the i-th row and b-th column in the node impedance matrix in the base state; _aj is the mutual impedance between node a and node j, and is the element of the ath row and jth column in the node impedance matrix in the base state; Z _bj is the mutual impedance between node b and node j, and is the element of the bth row and jth column in the node impedance matrix in the base state.

It should be noted that the disconnection of line N-1 may cause the grid to be disconnected. Before correcting the node impedance elements, it is necessary to determine in advance whether the disconnection of line N-1 will cause the grid to be disconnected. If it causes the system to be disconnected, the topology analysis is re-performed to form the electrical island-node-branch model after the disconnection.

According to the node impedance matrix when the power grid line N-1 is disconnected, the multi-infeed DC short-circuit ratio considering line N-1 is calculated. The specific formula can be:

Where, BS _DC is the set of AC bus nodes of the DC converter station in the multi-infeed DC system, MSCR _i is the short-circuit ratio of the DC feed-in commutation bus of the i-th loop, U _i is the voltage of the commutation bus node i, P _di is the i-th DC transmission power, P _dj is the j-th DC transmission power, is the element in row i and column i in the node impedance matrix when line N-1 is disconnected,/> is the element in the i-th row and j-th column of the node impedance matrix when line N-1 is disconnected.

The above method realizes the rapid calculation of the node impedance matrix based on multi-threaded parallel mode. When the network structure is changed, the node impedance local correction method is used to realize the rapid calculation of the node impedance when the line N-1 is disconnected. This method only needs to calculate the self-impedance of the AC bus node of the DC converter station and the mutual impedance between the AC bus nodes of the converter station. There is no need to calculate all the elements of the node impedance matrix when the line N-1 is disconnected, which greatly reduces the amount of calculation, thereby improving the overall calculation speed of the multi-infeed DC short-circuit ratio of the large-scale power grid considering the line N-1.

In addition to being used for fast calculation of multi-input DC short-circuit ratio, the above method can also be extended to network analysis sensitivity calculation, short-circuit current calculation, network equivalence and other functions, and can be used to quickly solve the node impedance matrix.

Based on the same inventive concept, the embodiment of the present application further provides a multi-input DC short-circuit ratio calculation device, as shown in FIG3 , the multi-input DC short-circuit ratio calculation device comprises:

An acquisition module is used to acquire the primary equipment model, telemetering information and telemetering information of the power grid;

The node admittance matrix module is used to obtain the node admittance matrix of the electrical island of the power grid according to the primary equipment model, telesignaling measurement information and telemetering measurement information;

The node impedance matrix module is used to calculate the node impedance matrix in the base state in a multi-threaded parallel manner according to the node admittance matrix;

A correction module is used to correct the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix under the base state by using the branch addition method, so as to obtain the node impedance matrix under the condition that the grid line N-1 is disconnected;

The short-circuit ratio calculation module is used to calculate the multi-infeed DC short-circuit ratio considering line N-1 according to the node impedance matrix when the power grid line N-1 is disconnected.

Among them, the formula of the correction element of the correction module is:

Wherein, _Zij is the mutual impedance between node i and node j, which is the element of the i-th row and j-th column in the node impedance matrix in the base state; _Zi′ij is the element after the correction of _Zij ; _Zaa is the self-impedance of node a at the end of the disconnected line ab, which is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zibb is the self-impedance of node b at the end of the disconnected line ab, which is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node a and node b, which is the element of the a-th row and b-th column in the node impedance matrix in the base state; Zib is the disconnected line impedance between node a and node b; _Zia is the mutual impedance between node i and node a, which is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node i and node b, which is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zib is the mutual impedance between node i and node b, which is the element of the i-th row and b-th column in the node impedance matrix in the base state; _aj is the mutual impedance between node a and node j, and is the element of the ath row and jth column in the node impedance matrix in the base state; Z _bj is the mutual impedance between node b and node j, and is the element of the bth row and jth column in the node impedance matrix in the base state.

All relevant contents of each step involved in the embodiment of the multi-infeed DC short-circuit ratio calculation method corresponding to FIG. 1 can be referred to the functional description of the functional modules corresponding to the multi-infeed DC short-circuit ratio calculation device in the embodiment of the present application, and will not be repeated here.

The program of the multi-input DC short-circuit ratio calculation device in the embodiment of the present application can run independently and has nothing to do with the network analysis functions running in the dispatching automation system, such as state estimation, static safety analysis, and reactive voltage optimization functions, and does not affect the operation of the actual dispatching system production functions.

Based on the same inventive concept, an embodiment of the present application also provides a storage medium, which is a computer-readable storage medium that stores one or more programs, and the one or more programs include instructions. When the instructions are executed by a computing device, the computing device executes a multi-input DC short-circuit ratio calculation method.

Based on the same inventive concept, an embodiment of the present application also provides a computing device, comprising one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing a multi-input DC short-circuit ratio calculation method.

Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

The present invention is described with reference to the flowchart and/or block diagram of the method, device (system), and computer program product according to the embodiment of the present invention. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the process and/or box in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.

Claims (11)

1. A method for calculating a multi-input DC short-circuit ratio, characterized by comprising: Obtain the primary equipment model, telemetering information and telemetering information of the power grid; Acquire a node admittance matrix of a power grid electrical island according to the primary equipment model, the telesignaling measurement information and the telemetry measurement information; The node numbers of the node admittance matrix are reordered by using a minimum degree node sorting method; wherein, in the process of reordering the node numbers, only the changes in the power grid network structure are processed, and the floating point number calculation in the simulated Gaussian elimination method is not performed; Performing LDU factor decomposition on the node admittance matrix after the node numbers are reordered to obtain a factor table; According to the factor table, a node impedance matrix in a base state is calculated in a multi-threaded parallel manner; Correcting the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state to obtain the node impedance matrix when the grid line N-1 is disconnected; According to the node impedance matrix when the power grid line N-1 is disconnected, the multi-infeed DC short-circuit ratio considering the line N-1 is calculated. 2. The multi-infeed DC short-circuit ratio calculation method according to claim 1 is characterized in that the primary device model includes primary device component parameters and connection relationships between primary device components, and the telemetry measurement information includes transformer gear measurement information; according to the primary device model, the telesignal measurement information and the telemetry measurement information, the node admittance matrix of the power grid electrical island is obtained, and the specific process is: According to the connection relationship between the telemetering measurement information and the primary equipment components, an electrical island-node-branch model of the power grid is obtained; A node admittance matrix of the electrical island of the power grid is obtained according to the electrical island-node-branch model, the primary equipment component parameters and the transformer gear measurement information. 3. The multi-input DC short-circuit ratio calculation method according to claim 1 or 2, characterized in that the elements in the node admittance matrix are stored in a sparse format based on an associative container, and non-zero elements and their indexes are stored. 4. The method for calculating the short-circuit ratio of a multi-infeed DC power grid according to claim 1, characterized in that the relevant elements involved in the calculation of the short-circuit ratio of a multi-infeed DC power grid in the node impedance matrix in the base state are corrected to obtain the node impedance matrix when the power grid line N-1 is disconnected, and the specific process is as follows: The branch addition method is adopted to correct the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state, so as to obtain the node impedance matrix in the case where the line N-1 is disconnected. 5. The method for calculating the multi-input DC short-circuit ratio according to claim 4, characterized in that the formula for element correction is: Among them, _Zij is the element of the i-th row and j-th column in the node impedance matrix in the base state; _{Zi′j is} the element after correction of _Zij ; _Zaa is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zbb is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zab is the element of the a-th row and b-th column in the node impedance matrix in the base state; _zab is the impedance of the disconnected line between node a and node b; _Zia is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zaj is the element of the a-th row and j-th column in the node impedance matrix in the base state; _Zbj is the element of the b-th row and j-th column in the node impedance matrix in the base state. 6. The method for calculating the short-circuit ratio of a multi-infeed DC circuit according to claim 1, wherein the formula for calculating the short-circuit ratio of a multi-infeed DC circuit considering line N-1 is: Where, BS _DC is the set of AC bus nodes of the DC converter station in the multi-infeed DC system, MSCR _i is the short-circuit ratio of the DC feed-in commutation bus of the i-th loop, U _i is the voltage of the commutation bus node i, P _di is the i-th DC transmission power, P _dj is the j-th DC transmission power, is the element in row i and column i in the node impedance matrix when line N-1 is disconnected,/> is the element in the i-th row and j-th column of the node impedance matrix when line N-1 is disconnected. 7. A multi-input DC short-circuit ratio calculation device, characterized in that it comprises: An acquisition module is used to acquire the primary equipment model, telemetering information and telemetering information of the power grid; A node admittance matrix module, used for obtaining a node admittance matrix of a power grid electrical island according to the primary equipment model, the telesignaling measurement information and the telemetry measurement information; The node impedance matrix module adopts the minimum degree node sorting method to reorder the node numbers of the node admittance matrix; performs LDU factor decomposition on the node admittance matrix after the node numbers are reordered to obtain a factor table; and calculates the node impedance matrix in the base state in a multi-threaded parallel manner according to the factor table; wherein, in the process of reordering the node numbers, only the changes in the power grid network structure are processed, and the floating point number calculation in the simulated Gaussian elimination method is not performed; A correction module, used to correct the relevant elements involved in the multi-input DC short-circuit ratio calculation in the node impedance matrix under the base state, and obtain the node impedance matrix when the power grid line N-1 is disconnected; The short-circuit ratio calculation module is used to calculate the multi-input DC short-circuit ratio considering line N-1 according to the node impedance matrix when the power grid line N-1 is disconnected. 8. The multi-infeed DC short-circuit ratio calculation device according to claim 7 is characterized in that the correction module is used to: adopt a branch addition method to correct the relevant elements involved in the multi-infeed DC short-circuit ratio calculation in the node impedance matrix in the base state to obtain the node impedance matrix when the line N-1 is disconnected. 9. The multi-input DC short-circuit ratio calculation device according to claim 8, characterized in that the formula of the correction element of the correction module is: Among them, _{Zij is} the element of the i-th row and j-th column in the node impedance matrix in the base state; _Zi′j is the element after correction of _Zij ; _Zaa is the element of the a-th row and a-th column in the node impedance matrix in the base state; _Zbb is the element of the b-th row and b-th column in the node impedance matrix in the base state; _Zab is the element of the a-th row and b-th column in the node impedance matrix in the base state; _zab is the impedance of the disconnected line between node a and node b; _Zia is the element of the i-th row and a-th column in the node impedance matrix in the base state; _Zib is the element of the i-th row and b-th column in the node impedance matrix in the base state; _Zaj is the element of the a-th row and j-th column in the node impedance matrix in the base state; _Zbj is the element of the b-th row and j-th column in the node impedance matrix in the base state. 10. Storage medium, characterized in that: the storage medium is a computer-readable storage medium storing one or more programs, and the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device executes any one of the methods according to claims 1 to 6. 11. A computing device, comprising: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the methods according to claims 1 to 6.