CN113990809B - Packaging structure, circuit board assembly and electronic equipment - Google Patents
Packaging structure, circuit board assembly and electronic equipment Download PDFInfo
- Publication number
- CN113990809B CN113990809B CN202111548243.5A CN202111548243A CN113990809B CN 113990809 B CN113990809 B CN 113990809B CN 202111548243 A CN202111548243 A CN 202111548243A CN 113990809 B CN113990809 B CN 113990809B
- Authority
- CN
- China
- Prior art keywords
- substrate
- package
- supporting part
- support portion
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Casings For Electric Apparatus (AREA)
Abstract
Description
技术领域technical field
本发明涉及半导体封装技术领域,特别是涉及一种封装结构、电路板组件和电子设备。The present invention relates to the technical field of semiconductor packaging, in particular to a packaging structure, a circuit board assembly and an electronic device.
背景技术Background technique
随着科学技术的快速发展,对芯片要求越来越高,封装尺寸和芯片功耗都在快速增加。随着封装尺寸增加,封装翘曲随之增大,封装翘曲不仅会使封装内部应力增加,还会导致芯片与电路板焊接不良,产生如连锡、虚焊等问题。而芯片功耗增加使芯片产生并散发出更多的热量,对芯片封装散热提出了更高的要求。With the rapid development of science and technology, the requirements for chips are getting higher and higher, and the package size and chip power consumption are increasing rapidly. As the package size increases, the package warpage increases. The package warpage will not only increase the internal stress of the package, but also lead to poor soldering between the chip and the circuit board, resulting in problems such as tin connection and virtual soldering. The increase in chip power consumption causes the chip to generate and dissipate more heat, which puts forward higher requirements for the heat dissipation of the chip package.
发明内容SUMMARY OF THE INVENTION
本发明实施例提供一种封装结构、电路板组件和电子设备,用以有效控制封装结构的翘曲,且不影响电子元器件的散热,确保封装结构的散热效率。Embodiments of the present invention provide a package structure, a circuit board assembly and an electronic device, which are used to effectively control the warpage of the package structure without affecting the heat dissipation of the electronic components and ensure the heat dissipation efficiency of the package structure.
第一方面,本发明实施例提供一种封装结构,包括:In a first aspect, an embodiment of the present invention provides a packaging structure, including:
基板,所述基板具有相对设置的第一表面和第二表面;a substrate, the substrate has a first surface and a second surface disposed oppositely;
电子元器件,所述电子元器件与所述基板的第一表面连接;an electronic component connected to the first surface of the substrate;
封装盖体,所述封装盖体包括顶盖、第一支撑部和第二支撑部,所述顶盖通过所述第一支撑部和所述第二支撑部连接于所述基板的第一表面上,所述第一支撑部和所述第二支撑部之间限定出第一空腔,所述顶盖在对应所述电子元器件的位置设置有开孔,所述电子元器件至少部分从所述开孔中露出。a package cover, the package cover includes a top cover, a first support part and a second support part, the top cover is connected to the first surface of the substrate through the first support part and the second support part On the top, a first cavity is defined between the first support part and the second support part, and the top cover is provided with an opening at a position corresponding to the electronic component, and the electronic component is at least partially exposed in the opening.
第二方面,本发明实施例提供一种电路板组件,所述电路板组件包括电路板和如上第一方面所述的封装结构,所述封装结构与所述电路板连接。In a second aspect, an embodiment of the present invention provides a circuit board assembly, which includes a circuit board and the package structure according to the first aspect above, where the package structure is connected to the circuit board.
第三方面,本发明实施例提供一种电子设备,所述电子设备包括如上第二方面所述的电路板组件。In a third aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes the circuit board assembly described in the second aspect above.
本发明实施例的方案,封装结构包括基板、电子元器件和封装盖体,其中,所述基板具有相对设置的第一表面和第二表面,所述电子元器件与所述基板的第一表面连接,所述封装盖体包括顶盖、第一支撑部和第二支撑部,所述顶盖通过所述第一支撑部和所述第二支撑部连接于所述基板的第一表面上,可以令顶盖在基板上的覆盖面积最大化,通过第二支撑部向第一支撑部提供力矩,从而控制基板的翘曲,以减小封装结构翘曲变形,防止因翘曲所造成的问题及损坏,并同时提高封装结构的产能与稳定性。所述第一支撑部和所述第二支撑部之间限定出第一空腔,该第一空腔为基板上除上述电子元器件之外的元器件提供了容置空间,便于诸如电容等其他元器件贴装在基板上,对基板上元器件较多的系统级封装(System In a Package,SiP)有很强的适用性,并且可以减轻封装重量;所述顶盖在对应所述电子元器件的位置设置有开孔,所述电子元器件从所述开孔中露出,电子元器件可与空气或散热器直接接触,保证了封装结构的散热效果。In the solution of the embodiment of the present invention, the package structure includes a substrate, an electronic component, and a package cover, wherein the substrate has a first surface and a second surface disposed opposite to each other, and the electronic component and the first surface of the substrate connection, the package cover body includes a top cover, a first support portion and a second support portion, the top cover is connected to the first surface of the substrate through the first support portion and the second support portion, The coverage area of the top cover on the substrate can be maximized, and the second supporting part can provide torque to the first supporting part, so as to control the warpage of the substrate, so as to reduce the warpage deformation of the package structure and prevent the problems caused by warpage. and damage, while improving the productivity and stability of the package structure. A first cavity is defined between the first support part and the second support part, and the first cavity provides a accommodating space for components on the substrate other than the above-mentioned electronic components, which is convenient for capacitors, etc. Other components are mounted on the substrate, which has strong applicability to the System In a Package (SiP) with many components on the substrate, and can reduce the weight of the package; the top cover is corresponding to the electronic The positions of the components are provided with openings, the electronic components are exposed from the openings, and the electronic components can be in direct contact with the air or the heat sink, thereby ensuring the heat dissipation effect of the package structure.
附图说明Description of drawings
图1a和图1b为相关技术中的一种封装结构的结构示意图;1a and 1b are schematic structural diagrams of a packaging structure in the related art;
图2a和图2b为相关技术中的另一种封装结构的结构示意图;2a and 2b are schematic structural diagrams of another packaging structure in the related art;
图3a-图3c为本发明的一个实施例提供的封装结构的结构示意图;3a-3c are schematic structural diagrams of a packaging structure provided by an embodiment of the present invention;
图4a-图4c为本发明的另一个实施例提供的封装结构的结构示意图;4a-4c are schematic structural diagrams of a package structure provided by another embodiment of the present invention;
图5为本发明的另一个实施例提供的封装结构的结构示意图;5 is a schematic structural diagram of a packaging structure provided by another embodiment of the present invention;
图6a和图6b为本发明的另一个实施例提供的封装结构的结构示意图;6a and 6b are schematic structural diagrams of a package structure provided by another embodiment of the present invention;
图7为在不同类型盖板下的基板翘曲度、电子元器件热阻的对比分析表格。Figure 7 is a comparative analysis table of substrate warpage and thermal resistance of electronic components under different types of cover plates.
附图标记:Reference number:
1-封装结构;10-基板;20-电子元器件;30-加强环;40-盖板;41-导热胶;1-Package structure; 10-Substrate; 20-Electronic components; 30-Reinforcing ring; 40-Cover plate; 41-Conductive adhesive;
50-封装盖体;510-顶盖;511-开孔;521-第一支撑部;522-第二支撑部;5221-支撑脚;523-第三支撑部;524-缺口;530-第一空腔;531-第二空腔;50-package cover; 510-top cover; 511-hole; 521-first support part; 522-second support part; 5221-support foot; 523-third support part; 524-notch; 530-first cavity; 531-second cavity;
61-底部填充胶;62-凸起触点;63-连接部。61-underfill; 62-raised contacts; 63-connection.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
应了解,在本发明实施例的描述中,如果有描述到“第一”、“第二”等只是用于区分技术特征为目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。“至少一个”是指一个或者多个,“多个”是指两个或两个以上。“和/或”,描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示单独存在A、同时存在A和B、单独存在B的情况。其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项”及其类似表达,是指的这些项中的任意组,包括单项或复数项的任意组。例如,a、b和c中的至少一项可以表示:a,b,c,a和b,a和c,b和c,或者,a和b和c,其中a,b,c可以是单个,也可以是多个。It should be understood that in the description of the embodiments of the present invention, if there is a description of "first", "second", etc., it is only for the purpose of distinguishing technical features, and should not be understood as indicating or implying relative importance or implicitly indicating that The number of indicated technical features or implicitly indicates the order of the indicated technical features. "At least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. where A and B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one of the following" and similar expressions, refers to any group of such items, including any group of single or plural items. For example, at least one of a, b, and c may represent: a, b, c, a and b, a and c, b and c, or, a and b and c, where a, b, and c may be a single , or more than one.
在本发明的描述中,术语“内”、“外”、“纵向”、“横向”、“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明而不是要求本发明必须以特定的方位构造和操作,因此不应当理解为对本发明的限制。In the description of the present invention, the orientation or positional relationship indicated by the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc. are based on the drawings The orientation or positional relationship shown is only for the convenience of describing the present invention rather than requiring the present invention to be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.
另外,本领域普通技术人员应当可以意识到,本发明实施例描述的连接包括直接连接和通过中间部件相连的间接连接。In addition, those of ordinary skill in the art should appreciate that the connections described in the embodiments of the present invention include direct connections and indirect connections through intermediate components.
随着科学技术的快速发展,对芯片要求越来越高,封装尺寸和芯片功耗都在快速增加。随着封装尺寸增加,封装翘曲几率随之增大,封装翘曲不仅会使封装内部应力增加,还会导致芯片与电路板焊接不良,产生如连锡、虚焊等问题。而芯片功耗增加使芯片产生并散发出更多的热量,对芯片封装散热提出了更高的要求。With the rapid development of science and technology, the requirements for chips are getting higher and higher, and the package size and chip power consumption are increasing rapidly. As the package size increases, the probability of package warpage increases. Package warpage will not only increase the internal stress of the package, but also lead to poor soldering between the chip and the circuit board, resulting in problems such as tin connection and virtual soldering. The increase in chip power consumption causes the chip to generate and dissipate more heat, which puts forward higher requirements for the heat dissipation of the chip package.
请参见图1a和图1b,图1a和图1b分别示出了相关技术中的一种封装结构的俯视图和剖面图。该封装结构包括:基板10、电子元器件20和加强环30(Stiffener ring),其中,电子元器件20和加强环30均设置在基板10的上表面,加强环30为环状结构,电子元器件20从加强环30的中空部位露出。图1a和图1b所示的封装结构通过设置在基板10上的加强环30来控制封装翘曲,这种封装结构,电子元器件20可与空气或散热器直接接触,散热性较好,加强环30对封装翘曲的控制能力较弱。Please refer to FIG. 1a and FIG. 1b, which respectively show a top view and a cross-sectional view of a package structure in the related art. The package structure includes: a
请参见图2a和图2b,图2a和图2b分别示出了相关技术中的另一种封装结构的俯视图和剖面图。该封装结构包括:基板10、电子元器件20和盖板40(Lid),其中,电子元器件20和盖板40均设置在基板10的上表面,盖板40和电子元器件20之间还设置有导热胶41(Tim胶),盖板40的下表面具有环状的支撑部,盖板40通过环状的支撑部与基板10连接。图2a和图2b所示的封装结构通过设置在基板10上的盖板40来控制封装翘曲,这种封装结构对封装翘曲控制相对较好,但是在电子元器件20和空气/散热器之间增加了阻挡(导热胶41和盖板40),导致热量传输的热阻增大,使得封装结构的散热能力较差。Please refer to FIG. 2a and FIG. 2b. FIG. 2a and FIG. 2b respectively show a top view and a cross-sectional view of another package structure in the related art. The package structure includes: a
为了克服相关技术的封装结构存在的缺点,本发明实施例提供了一种封装结构、电路板组件和电子设备,用以有效控制封装结构的翘曲,且不影响电子元器件的散热,确保封装结构的散热效率。In order to overcome the shortcomings of the packaging structure of the related art, the embodiments of the present invention provide a packaging structure, a circuit board assembly and an electronic device, which are used to effectively control the warpage of the packaging structure without affecting the heat dissipation of the electronic components and ensure the packaging structure. heat dissipation efficiency of the structure.
实施例1Example 1
请参见图3a、图3b和图3c,图3a、图3b和图3c示出了本发明的一个实施例提供的封装结构1的结构示意图。其中,图3a为封装结构1的俯视结构示意图,图3b为图3a中Ⅰ处的剖面结构示意图,图3c为图3b中Ⅱ处的剖面结构示意图。在图3a、图3b和图3c所示的实施例中,封装结构1包括:基板10、电子元器件20和封装盖体50。其中,所述基板10具有相对设置的第一表面和第二表面,所述电子元器件20与所述基板10的第一表面连接,所述封装盖体50包括顶盖510、第一支撑部521和第二支撑部522,所述顶盖510通过所述第一支撑部521和所述第二支撑部522连接于所述基板10的第一表面上,所述第一支撑部521和所述第二支撑部522之间限定出第一空腔530,所述顶盖510在对应所述电子元器件20的位置设置有开孔511,所述电子元器件20至少部分从所述开孔511中露出。Please refer to FIG. 3a, FIG. 3b, and FIG. 3c. FIG. 3a, FIG. 3b, and FIG. 3c are schematic structural diagrams of a package structure 1 provided by an embodiment of the present invention. 3a is a schematic top view of the package structure 1, FIG. 3b is a schematic cross-sectional structure at I in FIG. 3a, and FIG. 3c is a cross-sectional structure at II in FIG. 3b. In the embodiments shown in FIGS. 3 a , 3 b and 3 c , the package structure 1 includes: a
可以理解的是,基板10为电子元器件20封装的载体,起到为封装的电子元器件20提供电连接、保护、支撑、散热、组装等作用。It can be understood that the
示例性的,本发明实施例的封装结构1可以应用于电路板组件(Printed CircuitBoard Assembly,PCBA)中,封装结构1的基板10的第一表面用于安装电子元器件20和封装盖体50,封装结构1的基板10的第二表面用于与电路板(Printed Circuit Board,PCB)连接,封装结构1和电路板组成上述电路板组件。Exemplarily, the package structure 1 of the embodiment of the present invention can be applied to a circuit board assembly (Printed Circuit Board Assembly, PCBA). The first surface of the
电路板组件具体包括封装结构1和电路板,封装结构1以基板10的第二表面与电路板连接。The circuit board assembly specifically includes a package structure 1 and a circuit board, and the package structure 1 is connected to the circuit board through the second surface of the
具体实现时,可以在基板10的第二表面设置多个连接部63,这里的多个连接部63均用以与电路板电连接,多个连接部63在基板10的第二表面间隔分布。示例性的,连接部63可以为焊球(Solder ball),焊球可以为锡、铜等金属材料制成。连接部63也可以设置为金属连接柱(例如铜柱)。本发明实施例提供对连接部63的具体形式不作过多限制。本发明实施例提供的封装结构1通过多个连接部63与电路板电连接,实现封装结构1与电路板的电气互联,进而实现电路板组件的组装。In specific implementation, a plurality of connection parts 63 may be provided on the second surface of the
可以理解的是,本领域技术人员能够根据实际需求选择电子元器件20的种类。示例性的,电子元器件20可以是有源器件,这里,有源器件包括晶粒(Die)或者其他需要外加电源才能工作的器件/元件,需了解,在半导体封装领域,“晶粒”、“芯片”或“裸芯片”可以看作同义词。电子元器件20也可以是无源器件,这里,无源器件包括电容、电感、混频器、滤波器等不需要外加电源的器件/元件。在本发明实施例中,以电子元器件20为晶粒进行示例性说明。It can be understood that, those skilled in the art can select the type of the
在一个具体的实施例中,如图3b所示,电子元器件20通过多个凸起触点62(Bump)以倒装方式焊接在基板10的第一表面上。通过凸起触点62可以将电子元器件20的线路引出,实现电子元器件20与基板10上的其它有源/无源器件之间的电连接。In a specific embodiment, as shown in FIG. 3 b , the
可选的,多个所述凸起触点62之间设置有底部填充胶61(Underfill)。具体实现时,可以在电子元器件20与基板10连接的表面添加底部填充胶61,将电子元器件20倒装焊接于基板10时,由于虹吸作用,融化后的底部填充胶61流入凸起触点62底部,从而把凸起触点62完全包裹起来,起到保护凸起触点62的作用。Optionally, an underfill 61 (Underfill) is disposed between the plurality of the raised
可以理解的是,如图3a所示,本发明实施例描述的封装盖体50在对应电子元器件20的位置设置有开孔511,这样,当将封装盖体50连接至基板10的第一表面时,电子元器件20可以从封装盖体50的开孔511中露出。通过该开孔511,电子元器件20能够与空气或散热器直接接触,使得电子元器件20产生的热量便于传递扩散,从而增强了封装结构的散热性。It can be understood that, as shown in FIG. 3 a , the
可以理解的是,封装盖体50的开孔511可以采用不同的形状,例如,可以是圆形开孔、方形开孔或者椭圆形开孔,开孔511的尺寸可以基于电子元器件20进行适配。本发明实施例对于开孔511的具体形状和尺寸,不做具体限定。It can be understood that the
可以理解的是,本发明实施例描述的封装盖体50在用以与基板10相连的表面上设有挖空部分,具体实现时,可以预先设计好挖空区的形状,然后按照挖空区的形状对封装盖体50进行挖空,得到上述挖空部分。并且,在将封装盖体50的表面挖空之后,可以在封装盖体50的表面上形成第一支撑部521和第二支撑部522,如图3b和图3c所示,第一支撑部521和第二支撑部522之间是具有间隔的,顶盖510连接在第一支撑部521和第二支撑部522的上方,第一支撑部521和第二支撑部522之间为环形的第一空腔530。It can be understood that the
示例性的,第一支撑部521设置于所述顶盖510的外边缘区域,所述第二支撑部522设置于所述开孔511的边缘区域。Exemplarily, the
可以理解的是,在封装盖体50的结构中,顶盖510通过第一支撑部521和第二支撑部522架设在基板10的上方,第一支撑部521和第二支撑部522之间限定出第一空腔530,该第一空腔530在基板10的第一表面上为除上述电子元器件20之外的元器件提供了容置空间,对基板10上元器件较多的系统级封装(system in package,SiP)有很强的适用性,并且有利于减轻封装结构1的封装重量。It can be understood that, in the structure of the
具体实现时,可以预先设计挖空区的形状为包围开孔511的环形形状,然后按照预先设计的环形形状对封装盖体50进行挖空,封装盖体50经过挖空处理后,表面形成两个环状结构的支撑部,两个支撑部之间的部分即为顶盖510。这里,两个支撑部即为第一支撑部521和第二支撑部522,第一支撑部521位于顶盖510的外边缘区域,第二支撑部522位于开孔511的边缘区域。In specific implementation, the shape of the hollow area can be pre-designed to be an annular shape surrounding the
示例性的,第一支撑部521可以是方形环、圆形环、椭圆形环等环状结构,一般来说,第一支撑部521只需要与基板10适配即可,对于具体的环形在本发明实施例中不做具体限定。Exemplarily, the
示例性的,第二支撑部522可以是方形环、圆形环、椭圆形环等环状结构,一般来说,第二支撑部522只需要与开孔511适配即可,对于具体的环形在本发明实施例中不做具体限定。Exemplarily, the
可以理解的是,第一支撑部521和第二支撑部522可以采用不同的环状结构,例如,第一支撑部521为方形环状,第二支撑部522为圆形环状。当然,第一支撑部521和第二支撑部522也可以采用相同的环状结构,例如,第一支撑部521和第二支撑部522均为方形环状。It can be understood that the
可以理解的是,所述第一支撑部521和所述第二支撑部522分别粘接于所述基板10的第一表面上。具体的,可以通过粘接胶将第一支撑部521和第二支撑部522分别与基板10的第一表面粘接固定,如此,在第一支撑部521与基板10的第一表面之间、第二支撑部522与基板10的第一表面之间分别形成有粘接层。It can be understood that, the
实施例2Example 2
请参见图4a、图4b和图4c,图4a、图4b和图4c示出了本发明的一个实施例提供的封装结构1的结构示意图。其中,图4a为封装结构1的俯视结构示意图,图4b为图4a中Ⅲ处的剖面结构示意图,图4c为图4b中Ⅳ处的剖面结构示意图。在图4a-图4c所示的实施例中,封装结构1包括:基板10、电子元器件20和封装盖体50。其中,所述基板10具有相对设置的第一表面和第二表面,所述电子元器件20与所述基板10的第一表面连接,所述封装盖体50包括顶盖510、第一支撑部521、第二支撑部522和第三支撑部523,所述顶盖510通过第一支撑部521、第二支撑部522和第三支撑部523连接于所述基板10的第一表面上,所述顶盖510在对应所述电子元器件20的位置设置有开孔511,所述电子元器件20至少部分从所述开孔511中露出。Please refer to FIG. 4a, FIG. 4b and FIG. 4c. FIG. 4a, FIG. 4b and FIG. 4c are schematic structural diagrams of the package structure 1 provided by an embodiment of the present invention. 4a is a schematic top view of the package structure 1, FIG. 4b is a schematic cross-sectional structure at III in FIG. 4a, and FIG. 4c is a cross-sectional structure at IV in FIG. 4b. In the embodiment shown in FIGS. 4 a to 4 c , the package structure 1 includes: a
相比图3a-图3c所示的实施例,在图4a-图4c所示的实施例中,封装盖体50在第一支撑部521和第二支撑部522之间还设置有第三支撑部523,第一支撑部521、第二支撑部522和第三支撑部523相间隔设置,所述第一支撑部521和所述第二支撑部522之间限定出第一空腔530,第三支撑部523在所述第一空腔530内限定出至少两个第二空腔531。例如,在图4a-图4c所示的实施例中,第一支撑部521、第二支撑部522和第三支撑部523均为环状结构,第一支撑部521、第二支撑部522和第三支撑部523将封装盖体50用以与基板10连接的表面划分为两个环形的第二空腔531。Compared with the embodiment shown in FIGS. 3 a to 3 c , in the embodiment shown in FIGS. 4 a to 4 c , the
封装盖体50控制翘曲的具体原理是通过第二支撑部522经第三支撑部523向第一支撑部521提供力矩,有利于将封装结构的应力分散,从而有效减小封装结构翘曲,防止因翘曲所造成的问题及损坏,并同时提高封装结构的产能与稳定性。The specific principle of controlling the warpage of the
可以理解,具体实现过程中,在保证除电子元器件20之外的其它元器件具有足够的装配空间的前提下,可以适当地增加封装盖体50的支撑部的数量,例如,第三支撑部523的数量可以设置为多个,并且可以根据实际需要调整支撑部之间的位置距离。It can be understood that, in the specific implementation process, on the premise of ensuring that other components except the
需说明的是,在图4a-图4c所示的实施例中,电子元器件20与基板10的具体连接方式、封装盖体50与基板10的具体连接方式、封装结构1与电路板的连接方式、封装盖体50的制作方式等均可参照图3a-图3c所示实施例的相关说明,在此不再赘述。It should be noted that, in the embodiments shown in FIGS. 4 a to 4 c , the specific connection method between the
实施例3Example 3
请参照图5,图5示出了本发明的另一个实施例提供的封装结构1的横向剖面结构示意图。需说明的是,图5所示实施例的封装结构1的俯视结构和纵向剖面结构可以对应参照图3a、图3b所示实施例的结构,故在此省略。图5所示实施例的封装结构1包括:基板10、电子元器件20和封装盖体50。其中,所述基板10具有相对设置的第一表面和第二表面,所述电子元器件20与所述基板10的第一表面连接,所述封装盖体50包括顶盖510、第一支撑部521和第二支撑部522,所述顶盖510通过所述第一支撑部521和所述第二支撑部522连接于所述基板10的第一表面上,所述第一支撑部521和所述第二支撑部522之间限定出第一空腔530,所述顶盖510在对应所述电子元器件20的位置设置有开孔511,所述电子元器件20至少部分从所述开孔511中露出。在图5所示的实施例中,第一支撑部521和第二支撑部522均为环状结构,第一支撑部521设置有隔断环状的所述第一支撑部521的缺口524,第二支撑部522同样设置有隔断环状的所述第二支撑部522的缺口524,在本发明实施例中,缺口524起到为元器件走线提供走线空间的作用。例如,对于带光电模块的电子元器件20,往往需要引出线缆,为此,通过在第一支撑部521、第二支撑部522设置缺口524,从而为引出线缆提供了走线的空间。Please refer to FIG. 5 , which is a schematic cross-sectional structure diagram of a package structure 1 provided by another embodiment of the present invention. It should be noted that the top-view structure and longitudinal cross-sectional structure of the package structure 1 of the embodiment shown in FIG. 5 may correspond to the structures of the embodiments shown in FIGS. 3 a and 3 b , so they are omitted here. The package structure 1 of the embodiment shown in FIG. 5 includes: a
可以理解的是,第一支撑部521和第二支撑部522对应的缺口524数量为至少一个。需说明的是,图5所示的实施例中,第一支撑部521、第二支撑部522上的缺口524数量以及缺口524位置为示例性的,具体实现时,可以根据实际需要缺口524数量和缺口524位置进行适应性的调整。当然,缺口524也可以仅存在于第一支撑部521或者第二支撑部522,例如,只有位于第一空腔530中的元器件需要引出线缆,此时,只需在第一支撑部521开设缺口524即可;又例如,只有电子元器件20需要引出线缆,且线缆无需引至基板10之外,此时,只需在第二支撑部522开设缺口524即可。本发明实施例对缺口524的具体设置方式不作过多限定。It can be understood that the number of the
需说明的是,在图5所示的实施例中,电子元器件20与基板10的具体连接方式、封装盖体50与基板10的具体连接方式、封装结构1与电路板的连接方式、封装盖体50的制作方式等均可参照图3a-图3c所示实施例的相关说明,在此不再赘述。It should be noted that, in the embodiment shown in FIG. 5 , the specific connection method between the
实施例4Example 4
请参见图6a,图6a示出了本发明的另一个实施例提供的封装结构1的横向剖面结构示意图。需说明的是,图6a所示实施例的封装结构1的俯视结构和纵向剖面结构可以对应参照图3a、图3b所示实施例的结构,故在此省略。图6a所示实施例的封装结构1包括:基板10、电子元器件20和封装盖体50。其中,所述基板10具有相对设置的第一表面和第二表面,所述电子元器件20与所述基板10的第一表面连接,所述封装盖体50包括顶盖510、第一支撑部521和第二支撑部522,所述顶盖510通过所述第一支撑部521和所述第二支撑部522连接于所述基板10的第一表面上,所述第一支撑部521和所述第二支撑部522之间限定出第一空腔530,所述顶盖510在对应所述电子元器件20的位置设置有开孔511,所述电子元器件20至少部分从所述开孔511中露出。Referring to FIG. 6a, FIG. 6a shows a schematic cross-sectional structure diagram of a package structure 1 provided by another embodiment of the present invention. It should be noted that the top view structure and the longitudinal cross-sectional structure of the package structure 1 of the embodiment shown in FIG. 6a may correspond to the structures of the embodiments shown in FIGS. 3a and 3b, and are therefore omitted here. The package structure 1 of the embodiment shown in FIG. 6 a includes: a
相比图3a-图3c所示实施例中,第二支撑部522采用环状结构,在图6a所示的实施例中,第二支撑部522包括多个支撑脚5221,多个支撑脚5221围绕所述开孔511边缘间隔分布。可以理解,开孔511在图6a的剖面图中实际上并不能示出,在图6a中采用虚线表示开孔511在基板10上的投影位置。Compared with the embodiment shown in FIGS. 3 a to 3 c , the
具体地,如图6a所示,第二支撑部522包括四个方形的支撑脚5221,四个支撑脚5221分布在方形开孔511的四个角位。当然,在图6a所示的实施例中,支撑脚5221的形状、数量和分布状态均为示例性的,具体实现时,可以根据实际适应地改变支撑脚5221的形状、数量和分布状态。Specifically, as shown in FIG. 6 a , the second supporting
例如,如图6b所示,支撑脚5221的截面形状为直角形状,四个直角形状的支撑脚5221分布在方形开孔511的四个角位。本发明实施例对支撑脚5221的具体设置形式不作过多限制。For example, as shown in FIG. 6 b , the cross-sectional shape of the
可以理解,开孔511在图6b的剖面图中实际上并不能示出,在图6b中采用虚线表示开孔511在基板10上的投影位置。It can be understood that the
需说明的是,在图6a/图6b所示的实施例中,电子元器件20与基板10的具体连接方式、封装盖体50与基板10的具体连接方式、封装结构1与电路板的连接方式、封装盖体50的制作方式等均可参照图3a-图3c所示实施例的相关说明,在此不再赘述。It should be noted that, in the embodiment shown in FIG. 6a/FIG. 6b, the specific connection method between the
可以理解的是,本发明实施例的方案通过封装盖体50实现封装结构1的结构加强,以减小翘曲。相比图1a、图1b所示的方案,本发明实施例的方案中,由于封装盖体50具有可以为除上述电子元器件20之外的元器件提供容置空间的第一空腔530,所以有利于封装盖体50在基板10上的覆盖面积最大化(从而得到比图1a、图1b所示加强环更大的覆盖面积),使得封装盖体50具有更好的控制翘曲效果,封装盖体50控制翘曲的具体原理是通过第二支撑部522向第一支撑部521提供力矩,以减小封装结构的应力,从而减小封装结构翘曲,防止因翘曲所造成的问题及损坏,并同时提高封装结构的产能与稳定性。相比图2a、图2b所示的方案,本发明实施例的方案中,封装盖体50具有中空的开孔511,通过该开孔511,电子元器件20能够与空气或散热器直接接触,使得电子元器件20产生的热量便于传递扩散,相比图2a、图2b所示的方案中盖板将电子元器件20密封在基板10上,本发明实施例的封装结构1具有更优的散热性。综上可知,本发明实施例的封装结构1可以在保证封装结构1散热性的前提下有效减小封装翘曲变形。It can be understood that, in the solution of the embodiment of the present invention, the structure of the package structure 1 is strengthened by the
为便于理解本发明实施例采用的封装盖体50所带来的技术效果,下面以盖板类型为无盖板、图1a-图1b所示的加强环30(Stiffener ring)、图2a-图2b所示的常规盖板(Lid)+导热胶(Tim胶)模量0.04Mpa、图2a-图2b所示的常规盖板(Lid)+导热胶(Tim胶)模量0.04Mpa、本发明在图3a-图3c所示实施例提供的封装盖体50作为对比,当采用不同的盖板类型时,测量基板10在室温(25℃)和回流焊峰值(260℃)时的翘曲度,以及电子元器件20(以晶粒为例)到空气或散热器间的热阻,结果参见图7所示表格。In order to facilitate the understanding of the technical effects brought about by the
从图7所示表格可以看出,加强环或者常规盖板均能在一定程度上抑制翘曲,加强环控制翘曲的效果较弱,但不会增加额外热阻,散热较好;常规盖板控制翘曲效果优于加强环,但是受导热胶的模量影响较大,且会增加导热胶和盖板本身热阻,散热效果较差;本发明实施例提供的封装盖体抑制翘曲效果好且稳定,不会受到导热胶材料属性变化的影响,也不会增加额外热阻,散热效果良好。It can be seen from the table shown in Figure 7 that both the reinforcement ring or the conventional cover plate can restrain the warpage to a certain extent. The warpage control effect of the board is better than that of the reinforcement ring, but it is greatly affected by the modulus of the thermally conductive adhesive, and it will increase the thermal resistance of the thermally conductive adhesive and the cover itself, and the heat dissipation effect is poor; the package cover provided by the embodiment of the present invention inhibits warping The effect is good and stable, it will not be affected by changes in the properties of the thermally conductive adhesive material, nor will it increase additional thermal resistance, and the heat dissipation effect is good.
示例性的,以电子元器件20为晶粒为例,本发明实施例的封装结构1的封装工艺流程如下:Exemplarily, taking the
S1,晶粒通过凸起触点62(Bump)倒装焊接到基板10的第一表面上;S1, the die is flip-chip welded to the first surface of the
S2,在晶粒周围添加底部填充胶61(Underfill),由于虹吸作用,融化后的胶将流入凸起触点62底部,把凸起触点62完全包裹起来,起到保护凸起触点62的作用;S2, add underfill glue 61 (Underfill) around the die. Due to the siphon effect, the melted glue will flow into the bottom of the raised
S3,在晶粒上添加Tim胶(如有),在基板10对应第一支撑部521、第二支撑部522的位置上添加粘接胶;S3, adding Tim glue (if any) on the die, and adding adhesive glue to the positions of the
S4,将封装盖体50的第一支撑部521、第二支撑部522压在粘接胶上;S4, pressing the
S5,在一定温度下固化粘接胶,使盖板和基板10粘接在一起;S5, curing the adhesive at a certain temperature, so that the cover plate and the
S6,通过回流炉将焊球或者焊盘植在基板10的第二表面。S6 , implanting solder balls or pads on the second surface of the
本发明实施例还提供了一种电路板组件,所述电路板组件包括电路板和如上任意实施例所述的封装结构1,所述封装结构1与所述电路板连接。Embodiments of the present invention further provide a circuit board assembly, which includes a circuit board and the package structure 1 described in any of the above embodiments, where the package structure 1 is connected to the circuit board.
具体实现时,可以在基板10的第二表面设置多个连接部63,这里的多个连接部63均用以与电路板电连接,多个连接部63在基板10的第二表面间隔分布。示例性的,连接部63可以为焊球,焊球可以为锡、铜等金属材料制成。本发明实施例提供的封装结构1通过多个连接部63与电路板电连接,实现封装结构1与电路板的电气互联,进而实现电路板组件的组装。In specific implementation, a plurality of connection parts 63 may be provided on the second surface of the
本发明实施例还提供了一种电子设备,所述电子设备包括如上任一实施例所述的电路板组件。这里的电子设备可以是手机、平板电脑、笔记本电脑、车载设备、可穿戴设备、无人机、路由器等产品。电子设备也可以是功率电源模块或网络交换设备等设备。An embodiment of the present invention further provides an electronic device, where the electronic device includes the circuit board assembly described in any of the above embodiments. The electronic devices here can be mobile phones, tablet computers, laptops, in-vehicle devices, wearable devices, drones, routers and other products. The electronic device can also be a power supply module or a network switching device.
应能理解,本发明对各个实施例的描述都各有侧重,某个实施例中没有详述或记载的部分,可以参见其它实施例的相关描述。另外,本发明所描述的各个实施方式中所涉及到的技术特征,只要彼此之间未构成冲突就可以相互组合。It should be understood that the description of each embodiment of the present invention has its own emphasis. For parts that are not described or described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In addition, the technical features involved in the various embodiments described in the present invention can be combined with each other as long as they do not conflict with each other.
以上是对本发明的较佳实施进行了具体说明,但本发明并不局限于上述实施方式,熟悉本领域的技术人员在不违背本发明精神的共享条件下,还可作出种种等同的变形或替换,这些等同的变形或替换均包括在本发明权利要求所限定的范围内。The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned embodiments, and those skilled in the art can make various equivalent deformations or replacements under the sharing conditions that do not violate the spirit of the present invention. , these equivalent modifications or replacements are included within the scope defined by the claims of the present invention.
Claims (6)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111548243.5A CN113990809B (en) | 2021-12-17 | 2021-12-17 | Packaging structure, circuit board assembly and electronic equipment |
PCT/CN2022/078891 WO2023108909A1 (en) | 2021-12-17 | 2022-03-02 | Packaging structure, circuit board assembly and electronic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111548243.5A CN113990809B (en) | 2021-12-17 | 2021-12-17 | Packaging structure, circuit board assembly and electronic equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113990809A CN113990809A (en) | 2022-01-28 |
CN113990809B true CN113990809B (en) | 2022-04-29 |
Family
ID=79733995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111548243.5A Active CN113990809B (en) | 2021-12-17 | 2021-12-17 | Packaging structure, circuit board assembly and electronic equipment |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN113990809B (en) |
WO (1) | WO2023108909A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN118116875B (en) * | 2024-04-30 | 2024-08-20 | 格创通信(浙江)有限公司 | System-in-chip and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6602740B1 (en) * | 1999-11-24 | 2003-08-05 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
WO2021217319A1 (en) * | 2020-04-26 | 2021-11-04 | 华为技术有限公司 | Package structure, electronic device, and chip packaging method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407334B1 (en) * | 2000-11-30 | 2002-06-18 | International Business Machines Corporation | I/C chip assembly |
US20050121757A1 (en) * | 2003-12-04 | 2005-06-09 | Gealer Charles A. | Integrated circuit package overlay |
US20080099910A1 (en) * | 2006-08-31 | 2008-05-01 | Ati Technologies Inc. | Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip |
US9041192B2 (en) * | 2012-08-29 | 2015-05-26 | Broadcom Corporation | Hybrid thermal interface material for IC packages with integrated heat spreader |
US20140167243A1 (en) * | 2012-12-13 | 2014-06-19 | Yuci Shen | Semiconductor packages using a chip constraint means |
JP6421050B2 (en) * | 2015-02-09 | 2018-11-07 | 株式会社ジェイデバイス | Semiconductor device |
TWI555147B (en) * | 2015-03-20 | 2016-10-21 | 矽品精密工業股份有限公司 | Heat-dissipation package structure and its heat sink |
TWI647802B (en) * | 2016-07-06 | 2019-01-11 | 矽品精密工業股份有限公司 | Heat dissipation package structure |
DE102016124270A1 (en) * | 2016-12-13 | 2018-06-14 | Infineon Technologies Ag | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE |
TWI658549B (en) * | 2017-01-25 | 2019-05-01 | 矽品精密工業股份有限公司 | Heat-dissipating packaging structure |
JP7001445B2 (en) * | 2017-11-30 | 2022-01-19 | ローム株式会社 | Semiconductor devices and their manufacturing methods |
CN110854083B (en) * | 2019-11-22 | 2021-03-23 | 海光信息技术股份有限公司 | Packaging structure of semiconductor chip and packaging process thereof |
-
2021
- 2021-12-17 CN CN202111548243.5A patent/CN113990809B/en active Active
-
2022
- 2022-03-02 WO PCT/CN2022/078891 patent/WO2023108909A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6602740B1 (en) * | 1999-11-24 | 2003-08-05 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
WO2021217319A1 (en) * | 2020-04-26 | 2021-11-04 | 华为技术有限公司 | Package structure, electronic device, and chip packaging method |
Also Published As
Publication number | Publication date |
---|---|
WO2023108909A1 (en) | 2023-06-22 |
CN113990809A (en) | 2022-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10555417B2 (en) | Mainboard assembly including a package overlying a die directly attached to the mainboard | |
KR102245003B1 (en) | Semiconductor packages capable of overcoming overhangs and methods for fabricating the same | |
TWI506743B (en) | Thermal management structure of semiconduvtor device and methods for forming the same | |
TWI654734B (en) | Stacked semiconductor package | |
TW201543971A (en) | A three-dimensional package structure and the method to fabricate thereof | |
US12199001B2 (en) | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same | |
KR100973722B1 (en) | Electronic module assembly with heat sink | |
JP2008160128A (en) | Printed circuit board, light emitting device including the same, and manufacturing method thereof | |
US7180166B2 (en) | Stacked multi-chip package | |
US11682603B2 (en) | Control of thermal interface material in multi-chip package | |
CN113990809B (en) | Packaging structure, circuit board assembly and electronic equipment | |
TWI793821B (en) | Stacked electronic module and the method to make the same | |
JP4919689B2 (en) | Module board | |
WO2021129092A1 (en) | System-in-package structure, and packaging method for same | |
TWI269414B (en) | Package substrate with improved structure for thermal dissipation and electronic device using the same | |
TWI475651B (en) | Semiconductor device and associated method | |
CN110634813A (en) | Packaging structure | |
WO2020237630A1 (en) | Chip packaging structure and circuit structure | |
US20250112105A1 (en) | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same | |
TWI781863B (en) | Planar type multi-chip device | |
CN219163385U (en) | High heat dissipation substrate structure and packaging structure | |
CN216084861U (en) | Semiconductor packaging structure | |
CN112652588B (en) | Chip packaging structure and chip packaging method | |
TWI360217B (en) | Stacked packaging module and method for manufactur | |
US11239141B2 (en) | Lead frame package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20221118 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Zhongxing building, science and technology south road, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |
|
TR01 | Transfer of patent right |