CN113990807A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN113990807A CN113990807A CN202111249288.2A CN202111249288A CN113990807A CN 113990807 A CN113990807 A CN 113990807A CN 202111249288 A CN202111249288 A CN 202111249288A CN 113990807 A CN113990807 A CN 113990807A
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- 238000004806 packaging method and process Methods 0.000 title abstract description 27
- 239000006185 dispersion Substances 0.000 claims abstract description 82
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000009826 distribution Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- -1 silicon dioxide compound Chemical class 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 81
- 239000012790 adhesive layer Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000499 gel Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application provides a chip packaging structure. The chip packaging structure comprises: the first surface of the packaging substrate is electrically connected with a driving chip; the stress dispersion layer is arranged on the first surface and positioned at the periphery of the driving chip, and the thickness of the stress dispersion layer is greater than or equal to that of the driving chip in the direction perpendicular to the first surface; the stress buffer layer covers the stress dispersion layer and wraps the driving chip; and the semiconductor chip group is arranged on the stress buffer layer and is electrically connected with the first surface. This application is through setting up above-mentioned stress dispersion layer, can be used for dispersing the encapsulation in-process semiconductor chip group owing to receive the downward stress that external force applyed and produce to effectively avoid among the prior art stress concentration with the stress buffer layer in with the region that corresponds at the drive chip edge, bottom chip in the semiconductor chip group that leads to damages, and then reduced in the semiconductor chip group that the chip takes place to become invalid and causes the risk of short circuit, improved chip packaging structure's performance.
Description
Technical Field
The application relates to the field of semiconductor integrated circuit manufacturing, in particular to a chip packaging structure.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), a three-dimensional NAND flash memory is further proposed.
Packaging is an important step in the 3D NAND memory manufacturing process. At present, a chip package structure generally electrically connects a chip set to a package substrate through a wire, and the chip set is packaged and fixed through a package housing. However, the chip in the prior art is prone to short-circuit problems after packaging.
Disclosure of Invention
The main objective of the present application is to provide a chip package structure to solve the problem that a short circuit easily occurs after a chip in the prior art is packaged.
In order to achieve the above object, according to an aspect of the present application, there is provided a chip packaging structure including: the first surface of the packaging substrate is electrically connected with a driving chip; the stress dispersion layer is arranged on the first surface and positioned at the periphery of the driving chip, and the thickness of the stress dispersion layer is greater than or equal to that of the driving chip in the direction perpendicular to the first surface; the stress buffer layer covers the stress dispersion layer and wraps the driving chip; and the semiconductor chip group is arranged on the stress buffer layer and is electrically connected with the first surface.
Further, the difference value of the Young modulus between the driving chip and the stress dispersion layer is Y1The difference value of the Young modulus between the driving chip and the stress buffer layer is Y2，Y1＜Y2。
Further, the material forming the stress dispersion layer includes silicon dioxide and/or silicon.
Further, the material forming the stress buffer layer includes an epoxy resin and/or a silica composite.
Furthermore, the stress dispersion layer comprises a plurality of sub-dispersion parts, each sub-dispersion part is positioned on at least one side of the driving chip, and the adjacent sub-dispersion parts are connected with and surround the stress dispersion layer.
Further, the sub-dispersion parts are respectively located on different sides of the driving chip, and the projection areas of the sub-dispersion parts located on the opposite sides on the first surface are equal.
Further, the stress dispersion layer comprises a first sub-dispersion part and a second sub-dispersion part, two ends of the first sub-dispersion part are connected with two ends of the second sub-dispersion part in a one-to-one correspondence mode, and the projection areas of the first sub-dispersion part and the second sub-dispersion part on the first surface are equal.
Further, the first sub-dispersion portion and the second sub-dispersion portion are U-shaped structures or L-shaped structures.
Further, the semiconductor chip group comprises a plurality of semiconductor chips which are sequentially stacked along the direction far away from the stress buffer layer, and the projection area of the first semiconductor chip on the first surface in the direction far away from the stress buffer layer is S1The projection area of the stress buffer layer on the first surface is S2，S1≤S2。
Further, the chip package structure further includes: and the packaging shell is arranged on the packaging substrate, and the semiconductor chip group is packaged in the packaging shell.
The technical scheme of the application provides a chip packaging structure, including packaging substrate, stress dispersion layer, stress buffer layer and semiconductor chip group, wherein, packaging substrate's first surface electricity is connected with driver chip, stress dispersion layer sets up on the first surface and is located driver chip's periphery, and in the direction of the first surface of perpendicular to, stress dispersion layer's thickness is more than or equal to driver chip's thickness, stress buffer layer covers stress dispersion layer and wraps up driver chip, semiconductor chip group sets up on stress buffer layer and is connected with first surface electricity. This application is through setting up above-mentioned stress dispersion layer, can be used for dispersing the encapsulation in-process semiconductor chip group owing to receive the downward stress that external force applyed and produce to effectively avoid among the prior art stress concentration with the stress buffer layer in with the region that corresponds at the drive chip edge, bottom chip in the semiconductor chip group that leads to damages, and then reduced in the semiconductor chip group that the chip takes place to become invalid and causes the risk of short circuit, improved chip packaging structure's performance.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a stress distribution layer provided in accordance with an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a stress distribution layer according to another embodiment of the present disclosure;
FIG. 4 is a schematic cross-sectional view of a stress distribution layer according to still another embodiment of the present disclosure;
fig. 5 is a schematic cross-sectional view illustrating a chip package structure with a package housing according to an embodiment of the present disclosure.
Wherein the figures include the following reference numerals:
10. a package substrate; 20. a driving chip; 30. a stress dispersion layer; 310. a sub-dispersion section; 311. a first sub-dispersion section; 312. a second sub-dispersion section; 40. a stress buffer layer; 50. a semiconductor chip set; 510. a semiconductor chip; 520. a second adhesive layer; 60. a first adhesive layer; 70. an electrical contact; 80. a package housing; 90. and a protective layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the chip package structure in the prior art, usually, the chip set is electrically connected to the package substrate through the wires, and the chip set is packaged and fixed through the package housing.
The inventor of the present application has studied the above problem, and proposes a chip package structure, as shown in fig. 1, including: the package substrate 10, the first surface of the package substrate 10 is electrically connected with the driving chip 20: the stress dispersion layer 30 is arranged on the first surface and positioned at the periphery of the driving chip 20, and the thickness of the stress dispersion layer 30 is greater than or equal to that of the driving chip 20 in the direction perpendicular to the first surface; the stress buffer layer 40 covers the stress dispersion layer 30 and wraps the driving chip 20; and a semiconductor chip set 50 disposed on the stress buffer layer 40 and electrically connected to the first surface.
The research shows that the chip in the prior art is easy to have short circuit after being packaged because the stress buffer layer is adopted to directly wrap the driving chip, so that the external force generated by the semiconductor chip group during packaging is uneven in distribution in the stress buffer layer and is easy to concentrate at the position corresponding to the edge of the driving chip, and therefore the semiconductor chip positioned at the bottom in the semiconductor chip group is easy to break, and further the failure is caused. This application is through setting up above-mentioned stress dispersion layer 30, can be used for dispersing the encapsulation in-process semiconductor chip group 50 owing to receive the downward stress that external force applyed and produce to effectively avoid among the prior art stress concentration with the stress buffer layer 40 in with the region that corresponds at the edge of driver chip 20, bottom chip in the semiconductor chip group 50 that leads to damages, and then reduced semiconductor chip group 50 in the chip take place to become invalid and cause the risk of short circuit, improved chip packaging structure's performance.
The material of the package substrate 10 may be a conventional insulating material, for example, an epoxy-based laminate substrate, a resin-based Bismaleimide Triazine (BT) substrate, or the like. The package substrate 10 may also have rigidity so as to provide mechanical support for the driving chip 20 and the semiconductor chip set 50.
The package substrate 10 may also provide electrical support for the driving chip 20 and the semiconductor chip set 50. Illustratively, the package substrate 10 has multiple layers of metal traces with insulating material therebetween. The metal traces on the different layers may be connected by vias. The material of the metal trace may include, but is not limited to, gold, silver, copper, aluminum, and other metal wiring materials.
The driving chip 20 may be fixedly disposed on the package substrate 10 through a first adhesive layer 60 and electrically connected to the package substrate 10 through a wire, as shown in fig. 1. Illustratively, the first adhesive layer 60 is a Die Attach Film (DAF).
In an alternative embodiment of the present application, the difference between the young's modulus of the driver chip 20 and the stress dispersion layer 30 is Y1The difference between the Young's modulus of the driver chip 20 and the stress buffer layer 40 is Y2，Y1＜Y2. In the above embodiment, by adding the stress dispersion layer 30 and providing the young's modulus of the stress dispersion layer 30 closer to that of the driver chip 20 than that of the stress buffer layer 40, the stress generated in the semiconductor chip set 50 during packaging can be distributed to the stress buffer layer 40The distribution is more uniform, thereby reducing the risk of implementation due to breakage of the semiconductor chip 510. It should be noted that the mechanical property of the additional stress buffer layer 40 close to the driver chip 20 in the present application is not limited to the young's modulus, and may also have other mechanical properties close to the driver chip 20, such as poisson's ratio, and the present application is not limited specifically.
In the above-described embodiment of the present application, since the control chip in the related art is generally a silicon-based chip, in order to make the stress dispersion layer 30 have a young's modulus closer to that of the driver chip 20, it is preferable that the material forming the stress dispersion layer 30 includes silicon dioxide and/or silicon. But not limited to the above preferred species, and those skilled in the art can reasonably select a material satisfying the above young's modulus according to the prior art.
In the above-described embodiments of the present application, the material forming the stress buffer layer 40 may include an epoxy resin and/or a silica composite. The material generally has fluidity, so that the material can not only better cover the driving chip 20 and the stress dispersion layer 30 in the molding process, but also better fill in the gap between the driving chip 20 and the stress dispersion layer 30, thereby improving the uniformity of the distribution of the stress generated by the semiconductor chip set 50 in the stress buffer layer 40 during packaging. It should be noted that the material forming the stress buffer layer 40 in the present application is not limited to the above-mentioned kind, and may be other insulating materials with fluidity in the prior art, and the present application is not limited in particular.
In order to facilitate the stress dispersion layer 30 to be disposed on the package substrate 10 at the periphery of the driver chip 20, the stress dispersion layer 30 may include a plurality of sub-dispersion portions 310, each sub-dispersion portion 310 is located on at least one side of the driver chip 20, and adjacent sub-dispersion portions 310 are connected to and surround the stress dispersion layer 30, as shown in fig. 2 to 4.
In an alternative embodiment of the present application, the sub-dispersion parts 310 are respectively located on different sides of the driving chip 20, and the projection areas of the sub-dispersion parts 310 located on the opposite sides on the first surface are equal, as shown in fig. 2. By adopting the above embodiment, the elongated sub-dispersing portions 310 can be respectively disposed on different sides of the driver chip 20, so that the stress dispersing layers 30 are formed by adjacent sub-dispersing portions 310, the difficulty of the preparation process of the stress dispersing layers 30 is reduced, and the stress dispersing layers 30 are conveniently disposed on the package substrate 10 around the driver chip 20.
In another alternative embodiment of the present application, the stress dispersion layer 30 includes a first sub-dispersion portion 311 and a second sub-dispersion portion 312, two ends of the first sub-dispersion portion 311 are connected to two ends of the second sub-dispersion portion 312 in a one-to-one correspondence manner, and projection areas of the first sub-dispersion portion 311 and the second sub-dispersion portion 312 on the first surface are equal. The first sub-dispersion portion 311 and the second sub-dispersion portion 312 may have a U-shaped structure, as shown in fig. 3; the first sub-dispersion part 311 and the second sub-dispersion part 312 may have an L-shaped structure, as shown in fig. 4. With the above embodiment, the difficulty of the manufacturing process of the stress dispersion layer 30 can also be reduced, and the stress dispersion layer 30 can be conveniently disposed on the package substrate 10 around the driving chip 20.
In an alternative embodiment of the present application, the semiconductor chip group 50 includes a plurality of semiconductor chips 510 sequentially stacked and disposed along a direction away from the stress buffer layer 40, and a projection area of a first semiconductor chip 510 on the first surface in the direction away from the stress buffer layer 40 is S1The projected area of the stress buffer layer 40 on the first surface is S2，S1≤S2. With the above embodiment, the contact area between the semiconductor chip 510 located at the lowermost layer in the semiconductor chip group 50 and the stress buffer layer 40 can be smaller than the upper surface area of the stress buffer layer 40, or the contact area between the semiconductor chip 510 and the stress buffer layer 40 can be the same, so that the stress generated by the semiconductor chip group 50 during packaging can be more uniformly distributed in the stress buffer layer 40.
The semiconductor chip set 50 of the present application includes a plurality of semiconductor chips 510, adjacent semiconductor chips 510 are stacked by a second adhesive layer 520, and adjacent semiconductor chips 510 are connected by a wire, and the semiconductor chips 510 may form a multi-step structure or be staggered as shown in fig. 1. Illustratively, the semiconductor chip 510 is a memory chip having a memory structure for providing a memory function. It should be noted that the semiconductor chip 510 described above in this application may also be a chip having other functions, such as including functions for providing computing functions and/or processing functions.
The material of the connecting line may include, but is not limited to, gold, silver, copper, aluminum, and other metal connecting line materials. Illustratively, the second adhesive layer 520 is a Die Attach Film (DAF).
The number of the semiconductor chip sets 50 may be one or more. Illustratively, only one semiconductor chip set 50 is packaged on the package substrate 10, as shown in fig. 1. In another example, a plurality of semiconductor chip groups are packaged on the package substrate, and the plurality of semiconductor chip groups are distributed on the package substrate. It should be noted that the number of chips in different semiconductor chip groups 50, the stacking structure, and the circuit structure in the chips may be the same or different.
The above chip package structure of the present application may further include a package housing 80 for improving reliability of the device, as shown in fig. 5, the package housing 80 is mounted on the package substrate 10, and the semiconductor chip group 50 is packaged inside the package housing 80. The material of the package housing 80 may be a conventional semiconductor package material in the prior art, including but not limited to Epoxy Molding Compound (EMC).
Optionally, the chip package structure of the present application may further include a protection layer 90 disposed outside the semiconductor chip set 50, as shown in fig. 5. The protection layer 90 may be made of a material with a certain shock absorption capability, such as silicon gel, resin or other bonding glue, and by disposing the protection layer 90 outside the semiconductor chip set 50 and the corresponding wires, on one hand, the chips or the wires may be prevented from being damaged when the package housing 80 is manufactured, and on the other hand, a part of deformation and external force may be absorbed when the package housing 80 is squeezed by an external force. Illustratively, the above-described protective layer 90 includes an Epoxy Molding Compound (EMC).
The chip package structure of the present application may further include an electrical contact 70, and each semiconductor chip 510 in the semiconductor chip group 50 is electrically connected to the electrical contact 70 through a wire. The electrical contact 70 may be disposed at any position exposed outside the package housing 80, and the electrical contact 70 is exemplarily a solder ball disposed on a side of the package substrate 10 away from the semiconductor chip group 50, as shown in fig. 1 and 5.
Illustratively, the method of packaging the semiconductor chip set 50 to obtain the chip package structure includes:
providing a package substrate 10, wherein one side of the package substrate 10 is provided with a driving chip 20 fixedly arranged through DAF glue, and the driving chip 20 is electrically connected with the package substrate 10 through a connecting wire;
arranging a silicon dioxide layer on the periphery of the driving chip 20 on the packaging substrate 10 to serve as a stress dispersion layer 30, wherein the height of the stress dispersion layer 30 is not lower than that of the driving chip 20;
coating epoxy resin with fluidity on the surface of the packaging substrate 10, so that the epoxy resin wraps the driving chip 20 and covers the stress dispersion layer 30, and curing the epoxy resin to obtain a stress buffer layer 40;
sequentially arranging a plurality of semiconductor chips 510 on the stress buffer layer 40 through the DAF paste to form a semiconductor chip group 50, and electrically connecting each semiconductor chip 510 with the package substrate 10 through a wire;
forming a protective layer 90 wrapping the semiconductor chip set 50 on the package substrate 10 by using silica gel, and forming a package casing 80 outside the protective layer 90, so that the semiconductor chip set 50 is packaged inside the package casing 80;
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
this application is through setting up above-mentioned stress dispersion layer, can be used for dispersing the encapsulation in-process semiconductor chip group owing to receive the downward stress that external force applyed and produce to effectively avoid among the prior art stress concentration with the stress buffer layer in with the region that corresponds at the drive chip edge, bottom chip in the semiconductor chip group that leads to damages, and then reduced in the semiconductor chip group that the chip takes place to become invalid and causes the risk of short circuit, improved chip packaging structure's performance.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111249288.2A CN113990807A (en) | 2021-10-26 | 2021-10-26 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111249288.2A CN113990807A (en) | 2021-10-26 | 2021-10-26 | Chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113990807A true CN113990807A (en) | 2022-01-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111249288.2A Pending CN113990807A (en) | 2021-10-26 | 2021-10-26 | Chip packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11163203A (en) * | 1997-11-28 | 1999-06-18 | Hitachi Ltd | Semiconductor device, its manufacturing method and wiring tape |
| US20100035380A1 (en) * | 2008-08-05 | 2010-02-11 | Kun Yuan Technology Co., Ltd. | Method for fabricating package structure of stacked chips |
| JP2010161399A (en) * | 2010-03-04 | 2010-07-22 | Renesas Technology Corp | Semiconductor apparatus |
| US20120018871A1 (en) * | 2010-07-21 | 2012-01-26 | Samsung Electronics Co., Ltd | Stack package and semiconductor package including the same |
| US20130056882A1 (en) * | 2011-09-06 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor package having support member |
| US20140306337A1 (en) * | 2013-04-12 | 2014-10-16 | Maxim Integrated Products, Inc. | Semiconductor device having a buffer material and stiffener |
| JP2015206013A (en) * | 2014-04-23 | 2015-11-19 | 日立化成株式会社 | Photosensitive adhesive composition, method for manufacturing semiconductor device using the same, and semiconductor device |
| WO2021119930A1 (en) * | 2019-12-16 | 2021-06-24 | 华为技术有限公司 | Chip package and fabrication method therefor |
-
2021
- 2021-10-26 CN CN202111249288.2A patent/CN113990807A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11163203A (en) * | 1997-11-28 | 1999-06-18 | Hitachi Ltd | Semiconductor device, its manufacturing method and wiring tape |
| US20100035380A1 (en) * | 2008-08-05 | 2010-02-11 | Kun Yuan Technology Co., Ltd. | Method for fabricating package structure of stacked chips |
| JP2010161399A (en) * | 2010-03-04 | 2010-07-22 | Renesas Technology Corp | Semiconductor apparatus |
| US20120018871A1 (en) * | 2010-07-21 | 2012-01-26 | Samsung Electronics Co., Ltd | Stack package and semiconductor package including the same |
| US20130056882A1 (en) * | 2011-09-06 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor package having support member |
| US20140306337A1 (en) * | 2013-04-12 | 2014-10-16 | Maxim Integrated Products, Inc. | Semiconductor device having a buffer material and stiffener |
| JP2015206013A (en) * | 2014-04-23 | 2015-11-19 | 日立化成株式会社 | Photosensitive adhesive composition, method for manufacturing semiconductor device using the same, and semiconductor device |
| WO2021119930A1 (en) * | 2019-12-16 | 2021-06-24 | 华为技术有限公司 | Chip package and fabrication method therefor |
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