CN113972308A

CN113972308A - Electronic substrate and electronic device

Info

Publication number: CN113972308A
Application number: CN202110189431.7A
Authority: CN
Inventors: 粘觉元; 宋朝钦; 谢佳宏; 刘美丞
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2020-07-24
Filing date: 2021-02-19
Publication date: 2022-01-25

Abstract

The present disclosure provides an electronic substrate and an electronic device. The electronic substrate comprises a base, a convex part and a bonding pad. The protruding portion and the bonding pad are disposed on the substrate. The bonding pad does not overlap with the boundary of the projection.

Description

Electronic substrate and electronic device

Technical Field

The present disclosure relates to an electronic substrate and an electronic device including the same.

Background

Before the electronic substrate and/or the electronic device is shipped, a series of reliability tests are performed. When a substrate (LED) is subjected to a thermal shock test, the CTE (coefficient of thermal expansion) between the LED and the substrate (e.g., glass) is not matched, which may result in cracking of the substrate or peeling of the LED, thereby causing dark spots.

Disclosure of Invention

The present disclosure provides an electronic substrate and an electronic device, which are helpful for improving reliability.

According to one embodiment of the present disclosure, an electronic substrate includes a base, a protrusion, and a bonding pad. The protruding portion and the bonding pad are disposed on the substrate. The bonding pad does not overlap with the boundary of the projection.

According to another embodiment of the present disclosure, an electronic device includes the electronic substrate and an electronic element. The electronic element is electrically connected with the bonding pad.

In order to make the aforementioned and other features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic partial cross-sectional view of an electronic device according to a first embodiment of the present disclosure;

FIG. 2 is a schematic top view of a portion of the electronic substrate of FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of an electronic device according to a second embodiment of the present disclosure;

FIG. 4 is a schematic top view of a portion of an electronic device according to a third embodiment of the present disclosure;

fig. 5 is a schematic partial cross-sectional view of an electronic device according to a fourth embodiment of the disclosure.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the reader and the simplicity of the drawings, the various drawings in the present disclosure depict only a portion of an electronic device/display device and certain elements of the drawings are not necessarily drawn to scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the relative sizes, thicknesses, and locations of various layers, regions, or structures may be reduced or exaggerated for clarity.

Certain terms are used throughout the description and following claims to refer to particular elements. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following description and claims, the terms "having" and "including" are used as open-ended terms, and thus should be interpreted to mean "including, but not limited to …".

Directional phrases used herein include, for example: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present (not directly). In contrast, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present therebetween.

The terms "about," "equal," "identical," "substantially," or "approximately" as referred to herein generally represent a range of 10% of a given value or range, or 5%, 3%, 2%, 1%, or 0.5% of the given value or range. Further, the phrase "a given range is from a first value to a second value," and "a given range is within a range from a first value to a second value" means that the given range includes the first value, the second value, and other values therebetween.

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. The terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the terms "electrically connected" and "coupled" encompass any direct and indirect electrical connection.

In the following embodiments, the same or similar elements will be denoted by the same or similar reference numerals, and the detailed description thereof will be omitted. Furthermore, the features of the various embodiments may be combined in any suitable manner without departing from the spirit or conflict of the invention, and all such modifications and equivalents as may be within the spirit and scope of the disclosure are deemed to be within the ambit and scope of the disclosure. In addition, the terms "first", "second", and the like in the description and the claims are only used for naming different elements or distinguishing different embodiments or ranges, and are not used for limiting the upper limit or the lower limit of the number of elements, nor are they used for limiting the manufacturing order or the arrangement order of the elements.

The electronic device of the present disclosure may include, but is not limited to, a display device, an antenna device, a sensing device, a light-emitting device, or a splicing device. The electronic device may include a bendable or flexible electronic device. The electronic device may for example comprise a liquid crystal (liquid crystal) layer or a light emitting diode. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED, which may include QLED, QDLED), a fluorescent (fluorescent), a phosphorescent (phosphor), or other suitable material, or a combination thereof, but is not limited thereto. The present disclosure will be described below with reference to a display device as an electronic device, but the present disclosure is not limited thereto.

The display device of the present disclosure may be any kind of display device, such as a self-luminous display device or a non-self-luminous display device. The self-light emitting display device may include a light emitting diode, a light conversion layer or other suitable materials, or a combination thereof, but is not limited thereto. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED, which may include a QLED or a QDLED), but is not limited thereto. The light conversion layer may include a wavelength conversion material and/or a light filtering material, and the light conversion layer may include, for example, fluorescence (phosphorescence), phosphorescence (phor), Quantum Dots (QD), other suitable materials, or combinations thereof, but is not limited thereto. The non-self-luminous display device may include a liquid crystal display device, but is not limited thereto.

Fig. 1 is a schematic partial cross-sectional view of an electronic device according to a first embodiment of the disclosure. Fig. 2 is a schematic partial top view of the electronic substrate of fig. 1. For simplicity, fig. 2 only shows two chain lines, a dotted line and a chain line at one point to respectively indicate the edges of the protrusion, the first conductive layer and the pad defining layer in fig. 1, and other elements and film layers are omitted. The cross section of the section line A-A' in FIG. 2 can be referred to FIG. 1.

Referring to fig. 1 and 2, an electronic device 1 may include a substrate 10 and an electronic component 12. For example, the substrate 10 may be an electronic substrate. The electronic substrate (substrate 10) may include a base 100, a protrusion 101, and a bonding pad 102, but not limited thereto.

The substrate 100 can be used to carry the protrusion 101 and the bonding pad 102. For example, the material of the substrate 100 may include glass, but is not limited thereto. In some embodiments, the substrate 100 may be a rigid substrate or a flexible substrate. In some embodiments, the material of the substrate 100 may include glass, plastic, Polycarbonate (PC), Polyimide (PI), polyethylene terephthalate (PET), quartz, sapphire (sapphire), ceramic, or a combination thereof, i.e., the substrate 100 may be a single-layer plate or a composite plate, but not limited thereto.

The projection 101 is provided on the substrate 100. For example, the projection 101 may be formed of a flat layer. In some embodiments, the planarization layer may be an organic insulating layer, but not limited thereto. In some embodiments, the projections 101 may be formed of a single layer of organic insulating layer. In other embodiments, the protrusion 101 may be formed by stacking a plurality of organic insulating layers. In some embodiments, the projections 101 may be an organic insulating layer, an inorganic insulating layer, or a combination thereof.

The bonding pads 102 are disposed on the substrate 100 and can be used to bond with the electronic device 12, but not limited thereto. For example, the electronic component 12 may be a light emitting diode. The light emitting diode may include, for example, a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (quantum dot LED, which may include a QLED, a QDLED), but is not limited thereto. In addition, the electronic device 12 may include a pad 120. In some embodiments, the electronic device 1 may also include a conductive adhesion layer 13 (e.g., a tin layer). The bonding pad 120 may be soldered to the bonding pad 102 through the conductive adhesive layer 13, such that the electronic device 12 is electrically connected to the bonding pad 102, but not limited thereto. In some embodiments, the bond pad 102 may comprise a two-layer stack structure. For example, the bonding pad 102 may include a first conductive layer 102-1 and a second conductive layer 102-2 sequentially stacked on the substrate 100. The first conductive layer 102-1 and the second conductive layer may be metal layers or metal alloy layers. Specifically, the first conductive layer 102-1 may include a copper layer, and the second conductive layer 102-2 may include a nickel layer, but not limited thereto. The second conductive layer 102-2 may have a higher adhesion force with the conductive adhesive layer 13 than the first conductive layer 102-1, so as to improve the adhesion force of the electronic element 12 to the bonding pad 102, but not limited thereto. The first conductive layer 102-1 and the second conductive layer 102-2 can have the same or different thicknesses. In other embodiments, the bonding pad 102 may be formed by a single conductive layer with proper material selection.

In some embodiments, the bonding pad 102 is disposed on the substrate 100 after the protrusion 101, for example. For example, the electronic substrate 10 may further include an insulating layer (e.g., the fourth insulating layer 107). An insulating layer (e.g., a fourth insulating layer 107) is disposed on the protrusion 101, and the bonding pad 102 may be disposed on the insulating layer (e.g., the fourth insulating layer 107).

Due to the mismatch between the thermal expansion coefficients of the electronic element 12 and the substrate 100, when the electronic device 1 is subjected to a thermal shock test, stress may be generated between the electronic element 12 and the substrate 100 due to thermal expansion and contraction. In the case where the solder joints are not flat, for example, the surface of the bonding pads 102 is not flat (for example, the surface of the copper layer is not flat), large stress is likely to be generated between the electronic component 12 and the substrate 100, resulting in cracking of the substrate 100 or peeling of the electronic component 12.

According to the observation, the position where the maximum stress is generated between the electronic component 12 and the substrate 100 may occur at the boundary B of the projection 101 (i.e., the boundary where the projection 101 starts to climb up), i.e., the substrate 100 is easily broken at the boundary B of the projection 101, where the crack starts at the boundary B of the projection 101 and ends in the substrate 100.

In the embodiment of the present disclosure, the bonding pad 102 does not overlap the boundary B of the protrusion 101, so that the bonding pad 102 does not overlap the position where the maximum stress is likely to be generated (i.e., the boundary B of the protrusion 101), so as to reduce the stress generated between the electronic device 12 and the substrate 100 or improve the flatness of the bonding point (e.g., the flatness of the surface of the bonding pad 102 or the surface on which the copper layer is disposed), thereby reducing the probability of cracking of the substrate 100 or peeling of the electronic device 12. According to some embodiments, the bonding pad 102 has a gap G with the boundary B of the protrusion 101, for example, the bonding pad 102 and the boundary B do not overlap in the thickness direction DT of the electronic device 1. In some embodiments, the gap G between the bonding pad 102 and the boundary B may fall within a range of 5 μm to 100 μm, i.e., 5 μm ≦ G ≦ 100 μm, but not limited thereto, in view of current process accuracy (e.g., exposure accuracy) and the small size requirements of the electronic device 1. In other embodiments, the gap G between the bonding pad 102 and the boundary B may be 0, i.e., the bonding pad 102 and the boundary B may be aligned or substantially aligned. According to some embodiments, the gap G may fall within a range of 0 μm to 300 μm. According to some embodiments, the gap G may fall within a range of 0 μm to 200 μm. According to some embodiments, the gap G may be greater than 0. According to some embodiments, the gap G may fall within a range of 5 μm to 200 μm. According to some embodiments, the gap G may fall within a range of 5 μm to 100 μm. According to some embodiments, the gap G may fall within a range of 5 μm to 50 μm. According to some embodiments, the gap G may fall within a range of 5 μm to 10 μm. According to some embodiments, the gap G may be a gap between the first conductive layer 102-1 of the bonding pad 102 and the protrusion 101. According to some embodiments, the gap G may be a gap between the second conductive layer 102-2 and the protrusion 101.

Conversely, in the case where the bonding pad 102 overlaps the boundary B of the convex portion 101 (not shown), specifically, a part of the bonding pad 102 overlaps a part of the convex portion 101 in the thickness direction DT. As shown in fig. 1, the projection 101 may have a slope at the edge. For example, the bonding pad 102 is disposed on the boundary B of the projection 101 and formed along the slope of the projection 101. Thus, the overlapping portion of the bonding pad 102 has an uneven surface due to the formation along the slope of the protrusion 101, so that a large stress is easily generated between the electronic component 12 and the substrate 100, which may cause cracking of the substrate 100 or peeling of the electronic component 12.

The base cracking rate refers to the ratio of the number of particles that the electronic component peels off or fails to operate normally due to base cracking to the total number of electronic components on the same substrate. Whether the electronic component is peeled off or whether it can operate normally (i.e., whether the electronic component can be lit) can be observed by an Optical Microscope (OM). Taking the substrate as glass as an example, it can be seen from the experimental results that the design in which the bonding pad does not overlap the boundary of the protrusion can reduce the substrate crack rate from 11.5% to 2% in some embodiments, compared to the design in which the bonding pad overlaps the boundary of the protrusion. Furthermore, from the simulation results, it can be seen that in some embodiments, a design in which the bond pad does not overlap the boundary of the protrusion may reduce the maximum stress from 2905MPa to 752MPa, as compared to a design in which the bond pad overlaps the boundary of the protrusion. Therefore, in some embodiments, the design that the bonding pad 102 does not overlap with the boundary B of the protrusion 101 helps to improve the reliability of the electronic device 1.

The electronic substrate 10 may further include other elements or layers according to different requirements, as shown in fig. 1. For example, the electronic substrate 10 may further include a driving element 103, a first insulating layer 104, a second insulating layer 105, a third insulating layer 106, a fourth insulating layer 107, and a pad defining layer 108.

Referring to fig. 1, the driving device 103 may be disposed on the substrate 100 and include, for example, a gate (not shown), a channel layer CH, a source (not shown), and a drain DE. The driving element 103 may be, for example, a thin film transistor, a top gate thin film transistor, or a bottom gate thin film transistor, but not limited thereto. Taking the driving device 103 as a bottom gate thin film transistor as an example, the gate is disposed on the substrate 100. The gate may be made of a metal, an alloy, or a combination thereof, but not limited thereto. A first insulating layer 104 is disposed on the gate and the substrate 100. The first insulating layer 104 may include an inorganic insulating layer, such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. The channel layer CH is disposed on the first insulating layer 104 and above the gate. The material of the channel layer CH may include, but is not limited to, amorphous silicon, polysilicon, or metal oxide. The second insulating layer 105 is disposed on the channel layer CH and the first insulating layer 104. The second insulating layer 105 may include an inorganic insulating layer, such as silicon oxide (SiOx) or silicon nitride (SiNx), but not limited thereto. The second insulating layer 105 has an opening a 1. The opening a1 exposes a portion of the channel layer CH. The source and drain electrodes DE are disposed on the second insulating layer 105 and are in contact with the channel layer CH through different openings a 1. The material of the source and the drain DE may include, but is not limited to, metal, alloy, or a combination thereof. The third insulating layer 106 is disposed on the second insulating layer 105, the source electrode, and the drain electrode DE. The third insulating layer 106 may include an inorganic insulating layer, such as silicon oxide (SiOx) or silicon nitride (SiNx), but not limited thereto. The third insulating layer 106 has an opening a 2. The opening a2 exposes a portion of the drain DE. The projection 101 is provided on the third insulating layer 106. A fourth insulating layer 107 is provided on the projections 101 and the third insulating layer 106. The fourth insulating layer 107 may include an inorganic insulating layer, such as silicon oxide (SiOx) or silicon nitride (SiNx), but not limited thereto. The fourth insulating layer 107 has an opening a 3. The opening A3 and the opening a2 may be connected and expose a portion of the drain DE.

With continued reference to fig. 1, the bond pad 102 may include a first conductive layer 102-1 and a second conductive layer 102-2. The first conductive layer 102-1 may be disposed on the fourth insulating layer 107, wherein the first conductive layer 102-1 of at least one of the bonding pads 102 may contact the drain electrode DE through the opening a2 and the opening A3. The pad defining layer 108 is disposed on the fourth insulating layer 107 and covers a portion E102-1 of the first conductive layer 102-1 of each bonding pad 102. The second conductive layer 102-2 may be disposed on the first conductive layer 102-1 and may cover a portion E108 of the pad defining layer 108. According to some embodiments, as shown in fig. 1, the edge E1 of the first conductive layer 102-1 may be closer to the boundary B of the protrusion 101 than the edge E2 of the second conductive layer 102-2 on the same side of the electronic element 12. Thus, a portion of the pad definition layer 108 may cover a portion of the first conductive layer 102-1, such as the portion E102-1. According to some embodiments (not shown), the edge E1 of the first conductive layer 102-1 may be farther away from the boundary B of the protrusion 101 than the edge E2 of the second conductive layer 102-2 on the same side of the electronic element 12.

It should be understood that although fig. 1 shows only one electronic component 12, any number of electronic components 12 may be disposed on the electronic substrate 10, as desired. In addition, the type of the electronic component 12 can be changed according to the requirement, and is not limited to the light emitting diode. In the structure where the electronic component 12 is a light emitting diode, the electronic device 1 can be, for example, a light emitting device, a display device (e.g., a non-self-luminous display device), or a tiled display device, but not limited thereto.

Fig. 3 is a schematic partial cross-sectional view of an electronic device according to a second embodiment of the disclosure. Referring to fig. 3, the main differences between the electronic device 1A and the electronic device 1 in fig. 1 are described as follows. The electronic device 1A includes an electronic substrate 10A, an electronic component 12, a conductive adhesive layer 13, and a circuit board 14. The electronic substrate 10A may be, for example, a wafer integrated with active devices (e.g., thin film transistors) and passive devices (e.g., capacitors or resistors). For example, the electronic substrate 10A may include a driving circuit, but is not limited thereto. Fig. 3 schematically shows that the electronic substrate 10A has a similar structure to the electronic substrate 10 in fig. 1, with the difference that the electronic substrate 10A further comprises a circuit layer 109 disposed between the base 100 and the third insulating layer 106. In order to clearly show the circuit layer 109, fig. 3 omits a portion of the layers and elements of the electronic substrate 10A, and please refer to fig. 1.

The electronic substrate 10A and the electronic component 12 are bonded to the same side of the circuit board 14, and the electronic substrate 10A and the electronic component 12 are electrically connected through the circuit board 14. For example, the circuit board 14 may include a circuit substrate 140, a bonding pad 141, and a protection layer 142.

The circuit substrate 140 may include a plurality of metal layers (not shown) and a plurality of insulating layers (not shown) that are alternately stacked. The bonding pads 141 are disposed on the circuit substrate 140 and can be used to bond the electronic element 12 and the electronic substrate 10A, but not limited thereto. For example, the pads 120 of the electronic device 12 and the bonding pads 102 of the electronic substrate 10A may be soldered to the bonding pads 141 by the conductive adhesive layer 13 (e.g., tin layer), so that the electronic device 12 and the bonding pads 102 are electrically connected, but not limited thereto. In some embodiments, the bonding pad 141 may include a double-layer stack structure. For example, the bonding pad 141 may include a first conductive layer 141-1 (e.g., a copper layer) and a second conductive layer 141-2 (e.g., a nickel layer) sequentially stacked on the circuit substrate 140, wherein the second conductive layer 141-2 may have a higher adhesion force with the conductive adhesion layer 13 than the first conductive layer 141-1, so as to improve the adhesion force of the electronic component 12 and the electronic substrate 10A to the bonding pad 141, but not limited thereto. In other embodiments, the bonding pad 141 may be formed by a single conductive layer with proper material selection.

The passivation layer 142 is disposed on the circuit substrate 140 and the partial first conductive layer 141-1. In detail, the protection layer 142 has a plurality of openings a 4. The plurality of openings a4 expose regions of the first conductive layer 141-1 where the second conductive layer 141-2 is to be disposed, respectively, to facilitate the second conductive layer 141-2 to be disposed on the first conductive layer 141-1. The material of the protection layer 142 may include a solder resist (solder resist) or a photoresist (photoresist), but is not limited thereto.

In the present embodiment, the reliability of the electronic device 1A can also be improved by the design that the bonding pad 102 does not overlap with the boundary of the protrusion 101, and for the specific description, reference is made to the foregoing description, which is not repeated herein.

It should be understood that although fig. 3 only shows one electronic component 12 and one electronic substrate 10A, any number of electronic components 12 and any number of electronic substrates 10A may be disposed on the circuit board 14, as desired. In addition, the type of the electronic component 12 can be changed according to the requirement, and is not limited to the light emitting diode. In addition, the specific structure of the electronic substrate 10A may also be changed as required, and is not limited to that shown in fig. 3. In the structure where the electronic element 12 is a light emitting diode, the electronic device 1A can be, for example, a display device (e.g., a non-self-luminous display device) or a tiled display device, but not limited thereto.

Fig. 4 is a schematic top view of a portion of an electronic device according to a third embodiment of the disclosure. Referring to fig. 4, the electronic device 1B is, for example, a tiled display device. For example, the electronic device 1B may be formed by splicing four electronic devices 1 shown in fig. 1, but the number of the electronic devices 1 in the electronic device 1B may be changed according to the requirement. In fig. 4, each electronic device 1 includes, for example, one electronic substrate 10 (see fig. 1), four electronic devices 1 include four electronic substrates 10, and the four electronic substrates 10 are spliced together to form a tiled display device. In other embodiments, in the case that the electronic substrate 10A in fig. 3 does not affect the display quality, for example, when the size of the electronic substrate 10A is much smaller than that of the electronic device 1B or the size of the electronic substrate 10A is very small, the electronic device 1B may be formed by splicing a plurality of electronic devices 1A shown in fig. 3.

Fig. 5 is a schematic partial cross-sectional view of an electronic device according to a fourth embodiment of the disclosure. Referring to fig. 5, the electronic device 1C is, for example, a non-self-luminous display device. For example, the electronic device 1C may include the electronic device 1 shown in fig. 1 and the display panel DP. In the electronic device 1C, the electronic device 1 functions as a backlight module, for example. The electronic component 12 in the electronic device 1 is, for example, a light emitting diode, and the display panel DP is disposed on a transmission path of the light beam L from the light emitting diode. In other embodiments, the electronic device 1 in the electronic device 1C can be replaced by the electronic device 1A in fig. 3.

In summary, in the embodiments of the present disclosure, the design that the bonding pad does not overlap with the boundary of the protrusion portion is used to reduce the stress generated between the electronic device and the substrate or improve the flatness of the solder joint, thereby reducing the probability of cracking of the substrate or peeling off the electronic device, and contributing to improving the reliability of the electronic device.

The above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure.

Although the embodiments of the present disclosure and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure, and the features of the various embodiments may be arbitrarily mixed and substituted with one another to form new embodiments. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the present disclosure will suggest themselves to those skilled in the art having the benefit of this disclosure, and is intended to cover such modifications as may incorporate those features or methods into the practice of the present disclosure, as well as the equivalents of such processes, machines, manufacture, composition of matter, means, methods and steps, or any materials, which perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the scope of the present disclosure includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of the present disclosure also includes combinations of the respective claims and embodiments. The scope of the present disclosure is to be determined by the claims appended hereto.

Claims

1. an electronic substrate, is characterized in that, comprises:

base;

a protrusion disposed on the base; and

bonding pads disposed on the substrate;

wherein the bond pads do not overlap the boundaries of the protrusions.

2 . The electronic substrate of claim 1 , wherein the gap between the bonding pad and the boundary falls within a range of 5 μm to 100 μm. 3 .

3 . The electronic substrate of claim 1 , wherein the protruding portion is formed of a flat layer. 4 .

4. The electronic substrate according to claim 3, wherein the flat layer is an organic insulating layer.

5. The electronic substrate of claim 3, further comprising:

an insulating layer is provided on the protruding part,

wherein the bonding pads are disposed on the insulating layer.

6. An electronic device, characterized in that, comprising:

The electronic substrate of claim 1; and

The electronic component is electrically connected to the bonding pad of the electronic substrate.

7. The electronic device according to claim 6, wherein the electronic device is a light-emitting device.

8. The electronic device according to claim 6, wherein the electronic component is a light emitting diode.

9. The electronic device according to claim 8, further comprising:

The display panel is arranged on the transmission path of the light beam from the light emitting diode.

10 . The electronic device according to claim 6 , wherein the electronic device comprises a plurality of the electronic substrates, and the plurality of the electronic substrates are spliced together. 11 .