CN113971386A - Simulation method of integrated circuit - Google Patents
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Abstract
A method of simulating an integrated circuit, comprising: providing an initial unit circuit layout, wherein the initial unit circuit layout comprises a plurality of initial interconnection patterns; obtaining interconnection cutting layer information; performing analog processing on the initial unit circuit layout according to the interconnection cutting layer information to obtain a preset unit circuit layout; and establishing a post-netlist according to the preset unit circuit layout. By the simulation method of the integrated circuit, the accuracy and the reliability of the simulation result of the integrated circuit can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a simulation method of an integrated circuit.
Background
With the rapid development of the very large scale integrated circuit process, the number of components in the integrated circuit is increasing, and the size of the integrated circuit is becoming smaller and smaller, so that the components need to be connected by increasing metal interconnection layers, thereby increasing the speed and the integration level of the chip.
In an advanced process, after the layout design of an Integrated Circuit (IC) is finished, the layout of the IC is simulated, so that whether the design scheme of the IC meets the requirements or not is judged.
Judging whether the design scheme of the integrated circuit meets the requirements mainly comprises two aspects: on one hand, it is determined whether the circuit function of each unit circuit in each integrated circuit meets the design standard, and on the other hand, there are many timing violations during the chip design process, so that the timing correctness needs to be verified by timing Analysis (Time Analysis) during the design.
Timing Analysis typically includes Dynamic Timing Analysis (Dynamic Timing Analysis) and Static Timing Analysis (STA). The dynamic timing analysis mainly uses the input vector as the stimulus to verify the timing function of the whole design, whether the dynamic timing analysis is accurate or not depends on the coverage rate of the input stimulus, and the biggest disadvantage is that the speed is very slow, for example, when a million gates (gate) design is subjected to a full coverage test, the time spent on the design needs to be calculated in a month unit. Static Timing analysis analyzes whether a specific circuit violates a Timing Constraint given by a designer by applying a specific Timing Model (Timing Model). Compared with dynamic time sequence analysis, static time sequence analysis has high speed because input excitation is not needed, and meanwhile, because the static time sequence analysis is Based on Path analysis (Path Based) and adopts exhaustive logic, whether all synchronous logic violates the constraint or not can be theoretically analyzed.
Generally, when determining whether the circuit function of each unit circuit in the integrated circuit meets the design standard, a post-netlist of each unit circuit needs to be obtained based on the design scheme of the integrated circuit, and verification is performed according to data of the post-netlist. When the time sequence analysis is carried out, the time sequence analysis is carried out on the integrated circuit according to the data of the post-simulated netlist and the corresponding preparation process parameters. Therefore, in the process of simulating the layout of the integrated circuit, whether the data of the post-simulated netlist is accurate is particularly important.
However, the existing post-simulation netlist data is still not accurate enough, which results in inaccurate and unreliable results of simulation of the layout of the integrated circuit.
Disclosure of Invention
The invention solves the technical problem of providing a simulation method of an integrated circuit, so as to increase the accuracy and reliability of the simulation result of the layout of the integrated circuit.
In order to solve the above technical problem, a technical solution of the present invention provides a simulation method for an integrated circuit, including: providing an initial unit circuit layout, wherein the initial unit circuit layout comprises a plurality of initial interconnection patterns; obtaining interconnection cutting layer information; performing analog processing on the initial unit circuit layout according to the interconnection cutting layer information to obtain a preset unit circuit layout; and establishing a post-netlist according to the preset unit circuit layout.
Optionally, the method for obtaining the interconnection cutting layer information includes: providing a layout of an interconnection cutting layer; and acquiring the information of the interconnection cutting layer according to the interconnection cutting layer layout.
Optionally, the interconnection cutting layer layout comprises a plurality of interconnection cutting patterns; the interconnect cutting layer information includes: the shape and position of a number of said interconnected cutting patterns.
Optionally, the interconnection cutting layer layout comprises a plurality of interconnection cutting patterns; the interconnect cutting layer information includes: information embodying the shape and position of a number of said interconnected cutting patterns.
Optionally, the method of analog processing includes: acquiring a plurality of to-be-processed graphs according to the interconnection cutting layer information and the initial unit circuit layout, wherein the to-be-processed graphs are initial interconnection graphs which are adjacent to the interconnection cutting graphs and have different extension directions; and extending all the to-be-processed graphs to corresponding associated boundaries along the extending direction of the to-be-processed graphs to form first interconnection graphs, wherein the corresponding associated boundaries are boundaries of the interconnection cutting graphs adjacent to the corresponding to-be-processed graphs.
Optionally, the post-emulated netlist comprises a first post-emulated netlist, and the first post-emulated netlist comprises first RC information.
Optionally, the method for establishing the first post-netlist according to the preset unit circuit layout includes: and acquiring the first RC information according to the initial interconnection graph and the first interconnection graph of the preset unit circuit layout.
Optionally, the first post-netlist further includes first MOS transistor information.
Optionally, the initial unit circuit layout further includes a plurality of MOS device patterns, and the MOS device patterns of the preset unit circuit layout are the same as the MOS device patterns of the initial unit circuit layout; the method for establishing the first post-simulation netlist according to the preset unit circuit layout further comprises the following steps: and acquiring the information of the first MOS transistor according to the MOS device graph of the preset unit circuit layout.
Optionally, the first MOS transistor information includes ss process corner information.
Optionally, the method further includes: and establishing a first time sequence model according to the first post-simulated netlist.
Optionally, the method further includes: and establishing a second post-simulation netlist according to the initial unit circuit layout.
Optionally, the method for establishing the second post-netlist according to the initial unit circuit layout includes: and acquiring the second RC information according to the initial interconnection graph of the initial unit circuit layout.
Optionally, the method for establishing the second post-netlist according to the initial unit circuit layout further includes: and acquiring the second MOS transistor information according to the MOS device graph of the initial unit circuit layout, wherein the second MOS transistor information comprises ff process angle information.
Optionally, the method further includes: and establishing a second time sequence model according to the second post-simulation netlist.
Optionally, the method further includes: performing a first unit circuit function test according to the first post-simulated netlist to obtain a first circuit function test result; performing a second unit circuit function test according to the second post-simulation netlist to obtain a second circuit function test result; and acquiring a circuit function judgment result according to the first circuit function test result and the second circuit function test result, wherein the circuit function judgment result comprises that the circuit function is qualified or the circuit function is unqualified.
Optionally, the method for obtaining the circuit function judgment result includes: providing a design specification standard; when the first circuit function test result is in the design specification standard range and the second circuit function test result is in the design specification standard range, the circuit function judgment result is that the circuit function is qualified; and when the first circuit function test result or the second circuit function test result is out of the design specification standard range, the circuit function judgment result is that the circuit function is unqualified.
Optionally, the method further includes: and when the circuit function judgment result indicates that the circuit function is qualified, simulating the integrated circuit according to the first time sequence model and the second time sequence model to obtain a simulation result of the integrated circuit.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the simulation method of the integrated circuit provided by the technical scheme of the invention, the initial unit circuit layout is subjected to simulation processing according to the interconnection cutting layer information so as to obtain the preset unit circuit layout, and the preset unit circuit layout can preset the modification (extension) condition of a plurality of initial interconnection patterns in the subsequent design of the top layer circuit layout. Because the post-netlist is established according to the preset unit circuit layout, the post-netlist can reflect the information data of a plurality of modified (prolonged) preset initial interconnection patterns, and therefore the precision of the post-netlist for the initial unit circuit layout is improved. The precision of the post-netlist aiming at the initial unit circuit layout is improved, so that on one hand, the precision of a subsequent time sequence model established through the post-netlist can be improved, the precision and the reliability of a simulation result can be improved in the subsequent process of simulating the integrated circuit according to the time sequence model, on the other hand, whether the circuit function of the initial unit circuit layout is qualified or not can be accurately judged in the subsequent process, and therefore the initial unit circuit layout capable of being simulated by the integrated circuit can be accurately screened.
Drawings
FIG. 1 is a flow diagram of a method of simulating an integrated circuit;
FIG. 2 is a layout diagram of a cell circuit of an integrated circuit;
FIG. 3 is a flow chart illustrating a method for simulating an integrated circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an initial cell circuit layout according to one embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an interconnect cutting layer layout according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a preset cell circuit layout according to an embodiment of the present invention.
Detailed Description
As described in the background art, the existing post-simulation netlist data is still not accurate enough, resulting in inaccurate results of simulation of the layout of the integrated circuit. The analysis will now be described with reference to specific examples.
FIG. 1 is a flow diagram of a method of simulating an integrated circuit.
Fig. 2 is a layout diagram of a cell circuit of an integrated circuit.
Referring to fig. 1, the method for simulating an integrated circuit includes:
step S100, providing a layout of a unit circuit;
step S110, establishing a back-simulated netlist of the layout of the unit circuit according to the layout of the unit circuit;
step S120, establishing a unit circuit time sequence model according to the post-simulated netlist;
step S130, according to the post-simulated netlist, performing a unit circuit function test, and obtaining a unit circuit function test result;
step S140, providing a design specification standard, and comparing the functional test result of the unit circuit with the design specification standard;
when the result of the unit circuit function test is out of the design specification standard range, executing step S150; when the result of the unit circuit function test is within the design specification standard range, the step S160 is continuously performed.
And S150, judging that the layout design of the unit circuit is unqualified, and modifying the layout of the unit circuit.
And step S160, carrying out integrated circuit simulation according to the unit circuit time sequence model.
The layout 10 (shown in fig. 2) of the unit circuit includes: a plurality of first interconnection patterns 11, the first interconnection patterns 11 being used to form the first interconnection structure.
The layout 10 of the cell circuit is used for the subsequent formation of an integrated circuit.
The post-imitative netlist comprises RC information and MOS tube information, and when the MOS tube information comprises ss process corner information, a first time sequence model is established through the post-imitative netlist; and when the MOS tube information comprises ff process angle information, establishing a second time sequence model through the post-imitative netlist.
Therefore, the integrated circuit can be simulated according to the first time sequence model and the second time sequence model, and the time sequence delay condition of the integrated circuit can be obtained.
It should be noted that, for ease of understanding, only a part of the first interconnection pattern 11 in the layout 10 of the unit circuit is schematically shown in fig. 2.
However, in order to increase the integration of the integrated circuit, during the subsequent design of the top-level circuit, the layouts 10 of the plurality of unit circuits need to be spliced. After the layouts 10 of the plurality of unit circuits are connected, on one hand, in the layout 10 of each unit circuit, the end portion pitch S2 (not shown) between the first interconnection patterns 11 which are partially adjacent to each other is small, and on the other hand, the end portion pitch S1 (shown in fig. 2) between the first interconnection patterns 11 and the integrated interconnection pattern 21 (shown in fig. 2) of the top-layer circuit layout is small. Since the end portion pitch S2 and the end portion pitch S1 are small, it is necessary to disconnect the connected first interconnect pattern 11 and integrated interconnect pattern 21 by the interconnect cutting pattern 20 (as shown in fig. 2) to form a first interconnect structure, an integrated interconnect structure corresponding to the portion of the first interconnect pattern 11, the integrated interconnect pattern 21.
On the one hand, in order to reduce the area occupied by the interconnect cutting structures formed by the interconnect cutting pattern 20 and reduce the influence of the interconnect cutting structures on the formation positions of other semiconductor structures, thereby resulting in a smaller critical dimension of the interconnect cutting pattern 20, on the other hand, one interconnect cutting pattern 20 may need to cope with different terminal pitches S1 and S2 in order to correspond to the terminal pitch S1 and S2, which are the smallest among the terminal pitches S1 and S2, thereby also resulting in a smaller critical dimension of the interconnect cutting pattern 20. Thus, after the layout design of the unit circuit is completed, the part of the first interconnection pattern 11 needs to be modified to fit the interconnection cut pattern 20. Namely: after the layout 10 of the unit circuit is designed, in the subsequent top-level circuit design, part of the first interconnection pattern 11 is extended to the interconnection cutting pattern 20 to form an additional first interconnection pattern 13 (as shown in fig. 2).
Due to the formation of the supplemental first interconnection pattern 13, parasitic resistance and parasitic capacitance corresponding to the layout 10 of the cell circuit are increased, resulting in poor RC information accuracy of the layout 10 of the cell circuit in the post-emulated netlist created by the above-described simulation method of an integrated circuit, i.e., poor data accuracy of the post-emulated netlist. Therefore, the result of the unit circuit function test performed through the post-imitative netlist is not reliable. Meanwhile, the RC information accuracy mainly reflects the resistance-capacitance delay condition, so that parasitic resistance and parasitic capacitance are increased, resulting in poor RC information accuracy, and the first timing model established based on the post-simulated netlist has poor accuracy, that is: and the time sequence model established according to the post-simulated netlist is difficult to reflect the time sequence delay condition of the unit circuit limit (worst). Due to the poor precision of the first timing model, the simulation result of the integrated circuit is inaccurate, and the limit condition of the timing delay of the integrated circuit cannot be accurately estimated.
In order to solve the technical problem, an embodiment of the present invention provides a simulation method for an integrated circuit, in which a preset unit circuit layout of each unit circuit is obtained according to interconnection cutting pattern layer information and each initial unit circuit layout, and a post-netlist based on the preset unit circuit layout is established according to each preset unit circuit layout, so that data accuracy of the post-netlist is improved, and accuracy and reliability of a simulation result are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 3 is a flowchart illustrating a simulation method of an integrated circuit according to an embodiment of the invention.
Referring to fig. 3, the method for simulating an integrated circuit includes:
step S200, providing an initial unit circuit layout, wherein the initial unit circuit layout comprises a plurality of initial interconnection patterns.
After step S200 is executed, step S210 and step S220 are executed, respectively.
Step S210, obtaining interconnection cutting layer information.
After step S210 is performed, steps S211 to S214 are sequentially performed.
And step S211, performing analog processing on the initial unit circuit layout according to the interconnection cutting layer information to obtain a preset unit circuit layout.
And S212, establishing a post-imitative netlist according to the preset unit circuit layout, wherein the post-imitative netlist comprises a first post-imitative netlist.
And step S213, establishing a first time sequence model according to the first post-simulation netlist.
And S214, performing a first unit circuit function test according to the first post-netlist to obtain a first circuit function test result.
And S220, establishing a second post-simulation netlist according to the initial unit circuit layout.
After step S220 is performed, steps S221 to S222 are sequentially performed.
And step S221, establishing a second time sequence model according to the second post-simulation netlist.
And step S222, performing a second unit circuit function test according to the second post-netlist to obtain a second circuit function test result.
After steps S214 and S222 are executed, step S230 is executed.
Step S230, obtaining a circuit function judgment result according to the first circuit function test result and the second circuit function test result, where the circuit function judgment result includes a circuit function passing or a circuit function failing.
When the circuit function determination result is that the circuit function is not qualified, step S240 is executed.
In step S240, the initial unit circuit layout is modified.
After step S240 is executed, the modified initial unit one-way layout is used as the initial unit circuit layout in step S200, and step S200 is executed again, and the above steps are repeated until the circuit function judgment result is that the circuit function is qualified.
When the circuit function is qualified as the circuit function judgment result, step S250 is executed.
And step S250, simulating the integrated circuit according to the first time sequence model and the second time sequence model, and obtaining a simulation result of the integrated circuit.
Because the initial unit circuit layout is subjected to analog processing according to the interconnection cutting layer information so as to obtain the preset unit circuit layout, the preset unit circuit layout can be preset in the design of the top layer circuit layout to modify (prolong) the condition of a plurality of initial interconnection patterns. Because the post-netlist is established according to the preset unit circuit layout, the post-netlist can reflect the information data of a plurality of modified (prolonged) preset initial interconnection patterns, and therefore the precision of the post-netlist for the initial unit circuit layout is improved. The precision of the post-imitative netlist aiming at the initial unit circuit layout is improved, and meanwhile, the post-imitative netlist comprises the first post-imitative netlist, so that on one hand, the precision of the first time sequence model established by the first post-imitative netlist can be improved, the precision and the reliability of a simulation result can be improved in the process of simulating the integrated circuit according to the first time sequence model, on the other hand, whether the circuit function of the initial unit circuit layout is qualified or not can be judged more accurately, and therefore the initial unit circuit layout capable of being simulated by the integrated circuit can be screened more accurately.
The following detailed description is made with reference to the accompanying drawings.
FIG. 4 is a schematic diagram of an initial cell circuit layout according to one embodiment of the invention.
Referring to fig. 4, step S200 is executed to provide an initial cell circuit layout 200, where the initial cell circuit layout 200 includes a plurality of initial interconnection patterns 201.
The initial cell circuit layout 200 is used to form a cell circuit, and the initial interconnection pattern 201 is used to form a cell electrical interconnection structure in the cell circuit.
It should be noted that, when designing an integrated circuit, a plurality of initial unit circuit layouts 200 need to be designed respectively, and then, a top-level circuit layout is designed to form a complete integrated circuit layout, so that unit circuits corresponding to the initial unit circuit layouts 200 can be electrically connected according to design requirements through top-level circuits corresponding to the top-level circuit layouts. Since each initial unit circuit layout 200 is designed according to actual functional requirements, each unit circuit layout 200 may be the same or different according to the same or different actual functional requirements for each initial unit one-way layout 200.
It should be noted that, in order to facilitate understanding of the simulation method of the integrated circuit described in the present embodiment, 3 initial interconnect patterns 201 are schematically illustrated in fig. 4. Since the initial cell one-way layout 200 is designed according to actual functional requirements, the number of the actual initial interconnection patterns 201 may be 1 or more, and the shape of the actual initial interconnection patterns 201 may also be different from the shape of the initial interconnection patterns 201 shown in fig. 4. The number and shape of the initial interconnect patterns 201 does not affect the effect of the simulation method of the integrated circuit.
In this embodiment, the initial unit circuit layout 200 further includes a plurality of semiconductor device patterns, including MOS device patterns (not shown).
The semiconductor device pattern is used for forming a semiconductor device of a unit circuit, and the MOS device pattern is used for forming an MOS tube in the semiconductor device.
In other embodiments, the semiconductor device pattern further includes a pattern of resistors, capacitors, and the like.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a layout of an interconnect cutting layer according to an embodiment of the present invention, and step S210 is executed to obtain information of the interconnect cutting layer.
In this embodiment, the method for acquiring the interconnection cutting layer information includes: providing an interconnection cutting layer layout (not marked in the figure); and acquiring the information of the interconnection cutting layer according to the interconnection cutting layer layout.
The interconnect cutting layer layout comprises a plurality of interconnect cutting patterns 301, and the interconnect cutting patterns 301 have boundaries 302 of the interconnect cutting patterns 301.
It should be noted that the interconnect cutting layer layout is used for forming an interconnect cutting layer, and the interconnect cutting pattern 301 is used for forming an interconnect cutting structure in the interconnect cutting layer. In the process of designing the integrated circuit, in order to improve the integration level of the integrated circuit, the top layer circuit layout comprises a top layer interconnection structure layout and an interconnection cutting layer layout, so that on one hand, a plurality of top layer electrical interconnection structures are formed through the top layer interconnection structure layout to realize the electrical connection between each unit circuit, on the other hand, a plurality of top layer electrical interconnection structures can be separated through a semiconductor structure formed by transferring the shape of a plurality of interconnection cutting patterns 301 in the interconnection cutting layer layout, and therefore, the unit electrical interconnection structures of each unit circuit, the semiconductor devices of each unit circuit and the plurality of top layer electrical interconnection structures can be realized according to the design requirements, And electrical isolation between the semiconductor devices of each unit circuit and the top-level electrical interconnect structures.
In this embodiment, the interconnect cutting layer information includes: the shape and location of several of the interconnected cutting patterns 301.
It should be noted that, in order to facilitate understanding of the simulation method of the integrated circuit described in this embodiment, fig. 5 schematically illustrates 1 interconnect cutting pattern 301 in the interconnect cutting layer layout. Since the interconnect cutting layer layout is designed according to the actual requirement on electrical insulation, the number of the actual interconnect cutting patterns 301 may be 1 or multiple, and the shape of the actual interconnect cutting patterns 301 may also be different from the shape of the interconnect cutting patterns 301 shown in fig. 5. The number and shape of the interconnect cutting patterns 301 do not affect the effect of the simulation method of the integrated circuit.
It should be noted that, in order to facilitate understanding of the simulation method of the integrated circuit described in this embodiment, in fig. 5, 1 illustrated interconnect cut pattern 301 is overlapped with the initial unit circuit layout 200 shown in fig. 4, so as to illustrate the corresponding position of the interconnect cut pattern 301 in the initial unit circuit layout 200.
In other embodiments, the interconnect cutting layer information includes: the information representing the shape and position of the plurality of interconnected cutting patterns is, for example, coordinate data representing the shape and position of the plurality of interconnected cutting patterns.
In the present embodiment, after step S200 is performed, step S210 is performed.
In other embodiments, step S200 is performed after step S210 is performed. Alternatively, step S200 and step S210 are performed simultaneously.
Since the steps S200 and S210 are performed for the purpose of performing the subsequent simulation process on the initial unit circuit layout 200, i.e. performing step S211, the execution sequence between step S200 and step S210 does not affect the effect of the simulation method of the integrated circuit.
Referring to fig. 6, fig. 6 is a schematic diagram of a preset unit circuit layout according to an embodiment of the present invention, and after step S200 and step S210 are executed, step S211 is executed, and the initial unit circuit layout 200 (shown in fig. 4) is subjected to simulation processing according to the interconnection cutting layer information to obtain the preset unit circuit layout 210.
In this embodiment, the method of simulation processing includes: acquiring a plurality of to-be-processed graphs (not marked in the figure) according to the interconnection cutting layer information and the initial unit circuit layout 200, wherein the to-be-processed graphs are initial interconnection graphs 201 which are adjacent to the interconnection cutting graphs 301 and have different extending directions; and extending all the to-be-processed graphs to corresponding associated boundaries 303 along the extending direction of the to-be-processed graphs to form first interconnection graphs 211, wherein the corresponding associated boundaries are boundaries 302 of the interconnection cutting graphs 301 adjacent to the corresponding to-be-processed graphs.
In this embodiment, in the simulation process, all of the initial interconnect patterns 201 that are adjacent to the interconnect cutting pattern 301 and have different extending directions are processed (extend to the corresponding associated boundary 303), so that the preset unit circuit layout 210 can preset the most extreme influence of the top circuit layout design on the initial unit circuit layout 200, that is: the situation where the maximum number of initial interconnect patterns 201 are extended by the limit during the top-level circuit layout design process.
It should be noted that, in order to facilitate understanding of the simulation method, a dashed box a is shown in fig. 6, and a portion of the first interconnection pattern 211 is extended from a corresponding initial interconnection pattern 201 (shown in fig. 4) before the simulation.
In another embodiment, the method of analog processing further comprises: acquiring a plurality of to-be-processed graphs according to the interconnection cutting layer information and the initial unit circuit layout, wherein the to-be-processed graphs are initial interconnection graphs which are adjacent to the interconnection cutting graphs and have different extension directions; and extending 50% of the graph to be processed to a corresponding associated boundary along the extending direction of the graph to be processed to form a first interconnection graph, wherein the corresponding associated boundary is the boundary of the interconnection cutting graph adjacent to the corresponding graph to be processed. Therefore, compared with the most extreme influence, the preset unit circuit layout can preset the condition that the top layer circuit layout design has 50% influence on the initial unit circuit layout, namely: in the top circuit layout design process, 50% of the initial interconnect pattern is extended.
Since the simulation process does not include the process of the semiconductor device pattern in the initial unit circuit layout 200, the MOS device pattern of the preset unit circuit layout 210 is the same as the MOS device pattern of the initial unit circuit layout 200.
Continuing to refer to fig. 6, after obtaining the preset unit circuit layout 210, then executing step S212, and establishing a post-netlist according to the preset unit circuit layout 210, where the post-netlist includes a first post-netlist; after step S212, step S213 is executed to establish a first timing model according to the first post-emulated netlist.
In this embodiment, the first post-copy netlist includes first RC information.
In this embodiment, the first post-copy netlist further includes first MOS transistor information.
In other embodiments, the first post-copy netlist does not include first MOS transistor information.
In this embodiment, the first MOS transistor information includes ss process corner information.
In this embodiment, the first timing model may be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis).
Specifically, in this embodiment, the method for creating the first post-netlist according to the preset cell circuit layout 210 includes: acquiring the first RC information according to the initial interconnection pattern 201 and the first interconnection pattern 211 of the preset unit circuit layout 210; and acquiring the information of the first MOS transistor according to the MOS device graph of the preset unit circuit layout 210.
It should be noted that, in the actual manufacturing process of the integrated circuit, due to the influence of the precision of the manufacturing process, the actually formed integrated circuit is prone to have a deviation from the integrated circuit corresponding to the integrated circuit layout, which results in the inconsistency of the characteristics shown between the actual integrated circuit and the designed integrated circuit. The ss process corner information refers to relevant process parameter data in the actual manufacturing process of the integrated circuit under the condition that the reaction speed of formed MOS (including NMOS (N-channel metal oxide semiconductor) tubes and PMOS (P-channel metal oxide semiconductor) tubes is the slowest, namely, under the condition that the manufacturing process precision is the worst.
Since the first RC information is obtained according to the initial interconnection pattern 201 and the first interconnection pattern 211 of the preset unit circuit layout 210, the first RC information includes related data information of the most extreme influence of the top-level circuit layout design on the initial unit circuit layout 200. Since the first MOS transistor information is obtained according to the MOS device pattern of the preset unit circuit layout 210, and the first MOS transistor information includes ss process corner information, the first MOS transistor information includes related data information of the semiconductor device corresponding to the initial unit circuit layout 200 when the manufacturing process deviation is the largest. Therefore, the first post-netlist not only includes the worst influence caused by the precision of the manufacturing process, but also includes the most extreme influence caused by the layout design of the top-layer circuit, so that the precision of the first post-netlist can be higher.
Because the first time sequence model is established according to the first post-simulation netlist, the first time sequence model not only can reflect the most extreme influence of the precision of the manufacturing process on the unit circuit, but also can reflect the most extreme influence of the top-layer circuit layout design on the unit electrical interconnection structure, so that the first time sequence model can more accurately reflect the slowest time sequence condition of the unit circuit after the initial unit circuit layout 200 is influenced by the top-layer circuit layout design, namely, the precision of the ss process corner in the simulation is improved. And when the integrated circuit is simulated according to the first time sequence model in the follow-up process, the precision and the reliability of the simulation result are improved.
In another embodiment, after 50% of the to-be-processed patterns extend to corresponding associated boundaries along the extending direction of the to-be-processed patterns to form first interconnection patterns, after a preset unit circuit layout is obtained, a post-netlist is built according to the preset unit circuit layout, the post-netlist includes a third post-netlist, and a third timing model is built according to the third post-netlist, wherein the third timing model may be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis). Therefore, compared with the most extreme influence, the third post-simulation netlist comprises related data information when the top-layer circuit layout design has 50% influence on the initial unit circuit layout, and the accuracy of the tt process corner in simulation is improved.
In this embodiment, after step S213, step S214 is executed to perform a first unit circuit function test according to the first post-netlist, and obtain a first circuit function test result.
It should be noted that the first circuit function test result is data representing a unit circuit function corresponding to the preset unit circuit layout 210, that is, data representing a circuit function of a unit circuit which is most affected by the worst manufacturing process deviation and the top circuit layout design.
Similarly, the precision of the first post-netlist is improved, so that a first circuit function test result with higher precision can be obtained after a first unit circuit function test is performed according to the first post-netlist.
In other embodiments, step S213 is performed after step S214 is performed. Alternatively, step S214 and step S213 are performed simultaneously.
It should be noted that the sequence between step S213 and step S214 does not affect the effect of the simulation method of the integrated circuit.
Continuing to refer to fig. 4, after step S200, executing step S220, and establishing a second post-netlist according to the initial unit circuit layout 200; after step S220, step S221 is executed to establish a second timing model according to the second post-netlist.
In this embodiment, the second post-copy netlist includes second RC information.
In this embodiment, the second post-copy netlist further includes second MOS transistor information.
In other embodiments, the second post-copy netlist does not include second MOS transistor information.
In this embodiment, the second MOS transistor information includes ff process corner information.
In this embodiment, the second timing model may be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis).
Specifically, in this embodiment, the method for creating the second post-netlist according to the initial cell circuit layout 200 includes: acquiring the second RC information according to the initial interconnection graph 201 of the initial unit circuit layout 200; and acquiring the information of the second MOS transistor according to the MOS device graph of the initial unit circuit layout 200.
The ff process corner information is related process parameter data when the reaction speed of the formed MOS (including NMOS and PMOS) transistor is the fastest, namely, the manufacturing process precision is the best, in the actual manufacturing process of the integrated circuit.
Since the second RC information is obtained according to the initial interconnection pattern 201 of the initial unit circuit layout 200, the second RC information includes related data information when the top-level circuit layout design has no influence on the initial unit circuit layout 200. Because the second MOS transistor information is obtained according to the MOS device graph of the initial unit circuit layout 200, and the second MOS transistor information includes ff process corner information, the second MOS transistor information includes related data information of the semiconductor device corresponding to the initial unit circuit layout 200 when the manufacturing process deviation is minimum. Therefore, the second post-simulated netlist includes related data information with minimal impact caused by manufacturing process deviations and minimal impact caused by top-level circuit layout design.
And establishing a second time sequence model according to the second post-simulated netlist, so that the second time sequence model can embody the fastest time sequence condition of the unit circuit.
In this embodiment, after step S221, step S222 is executed to perform a second unit circuit function test according to the second post-netlist, so as to obtain a second circuit function test result.
It should be noted that the second circuit function test result is data representing the unit circuit function corresponding to the initial unit circuit layout 200, that is, data representing the circuit function of the unit circuit when the circuit layout is not affected by the design of the top circuit layout while receiving the least manufacturing process deviation.
In other embodiments, step S221 is performed after step S222 is performed. Alternatively, step S222 and step S221 are performed simultaneously.
It should be noted that the sequence between step S221 and step S222 does not affect the effect of the simulation method of the integrated circuit.
In the present embodiment, after the steps S214 and S222 are executed, the step S230 is executed.
Step S230, obtaining a circuit function judgment result according to the first circuit function test result and the second circuit function test result, where the circuit function judgment result includes a circuit function passing or a circuit function failing.
Since the accuracy of the first circuit function test result is improved, it is possible to more accurately determine whether the circuit function of the initial unit circuit layout 200 is qualified, and thus, the initial unit circuit layout 200 on which the integrated circuit can be simulated can be more accurately screened.
Specifically, in this embodiment, the method for acquiring the circuit function determination result includes: providing a design specification standard; when the first circuit function test result is in the design specification standard range and the second circuit function test result is in the design specification standard range, the circuit function judgment result is that the circuit function is qualified; and when the first circuit function test result or the second circuit function test result is out of the design specification standard range, the circuit function judgment result is that the circuit function is unqualified.
It should be noted that, because the sequence among step S213, step S221 and step S230 does not affect the effect of the simulation method of the integrated circuit, in other embodiments, step S213 and step S221 can also be executed after step S230, or step S213 or step S221 and step S230 can be executed simultaneously.
Next, in this embodiment, when the circuit function determination result is that the circuit function is not qualified, step S240 is executed to modify the initial unit circuit layout 200.
After step S240 is executed, the modified initial unit one-way layout is used as the initial unit circuit layout in step S200, and step S200 is executed again, and the above steps are repeated until the circuit function judgment result is that the circuit function is qualified.
In other embodiments, step S240 is not performed, and the initial cell one-way layout 200 is abandoned and a new initial cell circuit layout is redesigned.
In this embodiment, when the circuit function determination result indicates that the circuit function is qualified, step S250 is executed to simulate the integrated circuit according to the first timing model and the second timing model, and obtain a simulation result of the integrated circuit.
The first timing model can reflect the slowest timing condition of the unit circuit after the initial unit circuit layout 200 is influenced by the design of the top circuit layout more accurately, so that the precision of the simulation result of the integrated circuit is improved, the range of the timing of the integrated circuit is simulated more accurately, and the precision and the reliability of the simulation result are improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of simulating an integrated circuit, comprising:
providing an initial unit circuit layout, wherein the initial unit circuit layout comprises a plurality of initial interconnection patterns;
obtaining interconnection cutting layer information;
performing analog processing on the initial unit circuit layout according to the interconnection cutting layer information to obtain a preset unit circuit layout;
and establishing a post-netlist according to the preset unit circuit layout.
2. The method for simulating an integrated circuit according to claim 1, wherein the method of acquiring the interconnect cutting layer information includes: providing a layout of an interconnection cutting layer; and acquiring the information of the interconnection cutting layer according to the interconnection cutting layer layout.
3. The method of simulating an integrated circuit according to claim 2, wherein the interconnect cut layer layout comprises a plurality of interconnect cut patterns; the interconnect cutting layer information includes: the shape and position of a number of said interconnected cutting patterns.
4. The method of simulating an integrated circuit according to claim 2, wherein the interconnect cut layer layout comprises a plurality of interconnect cut patterns; the interconnect cutting layer information includes: information embodying the shape and position of a number of said interconnected cutting patterns.
5. A method of simulating an integrated circuit as claimed in claim 3 or 4, characterized in that the method of simulation processing comprises: acquiring a plurality of to-be-processed graphs according to the interconnection cutting layer information and the initial unit circuit layout, wherein the to-be-processed graphs are initial interconnection graphs which are adjacent to the interconnection cutting graphs and have different extension directions; and extending all the to-be-processed graphs to corresponding associated boundaries along the extending direction of the to-be-processed graphs to form first interconnection graphs, wherein the corresponding associated boundaries are boundaries of the interconnection cutting graphs adjacent to the corresponding to-be-processed graphs.
6. The method for simulating an integrated circuit of claim 5 wherein the post-replica netlist comprises a first post-replica netlist, the first post-replica netlist comprising first RC information.
7. The method for simulating an integrated circuit according to claim 6, wherein the method for creating a first post-simulation netlist based on the pre-defined cell circuit layout comprises: and acquiring the first RC information according to the initial interconnection graph and the first interconnection graph of the preset unit circuit layout.
8. The method for simulating an integrated circuit of claim 7 wherein the first post-simulation netlist further comprises first MOS transistor information.
9. The method of simulating an integrated circuit according to claim 8, wherein the initial unit circuit layout further includes a plurality of MOS device patterns, the MOS device patterns of the preset unit circuit layout being the same as the MOS device patterns of the initial unit circuit layout; the method for establishing the first post-simulation netlist according to the preset unit circuit layout further comprises the following steps: and acquiring the information of the first MOS transistor according to the MOS device graph of the preset unit circuit layout.
10. The method for simulating an integrated circuit of claim 9 wherein said first MOS transistor information comprises ss process corner information.
11. The method for simulating an integrated circuit of claim 10, further comprising: and establishing a first time sequence model according to the first post-simulated netlist.
12. The method for simulating an integrated circuit of claim 11, further comprising: and establishing a second post-simulation netlist according to the initial unit circuit layout.
13. The method for simulating an integrated circuit of claim 12 wherein the method for creating a second post-simulation netlist from said initial cell circuit layout comprises: and acquiring the second RC information according to the initial interconnection graph of the initial unit circuit layout.
14. The method for simulating an integrated circuit of claim 13 wherein the method for creating a second post-simulation netlist from said initial cell circuit layout further comprises: and acquiring the second MOS transistor information according to the MOS device graph of the initial unit circuit layout, wherein the second MOS transistor information comprises ff process angle information.
15. The method for simulating an integrated circuit of claim 14, further comprising: and establishing a second time sequence model according to the second post-simulation netlist.
16. The method for simulating an integrated circuit of claim 15, further comprising: performing a first unit circuit function test according to the first post-simulated netlist to obtain a first circuit function test result; performing a second unit circuit function test according to the second post-simulation netlist to obtain a second circuit function test result; and acquiring a circuit function judgment result according to the first circuit function test result and the second circuit function test result, wherein the circuit function judgment result comprises that the circuit function is qualified or the circuit function is unqualified.
17. The method for simulating an integrated circuit according to claim 16, wherein the step of obtaining the result of the circuit function determination comprises: providing a design specification standard; when the first circuit function test result is in the design specification standard range and the second circuit function test result is in the design specification standard range, the circuit function judgment result is that the circuit function is qualified; and when the first circuit function test result or the second circuit function test result is out of the design specification standard range, the circuit function judgment result is that the circuit function is unqualified.
18. The method for simulating an integrated circuit of claim 17, further comprising: and when the circuit function judgment result indicates that the circuit function is qualified, simulating the integrated circuit according to the first time sequence model and the second time sequence model to obtain a simulation result of the integrated circuit.
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