CN113970692B - Chip difference detection method and system - Google Patents
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- CN113970692B CN113970692B CN202111133531.4A CN202111133531A CN113970692B CN 113970692 B CN113970692 B CN 113970692B CN 202111133531 A CN202111133531 A CN 202111133531A CN 113970692 B CN113970692 B CN 113970692B
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- 238000001514 detection method Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000005070 sampling Methods 0.000 claims description 25
- 230000015654 memory Effects 0.000 claims description 21
- 238000004590 computer program Methods 0.000 claims description 8
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- 238000012360 testing method Methods 0.000 abstract description 19
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- 230000001105 regulatory effect Effects 0.000 description 1
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The embodiment of the application discloses a method and a system for detecting chip variability, which are applied to a system for detecting chip variability, wherein the system for detecting chip variability comprises a plurality of silicon chip classification and calibration SCC Type circuits and an SCC control circuit; the method comprises the following steps: the SCC Type circuits input the output SO signals to the SCC control circuit; the SCC control circuit calculates circuit delay values of a plurality of SCCType circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether the chip has electrical characteristic differences according to the SO signals and the circuit delay values. The application provides a method for mixing and lapping transistors of different types to form the basic SCCtype, which can obviously reduce the occupied area of the ROSC on the vehicle-standard chip with smaller overall size, ensure the coverage rate of the test and meet the requirement of the vehicle-standard with higher stability requirement on the chip yield.
Description
Technical Field
The application relates to the technical field of communication, in particular to a method and a system for detecting chip variability.
Background
The chip, also called microcircuit (microcircuit), microchip (microchip) and integrated circuit (INTEGRATED CIRCUIT), is a silicon chip containing integrated circuit, has small volume and is an important component of electronic equipment such as computer. The manufacturing of the chip is an inaccurate process, and the chips produced together may show obvious electrical characteristic differences at different positions, which may affect the operation stability of the chip, for example, when the applied voltage of the chip is 0.9V, the chip needs to operate to a 320MHz frequency region, part of logic may stably operate at the frequency, and part of logic may have timing violations, thereby causing abnormal chip behaviors. These chips, which are significantly different, cannot be screened out by automated test equipment (Automatic Test Equipment, ATE) testing. Therefore, how to perform chip variability detection is a problem that needs to be solved for vehicle-scale chips with extremely high chip stability requirements.
Disclosure of Invention
The embodiment of the application provides a method and a system for detecting chip variability, which are used for mixing and lapping different types of transistors to form a base SCCtype, so that the occupied area of a ROSC (remote control unit) on a vehicle-mounted chip with smaller overall size can be obviously reduced, the coverage rate of a test is ensured, and the requirement of a vehicle-mounted standard with higher stability requirement on the chip yield is met.
In a first aspect, an embodiment of the present application provides a method for detecting chip variability, which is applied to a chip variability detection system, where the chip variability detection system includes a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, each SCC Type circuit includes a plurality of ring oscillator ROSC chains, and each ROSC chain is formed by different types of transistors;
The method comprises the following steps:
The SCC Type circuits input the output SO signals to the SCC control circuit;
The SCC control circuit calculates circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values;
The SCC control circuit determines whether the chip has an electrical characteristic difference according to the plurality of SO signals and the plurality of circuit delay values.
In a second aspect, the system for detecting chip variability provided by the embodiment of the application comprises a plurality of SCC Type circuits and an SCC control circuit for classifying and calibrating silicon chips, wherein each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; wherein,
The SCC Type circuits are used for inputting the output SO signals into the SCC control circuit;
The SCC control circuit is used for calculating circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit is also used for determining whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values.
In a third aspect, an embodiment of the present application provides a detection apparatus comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing part or all of the steps described in the method of the first aspect above.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps described in the method of the first aspect.
In a fifth aspect, embodiments of the present application provide a computer program product comprising instructions which, when run on an electronic device, cause the electronic device to perform the method of the first aspect described above.
The technical scheme provided by the application is applied to a chip variability detection system, wherein the chip variability detection system comprises a plurality of silicon chip classification and calibration SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; the SCC Type circuits input the output SO signals to the SCC control circuit; the SCC control circuit calculates circuit delay values of a plurality of SCC Type circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether the chip has electrical characteristic differences according to the SO signals and the circuit delay values. According to the application, different types of transistors are used for mixing and lapping to form the base SCCtype, SO that the occupied area of the ROSC on the vehicle-standard chip with smaller overall size can be remarkably reduced, meanwhile, the difference of the electrical characteristics of the chip is reflected by the SO signal output by the SCC Type circuit, the coverage rate of the test is ensured, and the requirement of the vehicle-standard with higher stability requirement on the chip yield is met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip variability detection system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an SCC type circuit according to an embodiment of the present application;
FIG. 3 is a schematic flow chart of a method for detecting chip variability according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a detection device according to an embodiment of the present application.
Detailed Description
Before describing the technical scheme of the embodiment of the present application, the following describes related concepts possibly related to the present application.
Ring oscillator (RingOscillator, ROSC): the ring-shaped circuit is formed by adopting an odd number of inverters and is used for outputting square wave pulses, and the ring-shaped oscillator has the biggest characteristic of being capable of measuring circuit delay with high precision so as to characterize circuit aging.
Silicon wafer classification and calibration (SiliconCharacterizationandCalibration, SCC): the method is characterized in that the silicon wafers are classified according to physical differences shown after production and manufacture, parameters such as power supply voltage of the chips are correspondingly adjusted, and the chips can be ensured to operate under the given performance.
Binning: the (chip) classification refers to the classification of the chip into different bins according to the result output by the SCC, and is used for representing the differences shown by the different bins.
SCCType: and the minimum SCC execution unit consists of a plurality of ROSC and a shift register.
Voltage modulation (VoltageTuning, VT): the pressure regulating operation is specifically performed on scctype.
Automatic integrated circuit tester (AutomaticTestEquipment, ATE): the method is used for detecting the integrity of the integrated circuit function so as to ensure that the internal sequential logic of the chip can not run with hardware errors.
For better understanding of the technical solutions of the present application by those skilled in the art, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the description of the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, software, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip variability detection system according to an embodiment of the present application. As shown in fig. 1, the chip variability detection system 100 includes a plurality of silicon chip classifying and calibrating SCC Type circuits 110 and an SCC control circuit 120. The output of each SCC Type circuit 110 is connected to the SCC control circuit 120, each SCC Type circuit 110 performs chip differential screening on the chip, and the screened output result is sent to the SCC control circuit 120, and then the SCC control circuit 120 judges whether the chip has an electrical characteristic difference according to the output signal of each SCC Type circuit 110. For example, SCC control circuit 120 may connect external components via a BUS (BUS) and receive BUS Signals (Signals).
By way of example, as shown in FIG. 1, the SCC control circuit 120 may include an SCC Type interface, an SCC controller, and an SCC register set. The whole chip may include a plurality of SCC Type circuits 110, each bit represents an SCC Type circuit, and the SCC control can receive the SO signals output by the SCC Type circuits 110 through the SCC Type interface, and can select the SO signal of any one SCC Type to reflect the electrical characteristic difference of the circuits from the plurality of SO signals. Wherein the SCC register set may be used to store the final result and/or parameters required by the SCC controller.
As shown in fig. 2, fig. 2 is a schematic structural diagram of an SCC Type circuit 110 according to an embodiment of the present application. As shown in fig. 2, the SCC Type circuit includes a plurality of ring oscillator ROSC chains, each of which is composed of different kinds of transistors, and Lian Bo counters, and a ripple counter (ripplecounter) captures the square wave output by the ROSC and converts it into serial data output SO signals.
The ROSC includes different combinational logic (such as and gate, or gate, not gate, etc.), each logic selects a different kind of transistor according to a different kind of an actual selection unit (cell) in a test area (for example, not gate selects a type a transistor and gate selects a type B transistor), in actual process production, the produced transistors have process deviation, that is, the characteristics of the produced transistors have different characteristics, the difference is amplified by delay (delay) generated by an odd number of ring oscillators connected in series, (due to delay, the phase difference is amplified under superposition of a plurality of inverters, when the phase change reaches 180 degrees compared with an initial phase, circuit oscillation is realized), and by presetting a sampling period number (N), the oscillation number in the period can be used for representing the delay condition of the circuit by counting the oscillation number in the period through a counter. And then can represent the circuit delay value of the region is buried to the ROSC through the SO signal of SCC Type circuit output to reflect the electrical characteristic difference of circuit.
The SCC Type circuits are used for inputting the output SO signals into the SCC control circuit; the SCC control circuit is used for calculating circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values, and determining whether the chip has electrical characteristic differences according to the plurality of SO signals and the plurality of circuit delay values.
Specifically, the delay values of different logic units on the ROSC chain can cause the difference of SO signals output by the SCC Type, and the SCC control circuit can calculate the circuit delay value corresponding to the SO value through data conversion of the received SO signals SO as to represent the circuit delay value of the ROSC embedded region, SO that the difference of the electrical characteristics of the circuits is reflected.
Optionally, in calculating the circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values, the SCC control circuit is specifically configured to: acquiring sampling clock cycles of the SCC Type circuits to obtain a plurality of sampling clock cycles; respectively inputting the plurality of sampling clock periods into a first formula to calculate to obtain the plurality of circuit delay values, wherein the first formula is expressed as: g= (n×s)/T, where N is a preset sampling period number, S is the sampling clock period, and T is a constant.
The SCC register group in the SCC control circuit can store a set sampling period number N in advance, wherein the N can be any value. The T is a single cycle of the delay line on the ROSC chain, which is a constant, specifically related to the process, and its value is the time of one square wave period on the ROSC chain in the case of the process and transistor type, used to calculate the standard (golden) value of square wave number and the process related parameters.
Specifically, the SCC controller calculates a test value (circuit delay value), which is the number of square waves formed after the ROSC has passed through the sampling time, from the formula, and the value is a standard value. By comparing the circuit delay value obtained in actual test with a standard value, whether the tested chip has electrical property difference can be judged. Specifically, if the difference between the circuit delay value obtained in actual test and the standard value is greater than or equal to a preset value, the chip is considered to have the electrical characteristic difference; if the difference between the circuit delay value obtained in the actual test and the standard value is smaller than a preset value, the chip is considered to have no electrical property difference. The preset value may be preset or set according to actual requirements, which is not limited in the embodiment of the present application.
Optionally, the SCC control circuit is disposed in a power domain that can be powered down.
In the embodiment of the application, an SCC controller in an SCC control circuit performs data interaction with the outside through an SCC bus interface, and realizes interaction with a SCCtype circuit through a SCCtype interface. The SCC control circuit is arranged in a normally open power domain at present, so that the power consumption loss is larger, therefore, the SCC control circuit is integrally arranged in the power domain with the power failure of a chip, the SCC control circuit can be controlled to be turned on only when an ATE test is carried out, the logic and the functional logic of the SCC control circuit are not affected mutually when the SCC control circuit works normally, and the SCC control circuit can be turned off along with a system, so that the power consumption of the SCC control circuit in actual working is reduced, and the influence on the overall power consumption of the system is minimized.
Referring to fig. 3, fig. 3 is a flow chart of a method for detecting chip variability according to an embodiment of the present application, which is applied to the chip variability detection system shown in fig. 1. As shown in fig. 3, the method includes the following steps.
S310, the SCC Type circuits input the output SO signals into the SCC control circuit.
Wherein, possibly include a plurality of SCC Type circuits in a chip, include many different types of transistors in every SCC Type circuit and constitute the ROSC chain. Since the ROSC chain contains different combinational logic (combinational logic such as and gate, or gate, not gate, etc.), each logic selects a different kind of transistor according to the different kinds of actually selected cells of the test area. The characteristics of the transistors are different, the difference is amplified by the delay generated by an odd number of ring oscillators connected in series, and the oscillation number in the period can be counted by a counter to be used for representing the delay condition of the circuit. And then can represent the circuit delay value of the region is buried to the ROSC through the SO signal of SCC Type circuit output to reflect the electrical characteristic difference of circuit. Therefore, each SCC Type circuit sends the SO signal output by the SCC Type circuit to the SCC control circuit, and the SCC control circuit logically judges whether the chip has the difference of electrical characteristics or not.
Optionally, the SCC Type circuit further includes a continuous wave counter; the method further comprises the steps of: the continuous wave counter converts square waves output by the plurality of ROSC chains into serial SO signals.
The SCC Type circuit comprises a plurality of ROSC chains, each ROSC chain has an output result, and the delay values of different logic units on each ROSC chain can cause the difference of SO signals output by the ROSC chains; and one chip may include a plurality of SCC Type circuits. Therefore, the SCC controller captures square waves output by a plurality of ROSCs through the continuous wave counter and converts the square waves into serial SO signals, and the SCC controller can conveniently detect the chip through the output SO signals of the SCC Type circuit.
S320, the SCC control circuit calculates circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values.
In the embodiment of the application, the delay values of different logic units on the ROSC chain can cause the difference of SO signals output by the SCC Type, and the SCC control circuit can calculate the circuit delay value corresponding to the SO value by carrying out data conversion on the received SO signals SO as to represent the circuit delay value of the ROSC embedded region, thereby reflecting the electrical characteristic difference of the circuit.
Optionally, the SCC control circuit calculates circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values, including: the SCC control circuit obtains sampling clock cycles of the SCC Type circuits to obtain a plurality of sampling clock cycles; the SCC control circuit inputs the sampling clock periods into a first formula respectively to calculate to obtain the circuit delay values, wherein the first formula is expressed as: g= (n×s)/T, where N is a preset sampling period number, S is the sampling clock period, and T is a constant.
The SCC register group in the SCC control circuit can store a set sampling period number N in advance, wherein the N can be any value. The T is a single cycle of the delay line on the ROSC chain, which is a constant, specifically related to the process, and its value is the time of one square wave period on the ROSC chain in the case of the process and transistor type, used to calculate the standard (golden) value of square wave number and the process related parameters.
S330, the SCC control circuit determines whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values.
Optionally, the SCC control circuit determines whether a chip has an electrical characteristic difference according to the plurality of SO signals and the plurality of circuit delay values, including: the SCC control circuit calculates the absolute value of the difference between the ith SO signal and the corresponding circuit delay value to obtain a first difference value; if the first difference value is greater than a preset value, the SCC control circuit determines that the first SCC Type circuit has an electrical characteristic difference, and the first SCC Type circuit is the SCC Type circuit corresponding to the ith SO signal; and if the first difference value is smaller than or equal to the preset value, the SCC control circuit determines that the first SCC Type circuit has no electrical characteristic difference.
Specifically, the SCC controller may select any one SO signal from among a plurality of SO signals to calculate. A test value (circuit delay value), i.e., the number of square waves formed after the ROSC has passed through the sampling time, is calculated by the formula, and is a standard value. By comparing the circuit delay value obtained in actual test with a standard value, whether the tested chip has electrical property difference can be judged. Specifically, if the difference between the circuit delay value obtained in actual test and the standard value is greater than or equal to a preset value, the chip is considered to have the electrical characteristic difference; if the difference between the circuit delay value obtained in the actual test and the standard value is smaller than a preset value, the chip is considered to have no electrical property difference. The preset value may be preset or set according to actual requirements, which is not limited in the embodiment of the present application.
Optionally, the SCC control circuit is disposed in a power domain that can be powered down.
In the embodiment of the application, an SCC controller in an SCC control circuit performs data interaction with the outside through an SCC bus interface, and interaction with a SCCtype circuit is realized through SCCTYPEINTERFACE. The SCC control circuit is arranged in a normally open power domain at present, so that the power consumption loss is larger, therefore, the SCC control circuit is integrally arranged in the power domain with the power failure of a chip, the SCC control circuit can be controlled to be turned on only when an ATE test is carried out, the logic and the functional logic of the SCC control circuit are not affected mutually when the SCC control circuit works normally, and the SCC control circuit can be turned off along with a system, so that the power consumption of the SCC control circuit in actual working is reduced, and the influence on the overall power consumption of the system is minimized.
It can be seen that the application provides a method for detecting chip variability, which is applied to a chip variability detection system, wherein the chip variability detection system comprises a plurality of SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; the SCC Type circuits input the output SO signals to the SCC control circuit; the SCC control circuit calculates circuit delay values of a plurality of SCC Type circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether the chip has electrical characteristic differences according to the SO signals and the circuit delay values. According to the application, different types of transistors are used for mixing and lapping to form the base SCCtype, SO that the occupied area of the ROSC on the vehicle-standard chip with smaller overall size can be remarkably reduced, meanwhile, the difference of the electrical characteristics of the chip is reflected by the SO signal output by the SCC Type circuit, the coverage rate of the test is ensured, and the requirement of the vehicle-standard with higher stability requirement on the chip yield is met.
The foregoing description of the embodiments of the present application has been presented primarily in terms of a method-side implementation. It will be appreciated that the network device, in order to implement the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a detection apparatus according to an embodiment of the present application, where the detection apparatus includes: one or more processors, one or more memories, one or more communication interfaces, and one or more programs; the one or more programs are stored in the memory and configured to be executed by the one or more processors.
The program includes instructions for performing the steps of: inputting the output SO signal into the SCC control circuit; calculating circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values; and determining whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values.
All relevant contents of each scenario related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.
It should be appreciated that the memory described above may include read only memory and random access memory and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store information of the device type.
In an embodiment of the present application, the processor of the above apparatus may be a central processing unit (Central Processing Unit, CPU), which may also be other general purpose processors, digital Signal Processors (DSP), application Specific Integrated Circuits (ASIC), field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should be understood that references to "at least one" in embodiments of the present application mean one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software elements in the processor for execution. The software elements may be located in a random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor executes instructions in the memory to perform the steps of the method described above in conjunction with its hardware. To avoid repetition, a detailed description is not provided herein.
The embodiment of the present application also provides a computer storage medium storing a computer program for electronic data exchange, where the computer program causes a computer to execute some or all of the steps of any one of the methods described in the above method embodiments.
Embodiments of the present application also provide a computer program product comprising instructions which, when run on an electronic device, cause the electronic device to perform part or all of the steps of any of the methods described in the method embodiments above.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and the division of elements, such as those described above, is merely a logical function division, and may be implemented in other manners, such as multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present application.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied essentially or partly in the form of a software product or all or part of the technical solution, which is stored in a memory, and includes several instructions for causing a computer device (which may be a personal computer, a server, or TRP, etc.) to perform all or part of the steps of the method of the embodiments of the present application. And the aforementioned memory includes: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, ROM, RAM, magnetic or optical disk, etc.
The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (9)
1. The method for detecting the chip variability is characterized by being applied to a chip variability detection system, wherein the chip variability detection system comprises a plurality of silicon chip classification and calibration SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types;
The method comprises the following steps:
The SCC Type circuits input the output SO signals to the SCC control circuit;
the SCC control circuit obtains circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit determines whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values;
Wherein the SCC control circuit determines whether a chip has an electrical characteristic difference according to the plurality of SO signals and the plurality of circuit delay values, comprising:
the SCC control circuit calculates the absolute value of the difference between the ith SO signal and the corresponding circuit delay value to obtain a first difference value;
if the first difference value is greater than a preset value, the SCC control circuit determines that the first SCC Type circuit has an electrical characteristic difference, and the first SCC Type circuit is the SCC Type circuit corresponding to the ith SO signal;
And if the first difference value is smaller than or equal to the preset value, the SCC control circuit determines that the first SCC Type circuit has no electrical characteristic difference.
2. The method of claim 1, wherein the SCC control circuit obtains circuit delay values for the plurality of SCC Type circuits to obtain a plurality of circuit delay values, comprising:
The SCC control circuit obtains sampling clock cycles of the SCC Type circuits to obtain a plurality of sampling clock cycles;
The SCC control circuit inputs the sampling clock periods into a first formula respectively to calculate to obtain the circuit delay values, wherein the first formula is expressed as: g= (n×s)/T, where N is a preset sampling period number, S is the sampling clock period, and T is a constant.
3. The method of claim 1 or 2, wherein the SCC control circuit is provided in a power domain that can be powered down.
4. The method of claim 1, wherein the SCC Type circuit further comprises a ripple counter;
The method further comprises the steps of: the continuous wave counter converts square waves output by the plurality of ROSC chains into serial SO signals.
5. The system is characterized by comprising a plurality of SCC Type circuits and an SCC control circuit, wherein each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; wherein,
The SCC Type circuits are used for inputting the output SO signals into the SCC control circuit;
the SCC control circuit is used for acquiring the circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit is further used for determining whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values;
wherein, in determining whether there is a difference in electrical characteristics of the chip according to the plurality of SO signals and the plurality of circuit delay values, the SCC control circuit is specifically configured to:
calculating the absolute value of the difference between the ith SO signal and the corresponding circuit delay value to obtain a first difference value;
if the first difference value is larger than a preset value, determining that an electrical characteristic difference exists in a first SCC Type circuit, wherein the first SCC Type circuit is the SCC Type circuit corresponding to the ith SO signal;
And if the first difference value is smaller than or equal to the preset value, determining that the first SCC Type circuit has no electrical characteristic difference.
6. The system of claim 5, wherein in calculating the circuit delay values of the plurality of SCC Type circuits to obtain the plurality of circuit delay values, the SCC control circuit is specifically configured to:
acquiring sampling clock cycles of the SCC Type circuits to obtain a plurality of sampling clock cycles;
Respectively inputting the plurality of sampling clock periods into a first formula to calculate to obtain the plurality of circuit delay values, wherein the first formula is expressed as: g= (n×s)/T, where N is a preset sampling period number, S is the sampling clock period, and T is a constant.
7. The system of claim 5 or 6, wherein the SCC control circuitry is disposed in a power domain that is powered down.
8. A detection device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-4.
9. A computer readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the method according to any one of claims 1-4.
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