CN113965705B - CMOS pixel addressing module and method - Google Patents
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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Abstract
The embodiment of the application discloses a CMOS pixel addressing module and a method, wherein the CMOS pixel addressing module is connected with a CMOS pixel array structure; the CMOS pixel array structure includes: a plurality of CMOS pixel array blocks; the CMOS pixel addressing module includes: the system comprises an address control module and a plurality of row address decoders which are all connected with the address control module; the address control module is connected with each CMOS pixel array block; each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder. By the scheme of the embodiment, direct block addressing is realized, addressing speed is improved, and overall yield and reliability are improved.
Description
Technical Field
The embodiment of the application relates to a photodiode detector design technology, in particular to a CMOS pixel addressing module and a CMOS pixel addressing method.
Background
The current flat panel detector has reached wafer level and can be tiled on three sides, with more than 90% of its entire flat panel area being CMOS (complementary metal oxide semiconductor) pixel array. The main working modes of the product are a full-frame mode and an ROI (Region of Interest region of interest) mode. The ROI mode requires addressing and readout of the charge of a designated detector region. The prior art addressing technique uses a conventional shift register chain scheme as shown in fig. 1.
In fig. 1, CLK is a clock terminal, D is a register data terminal, row_sel is a shift register chain output terminal, and RST is a CMOS pixel reset signal responsible for gating a CMOS pixel at a specified address. For example, to gate a CMOS pixel controlled by ROW_SEL [2], a high level 1 needs to be sequentially shifted from the D terminal through ROW_SEL [0], ROW_SEL [1] to ROW_SEL [2].
In the existing ROI addressing technology, the addressed shift register chain penetrates through the whole CMOS pixel array, when the area of the flat panel detector is large and the CMOS pixel array is very large in scale, if the CMOS pixel far from the distance D is to be addressed, the address needs to be sequentially shifted through the whole shift register chain to reach. This design suffers from one of the following significant drawbacks and disadvantages:
1. addressing is complex and takes time.
Each addressing requires moving the address throughout the shift register chain, especially for reading far-end CMOS pixel signals.
2. The reliability is poor.
The shift register chain is an entity in which any stage fails and the entire register chain is inoperable. In addition, for wafer level chips, the area is large, the probability of defects increases, and the failure rate of the shift register chain increases.
Disclosure of Invention
The embodiment of the application provides a CMOS pixel addressing module and a CMOS pixel addressing method, which can realize direct addressing in blocks, improve the addressing speed and improve the overall yield and reliability.
The embodiment of the application provides a CMOS pixel addressing module which is connected with a complementary metal oxide semiconductor CMOS pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks; ;
The CMOS pixel array structure may include: a plurality of CMOS pixel array blocks arranged in a longitudinal direction; each CMOS pixel array block comprises a plurality of CMOS pixels arranged according to a preset rule;
The CMOS pixel addressing module may include: an address control module and a plurality of row address decoders connected to the address control module;
the address control module is connected with each CMOS pixel array block;
each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder.
In an exemplary embodiment of the application, all CMOS pixel array blocks in the CMOS pixel array structure are identical;
the addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and the addresses of the CMOS pixels in each column are sequentially increased.
In an exemplary embodiment of the application, all row address decoders in the CMOS pixel addressing module are the same;
each row address decoder is connected with the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row selection signal line,
The number of the row selection signal lines in the block is the same as that of the CMOS pixel array block.
In an exemplary embodiment of the present application, each of the row address decoders is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row reset signal line,
The number of the row reset signal lines in the block is the same as that of the CMOS pixel array block.
In an exemplary embodiment of the present application, the address control module is connected to each CMOS pixel array block through a preset block selection signal line.
In an exemplary embodiment of the present application, each CMOS pixel array block corresponds to one routing area; the wiring types and the wiring modes of the wiring areas corresponding to all the CMOS pixel array blocks are the same.
The embodiment of the application also provides a CMOS pixel addressing method, which can comprise the following steps of:
generating, by an address control module of the CMOS pixel addressing module, a block selection signal for selecting a CMOS pixel array block to enable the selected CMOS pixel array block by the block selection signal;
Generating an intra-block row selection signal for selecting a row in a CMOS pixel array block by the address control module, and transmitting the intra-block row selection signal to a row address decoder of the CMOS pixel addressing module;
the intra-block row select signal is decoded by the row address decoder to address a target CMOS pixel.
In an exemplary embodiment of the present application, the row address decoder transmitted to the CMOS pixel addressing module may include:
And all row address decoders sent to the CMOS pixel addressing module or row address decoders corresponding to the selected CMOS pixel array blocks.
In an exemplary embodiment of the present application, the method may further include:
And when the address control module receives a reset instruction, generating an intra-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the intra-block row reset signal to a corresponding row address decoder.
In an exemplary embodiment of the present application, the method may further include:
And decoding the intra-block row reset signal through the row address decoder, and resetting the target CMOS pixel.
Compared with the related art, the CMOS pixel addressing module is connected with the CMOS pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks; the CMOS pixel addressing module includes: the system comprises an address control module and a plurality of row address decoders which are all connected with the address control module; the address control module is connected with each CMOS pixel array block; each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder. By the scheme of the embodiment, direct block addressing is realized, addressing speed is improved, and overall yield and reliability are improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.
FIG. 1 is a diagram of a related art method for addressing by using a conventional shift register chain;
FIG. 2 is a block diagram of a CMOS pixel addressing module according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a CMOS pixel addressing module according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a flat panel detector according to an embodiment of the present application;
fig. 5 is a flowchart of a CMOS pixel addressing method according to an embodiment of the present application.
Detailed Description
The present application has been described in terms of several embodiments, but the description is illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present application may also be combined with any conventional features or elements to form a unique inventive arrangement as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. It is therefore to be understood that any of the features shown and/or discussed in the present application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
The embodiment of the application provides a CMOS pixel addressing module, which is a wafer-level three-sided spliced CMOS pixel detector rapid addressing module, as shown in figure 2, wherein a complementary metal oxide semiconductor CMOS pixel addressing module 2 is connected with a CMOS pixel array structure 1; the CMOS pixel array structure 1 includes a plurality of CMOS pixel array blocks 11;
The CMOS pixel array structure 1 includes: a plurality of CMOS pixel array blocks 11 arranged in a longitudinal direction; each CMOS pixel array block 11 includes a plurality of CMOS pixels arranged according to a preset rule;
The CMOS pixel addressing module 2 includes: an address control module 21 and a plurality of row address decoders 22 each connected to the address control module 21;
the address control module 21 is connected with each CMOS pixel array block 11;
each CMOS pixel array block 11 corresponds to one row address decoder 22, and is connected to the corresponding row address decoder 22.
In an exemplary embodiment of the present application, as shown in fig. 3, for example, a CMOS pixel array block arranged in a longitudinal direction may include m, where m is a positive integer, for example: block 1CMOS Pixel Array, block 2CMOS Pixel Array, block 3CMOS Pixel Array, … …, block m CMOS Pixel Array.
In an exemplary embodiment of the present application, each Block CMOS pixel Array is a CMOS pixel Array Block of the same structural scale.
In an exemplary embodiment of the present application, a plurality of CMOS pixels included in each CMOS pixel array block are arranged in a rectangular or positive direction;
the addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and the addresses of the CMOS pixels in each column are sequentially increased.
In an exemplary embodiment of the present application, when each CMOS pixel array block includes a plurality of columns of CMOS pixels, for example, i columns of CMOS pixels, i being a positive integer, i columns of CMOS pixel addresses in the vertical direction within each CMOS pixel array block are sequentially 1 to i.
In an exemplary embodiment of the present application, when more CMOS pixels need to be extended within the CMOS pixel array structure, the more CMOS pixel array blocks may be extended in the longitudinal direction on the basis of the plurality of CMOS pixel array blocks.
In an exemplary embodiment of the present application, as shown in fig. 2, a CMOS pixel addressing module 2 may be used to address the CMOS pixel array structure 1; the CMOS pixel addressing module may include: an address control module (21) ADDRESS CTRL and a plurality of Row address decoders (22) Row decoders each connected to the address control module (21) ADDRESS CTRL;
The address control module (21) ADDRESS CTRL is connected with each CMOS pixel array block in the CMOS pixel array structure 1;
each CMOS pixel array block in the CMOS pixel array structure corresponds to one row address decoder respectively and is connected with the corresponding row address decoder.
In an exemplary embodiment of the present application, the address control module (21) ADDRESS CTRL may be connected to a plurality of Row address decoders (22) Row decoders through a Row address Bus (Row Addr Bus).
In an exemplary embodiment of the application, each CMOS pixel array block corresponds to the same Row address Decoder (22) Row Decoder.
In an exemplary embodiment of the present application, as shown in fig. 3, each Row address Decoder (22) Row Decoder is respectively connected to the CMOS pixels of each Row of the corresponding CMOS pixel array block.
In an exemplary embodiment of the present application, the each Row address Decoder is connected to the CMOS pixels of each Row of the corresponding CMOS pixel array block through a preset intra-block Row selection signal line,
The number of the row selection signal lines in the block is the same as that of the CMOS pixel array block.
In an exemplary embodiment of the present application, each of the row address decoders is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row reset signal line,
The number of the row reset signal lines in the block is the same as that of the CMOS pixel array block.
In an exemplary embodiment of the present application, as shown in fig. 3, the address control module ADDRESS CTRL is connected to each CMOS pixel array block through a preset block selection signal line.
In an exemplary embodiment of the present application, the address control module ADDRESS CTRL may be configured to generate a block selection signal BlockEn for selecting a CMOS pixel array block, and transmit the block selection signal to the selected CMOS pixel array block; and generating an intra-block Row selection signal RowSel for selecting a Row within the CMOS pixel array block, and transmitting the intra-block Row selection signal RowSel to the corresponding Row address Decoder.
In an exemplary embodiment of the present application, the Block 1CMOS pixel Array, block 2CMOS pixel Array, block 3CMOS pixel Array, … …, block m CMOS pixel Array may correspond to the corresponding Block select signals BlockEn [0], blockEn [1], blockEn [2], … …, blockEn [ m-1], respectively.
In an exemplary embodiment of the present application, the selected CMOS pixel array block is directly enabled by the BlockEn signal corresponding to the CMOS pixel array block without going through the shift register chain.
In an exemplary embodiment of the present application, the intra-block Row select signal RowSel generated by the address control module ADDRESS CTRL is simultaneously connected to all Row address decoders Row, and the intra-block Row select signal RowSel is decoded by the Row address decoders Row Decoder to gate the target CMOS pixel.
In an exemplary embodiment of the present application, only the Row address Decoder Row Decoder corresponding to the selected CMOS pixel array block decodes the target CMOS pixel in the ROI mode.
In an exemplary embodiment of the present application, each row address (e.g., rowAddr1, rowAddr, … …, rowAddr n) in each CMOS pixel array block may correspond to a respective intra-block row select signal RowSel (e.g., rowsel_1, rowsel_2, … …, rowsel_n).
In an exemplary embodiment of the present application, the address control module ADDRESS CTRL may be further configured to generate an intra-block Row reset signal RowRst for resetting each Row of CMOS pixels within the CMOS pixel array block, and send the intra-block Row reset signal to the corresponding Row address Decoder Row Decoder.
In an exemplary embodiment of the present application, the intra-block Row reset signal RowRst generated by the address control module ADDRESS CTRL is connected to all Row address decoders Row at the same time, and the intra-block Row reset signal RowRst is decoded by the Row address decoders Row to reset the target CMOS pixels.
In an exemplary embodiment of the present application, in the ROI mode, only the Row address Decoder Row Decoder corresponding to the selected CMOS pixel array block decodes the target CMOS pixel addressed thereto and resets the target CMOS pixel.
In an exemplary embodiment of the present application, each row address (e.g., rowAddr, rowAddr2, … …, rowAddr n) in each CMOS pixel array block may correspond to a respective intra-block row reset signal RowRst (e.g., rowRst _1, rowRst _2, … …, rowRst _n).
In an exemplary embodiment of the present application, as shown in fig. 3, each CMOS pixel array block corresponds to one routing region P (e.g., P1, P2, P3); all the block selection signal lines are arranged in the wiring area P;
in each routing region P, the routing modes of the block selection signal lines other than the block selection signal line of the CMOS pixel array block corresponding to the routing region are the same.
In an exemplary embodiment of the present application, the Block 1CMOS pixel Array, the Block 2CMOS pixel Array, the Block 3CMOS pixel Array, … …, the Block m CMOS pixel Array may correspond to the corresponding routing regions P1, P2, P3, … …, pm, respectively.
In an exemplary embodiment of the present application, the layout trace of BlockEn may take a 'Z' trace within each trace region, and the 'Z' trace layout of BlockEn within P1, P2, P3, … …, pm may be identical.
In the exemplary embodiment of the application, when the area of the flat panel detector needs to be expanded and more CMOS pixel array blocks need to be expanded, a plurality of blocks shown as L1, L2 and L3 can be longitudinally spliced in an infinite manner theoretically without re-customizing layout wiring and CMOS pixel arrays.
In an exemplary embodiment of the present application, the above-described CMOS pixel addressing module may be applied to the flat panel detector 3, as shown in fig. 4.
In the exemplary embodiment of the present application, the Pixel Array is the detector portion of the embodiment of the present application, that is, the CMOS Pixel Array structure 1, and the analog-to-digital converter ADC is responsible for converting signals of CMOS pixels into digital signals and sequentially outputs the digital signals through an Algorithm & Timing Control module and a FIFO (first in first out) module and then through a LVDS DRIVER (low voltage differential signal driving) port. Global Timing Control (global time control) module is connected with VERTICAL SCANNING Block (vertical scanning Block) module, and generates all time sequence control signals, and VERTICAL SCANNING Block module is the CMOS pixel addressing module 2 and is responsible for addressing and resetting the CMOS pixels. The other end of Global Timing Control modules is connected to an I2C Port (inter integrated circuit bus interface). The flat panel detector 3 may also be provided with a temperature Sensor (Temp Sensor). The flat panel detector 3 may also include a Voltage & Current Generator (Voltage current generator) that provides power to the Pixel Array and ADC.
The embodiment of the application also provides a CMOS pixel addressing method, which is based on the CMOS pixel addressing module, as shown in fig. 5, and can comprise the steps of S101-S103:
S101, generating a block selection signal for selecting a CMOS pixel array block by an address control module of the CMOS pixel addressing module so as to enable the selected CMOS pixel array block through the block selection signal;
S102, generating an intra-block row selection signal for selecting rows in a CMOS pixel array block by the address control module, and sending the intra-block row selection signal to a row address decoder of the CMOS pixel addressing module;
S103, decoding the intra-block row selection signals through the row address decoder, and addressing the intra-block row selection signals to the target CMOS pixels.
In an exemplary embodiment of the present application, the row address decoder transmitted to the CMOS pixel addressing module may include:
And all row address decoders sent to the CMOS pixel addressing module or row address decoders corresponding to the selected CMOS pixel array blocks.
In an exemplary embodiment of the present application, the method may further include:
And when the address control module receives a reset instruction, generating an intra-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the intra-block row reset signal to a corresponding row address decoder.
In an exemplary embodiment of the present application, the method may further include:
And decoding the intra-block row reset signal through the row address decoder, and resetting the target CMOS pixel.
In the exemplary embodiment of the present application, any embodiment of the foregoing system embodiment is applicable to the method embodiment, and will not be described herein in detail.
In an exemplary embodiment of the present application, the embodiment of the present application has at least the following advantages:
1. The traditional shift register chain addressing mode is abandoned, and the target CMOS pixels can be directly and rapidly addressed by adopting a blocking direct addressing mode, so that the addressing speed is improved.
2. In terms of circuit structure and physical design, each CMOS pixel array block is addressed independently by adopting a block addressing mode, and even if a certain decoder fails, the work of other blocks cannot be blocked, so that the overall yield and reliability are improved.
3. In the aspect of layout design, the block enable signal layout of each CMOS pixel array is completely consistent, a novel product is designed, the flat panel area can be directly reused when the flat panel area is expanded, repeated labor is avoided, and the design time is shortened.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (8)
1. The CMOS pixel addressing module is characterized by being connected with a Complementary Metal Oxide Semiconductor (CMOS) pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks;
The CMOS pixel addressing module includes: an address control module and a plurality of row address decoders connected to the address control module; the address control module is used for generating a block selection signal for selecting the CMOS pixel array block and generating a row selection signal for selecting the CMOS pixel array block; the block selection signal enables the selected CMOS pixel array block, and the row selection signal is sent to the row address decoder corresponding to the selected CMOS pixel array block;
the address control module is connected with each CMOS pixel array block through a preset block selection signal line, and each CMOS pixel array block is addressed independently by adopting a block direct addressing mode;
each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder.
2. The CMOS pixel addressing module according to claim 1, wherein all CMOS pixel array blocks are identical;
the addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and the addresses of the CMOS pixels in each column are sequentially increased.
3. The CMOS pixel addressing module according to claim 1 or 2, wherein all row address decoders in the CMOS pixel addressing module are identical;
Each row address decoder is connected with the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row selection signal line;
the number of the row selection signal lines in the block is the same as that of the CMOS pixel array block.
4. The CMOS pixel addressing module according to claim 1 or 2, wherein each of the row address decoders is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block via a predetermined intra-block row reset signal line,
The number of the row reset signal lines in the block is the same as that of the CMOS pixel array block.
5. The CMOS pixel addressing module according to claim 1 or 2, wherein each CMOS pixel array block corresponds to one routing area; the wiring types and the wiring modes of the wiring areas corresponding to all the CMOS pixel array blocks are the same.
6. A CMOS pixel addressing method, based on a CMOS pixel addressing module according to any one of claims 1-5, the method comprising:
generating, by an address control module of the CMOS pixel addressing module, a block selection signal for selecting a CMOS pixel array block to enable the selected CMOS pixel array block by the block selection signal;
Generating, by the address control module, an intra-block row select signal for selecting a row within a block of the CMOS pixel array, and transmitting to a row address decoder of the CMOS pixel addressing module, comprising: transmitting the pixel array block to a row address decoder corresponding to the selected CMOS pixel array block;
the intra-block row select signal is decoded by the row address decoder to address a target CMOS pixel.
7. The CMOS pixel addressing method according to claim 6, further comprising:
And when the address control module receives a reset instruction, generating an intra-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the intra-block row reset signal to a corresponding row address decoder.
8. The CMOS pixel addressing method according to claim 7, further comprising:
And decoding the intra-block row reset signal through the row address decoder, and resetting the target CMOS pixel.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101455070A (en) * | 2006-05-22 | 2009-06-10 | 汤姆森特许公司 | Image sensor and method for reading out pixels of the image sensor |
| CN106657829A (en) * | 2016-12-09 | 2017-05-10 | 南京邮电大学 | Reading circuit and reading method for high-density single-photon avalanche diode (SPAD) array-level analog signals |
| CN216122646U (en) * | 2021-11-04 | 2022-03-22 | 地太科特电子制造(北京)有限公司 | CMOS pixel addressing module and flat panel detector |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6466265B1 (en) * | 1998-06-22 | 2002-10-15 | Eastman Kodak Company | Parallel output architectures for CMOS active pixel sensors |
| CN101558649A (en) * | 2006-09-26 | 2009-10-14 | 皇家飞利浦电子股份有限公司 | Data processing with a plurality of memory banks |
| GB201117319D0 (en) * | 2011-10-06 | 2011-11-16 | Isis Innovation | Active pixel image sensor |
| CN103139495B (en) * | 2013-02-27 | 2014-03-12 | 天津大学 | Asynchronous pixel array with arbitration time error correction function |
| WO2015157341A1 (en) * | 2014-04-07 | 2015-10-15 | Samsung Electronics Co., Ltd. | High resolution, high frame rate, low power image sensor |
| CN108713315B (en) * | 2016-03-16 | 2020-02-21 | 株式会社理光 | Photoelectric conversion device, image reading device, and image forming apparatus |
| CN106454148B (en) * | 2016-11-15 | 2019-07-12 | 天津大学 | Piecemeal separate exposures CMOS image sensor pixel structure and its control method |
| KR102040368B1 (en) * | 2017-07-20 | 2019-11-04 | 이영종 | Hyper spectral image sensor and 3D Scanner using it |
| CN107483841A (en) * | 2017-08-11 | 2017-12-15 | 天津大学 | Programmable Pixel Array Based on Multi-Target Effective Recognition |
| CN108766332B (en) * | 2018-04-17 | 2021-09-10 | 南京昀光科技有限公司 | Scalable silicon-based microdisplay driver circuit |
-
2021
- 2021-11-04 CN CN202111301742.4A patent/CN113965705B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101455070A (en) * | 2006-05-22 | 2009-06-10 | 汤姆森特许公司 | Image sensor and method for reading out pixels of the image sensor |
| CN106657829A (en) * | 2016-12-09 | 2017-05-10 | 南京邮电大学 | Reading circuit and reading method for high-density single-photon avalanche diode (SPAD) array-level analog signals |
| CN216122646U (en) * | 2021-11-04 | 2022-03-22 | 地太科特电子制造(北京)有限公司 | CMOS pixel addressing module and flat panel detector |
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| CN113965705A (en) | 2022-01-21 |
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