CN113964196B - Depletion type power semiconductor structure, series structure and processing technology - Google Patents

Abstract

The present invention relates to the technical field of semiconductor devices, specifically a depletion-type power semiconductor structure, a series structure and a processing technology, wherein the depletion-type power semiconductor structure has a cell structure including: a BJT rear-stage structure and a JFET front-stage structure; a JFET The front-stage structure is set in the BJT post-stage structure, that is, the MOSFET structure of the input stage of the IGBT device is replaced by the JFET front-stage structure. This depletion-type power semiconductor structure does not need to grow gate oxide film, so it solves the actual manufacturability problem caused by the setting of various gate oxide layers, and it is easy to connect in series, which can achieve higher yield rate and lower production cost. low effect.

Description

A depletion mode power semiconductor structure, series structure and processing technology

technical field

The invention relates to the technical field of semiconductor devices, in particular to a depletion-type power semiconductor structure, a series structure and a processing technology.

Background technique

As solid-state semiconductor power devices gradually penetrate into the application scenarios of traditional gas switches and mechanical switches, the industry has put forward higher requirements for the switching capacity (voltage, current) of solid-state semiconductor power devices. At the same time, the increase in switching frequency plays a key role in reducing the weight of the product. Therefore, the demand for high-voltage, high-current, and high-frequency solid-state semiconductor power devices is imminent.

Among solid-state semiconductor power devices, unipolar devices have good switching performance and are easy to drive. Among them, depletion-type devices have the advantage of being easy to be applied in series; bipolar devices have good current flow capacity, and the chip can be effectively reduced under the same current. area, reducing device cost. The organic combination of the two originated from the IGBT device invented by Baliga in 1982, which inherited the output characteristics of bipolar devices and the input characteristics of unipolar devices. However, affected by materials, silicon-based IGBTs can only switch at a voltage level of 8.4kV, and commercial devices often do not exceed 6.5kV, which is far from meeting the needs of ultra-high voltage applications such as UHVDC transmission. Ultra-high pressure applications present great challenges. The study found that the third-generation semiconductor materials, such as silicon carbide, have a wider band gap, which can effectively increase the working voltage and meet the needs of ultra-high voltage applications such as UHV DC transmission. Therefore, it is of great significance to study silicon carbide IGBT devices . However, limited by SiO2/SiC interface defects and productivity, there are currently few units that can produce reliable gate oxide layers for silicon carbide planar MOSFETs, not to mention gate oxide layers for trench MOSFETs with higher current densities and more complex manufacturing processes. layers, so SiC IGBTs based on MOSFET input stages still have practical manufacturability issues.

In addition, because in the high-voltage field (6.5kV and above), due to the influence of low doping in the drift region, the parasitic structure of solid-state semiconductor power devices is prone to secondary breakdown during high-current switching, which is limited by the secondary breakdown of the parasitic structure , It is difficult for solid-state semiconductor power devices to meet the requirements of ultra-high voltage applications such as UHV DC transmission. Therefore, compared with the use of immature high-voltage single devices, connecting multiple relatively low-voltage devices in series can obtain higher reliability, higher yield, and lower production costs, but the series application is complicated, and the existing technology has no absorption circuit, it is difficult to achieve high-efficiency large-scale series connection.

Contents of the invention

One of the objectives of the present invention is to provide a depletion-mode power semiconductor structure that can be easily connected in series without growing a gate oxide film.

Basic solution 1 provided by the present invention: a depletion-type power semiconductor structure, the cell structure of which includes: a BJT rear-stage structure and a JFET front-stage structure;

The JFET front-stage structure is set in the BJT post-stage structure, that is, the JFET front-stage structure is used to replace the MOSFET structure of the input stage of the IGBT device.

Beneficial effects of basic scheme 1: The good characteristics of IGBT devices enable it to meet the needs of ultra-high voltage applications such as UHV DC transmission. Therefore, although limited by SiO2/SiC interface defects and productivity, researchers generally tend to study how to manufacture Reliable gate oxide layer for silicon carbide planar MOSFET to solve the actual manufacturability problem of silicon carbide IGBT based on MOSFET input stage. Gate oxide layer for planar MOSFET or gate oxide layer for trench MOSFET. In this structure, the JFET front-stage structure is used to replace the MOSFET structure of the input stage of the IGBT device. The JFET front-stage structure is set in the BJT post-stage structure, which does not affect the original IGBT The function of the device, and after replacing the MOSFET structure, the JFET front-end structure does not need to set the gate oxide layer for the silicon carbide planar MOSFET or the gate oxide layer for the trench MOSFET, so it solves the problem caused by the setting of various gate oxide layers. There are practical manufacturability issues.

Moreover, the JFET front-end structure can realize large-scale, self-balancing, and simple series cascading through the Super Cascode topology. In this structure, the JFET front-end structure replaces the MOSFET structure of the input stage of the IGBT device, and this structure can be large-scale through the JFET front-end structure. Scale, self-balancing, and simple series cascading, so as to solve the problem that the existing series application is complicated and it is difficult to achieve high-efficiency large-scale series connection.

To sum up, the depletion-mode power semiconductor structure that does not need to grow gate oxide film and is easy to be connected in series can achieve higher yield and lower production cost.

Further, the BJT post-stage structure is sequentially arranged from top to bottom: a metal collector, a collector region of the first conductivity type, a drift/base region of the second conductivity type, a buffer zone or field of the second conductivity type a stop zone, an emitter zone of the first conductivity type, a metal emitter;

The JFET front-stage structure is arranged in order from top to bottom: a gate structure, a source region of the second conductivity type, a channel region of the second conductivity type, and a drift/drain region of the second conductivity type;

The JFET front-end structure is arranged in the top layer of the drift/base region of the second conductivity type, and the drift/drain region of the second conductivity type is in contact with the drift/base region of the second conductivity type;

The collector region of the first conductivity type is arranged on both sides of the top layer of the drift/base region of the second conductivity type, and is in contact with the source region of the second conductivity type and the channel region of the second conductivity type;

The gate structure is arranged in the channel region of the second conductivity type, and is arranged in sequence from top to bottom: an insulator, a metal gate, and a gate region of the first conductivity type; wherein the metal gate is arranged on the gate region of the first conductivity type. In the electrode region; the gate region of the first conductivity type is arranged in the channel region of the second conductivity type, and the source region of the second conductivity type is arranged on both sides of the top layer of the channel region of the second conductivity type, and the first conductivity type type of gate region in contact.

Beneficial effects: when a negative voltage is applied between the metal gate and the metal emitter, the gate region of the first conductivity type in the JFET front-end structure is subjected to negative pressure to form a depletion layer, and the depletion layer increases with the absolute value of the negative voltage High and wide, when the absolute value of the negative pressure reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the channel region of the second conductivity type, and completely occupies the channel region of the second conductivity type. At this time, The current between the source region of the second conductivity type and the drift/drain region of the second conductivity type in the pre-JFET structure approaches zero. Because the drift/drain region of the second conductivity type of the JFET front-stage structure is in contact with the drift/base region of the second conductivity type of the BJT subsequent stage structure, the source region of the second conductivity type of the JFET front-stage structure and the BJT The collector region of the first conductivity type of the subsequent stage structure is in contact, so when the JFET front stage structure is not turned on, the drift/base region of the second conductivity type of the BJT subsequent stage structure is connected to the collector region of the first conductivity type It is not conducting, so the BJT post-stage structure is turned off, the current flowing through the entire device is close to zero, and the device is in an off state.

No voltage or positive voltage is applied between the metal gate and the metal emitter, and the gate region of the first conductivity type in the JFET pre-structure does not form a depletion layer, so the channel region of the second conductivity type allows current to flow However, at this time, the drift/base region of the second conductivity type and the collector region of the first conductivity type of the BJT rear-stage structure are connected through the JFET front-stage structure, and the hFE (common emitter current amplification factor) of the BJT rear-stage structure ) under magnification, there is current flowing from the emitter region of the first conductivity type to the collector region of the first conductivity type of the BJT subsequent stage structure, that is, there is current flowing from the emitter to the collector of the BJT subsequent stage structure, and the device is in conduction state.

As the applied current increases, that is, the positive voltage between the metal gate and the metal emitter increases, the carrier concentration of the drift/base region of the second conductivity type of the BJT post-stage structure increases, and the JFET pre-stage structure The carrier concentration of the drift/drain region of the second conductivity type also increases at the same time, thereby reducing the on-resistance of the BJT rear-stage structure and the JFET front-stage structure. At the same time, as the applied current increases, the voltage of the collector region of the first conductivity type of the BJT rear-stage structure rises, thereby injecting carriers into the channel region of the second conductivity type of the JFET front-stage structure, thereby further reducing The on-resistance of the JFET front-end structure. Both effects work together to reduce the variation of the device's turn-on voltage drop with current.

Further, the metal gate and the metal collector are separated by an insulator.

Beneficial effect: the metal grid and the metal collector are separated by the insulator, preventing their contact and affecting the use of the entire device.

Further, the collector region of the first conductivity type is a heavily doped collector region of the first conductivity type;

The emitter region of the first conductivity type is a heavily doped emitter region of the first conductivity type;

The source region of the second conductivity type is a heavily doped source region of the second conductivity type;

The drift/base region of the second conductivity type is a lightly doped drift/base region of the second conductivity type;

The drift/drain region of the second conductivity type is a lightly doped drift/drain region of the second conductivity type.

Beneficial effects: The main purpose of heavy doping is to thin the potential barrier when metal is drawn out and realize ohmic contact. Heavy doping of the emitter region can increase the efficiency of injecting electrons from the emitter to the base region, thereby achieving high current gain ; The drift/drain region is lightly doped to reduce electric field peaks and hot electron effects.

Further, the first conductivity type is P-type, and the second conductivity type is N-type.

Beneficial effects: the first conductivity type is P-type, and the second conductivity type is N-type, thereby realizing the structure of a depletion-type power semiconductor structure.

The second object of the present invention is to provide a depletion-mode power semiconductor series structure formed by series-connecting depletion-mode power devices including a depletion-mode power semiconductor structure that does not need to grow a gate oxide film and is easy to be connected in series, so as to improve voltage tolerance , Depletion-type power device yield and reliability, reducing production costs.

The second basic solution provided by the present invention: a series structure of depletion-type power semiconductors, including: multi-level depletion-type power devices containing depletion-type power semiconductor structures and low-voltage MOSFETs connected in series, and the emission of each stage of depletion-type power devices The pole is connected to the collector of the next-stage depletion-mode power device, and the emitter of the final-stage depletion-mode power device is connected to the drain of the low-voltage MOSFET.

Beneficial effects of the second basic scheme: in the series structure of depletion-mode power semiconductors, the collector of the first-stage depletion-mode power device is the positive stage of the series structure, the source of the MOSFET is the negative pole of the series structure, and the gate of the MOSFET is the series structure The control electrode, the entire series structure can be regarded as a voltage-controlled switching device, and the specific use is similar to that of a MOSFET. Depletion-type power devices are connected in series, which improves the voltage tolerance and reduces the dependence on single voltage in the ultra-high voltage system, thereby improving the yield of depletion-type power devices and reducing production costs. At the same time, the lower monomer voltage can suppress the parasitic BJT of the input stage of the depletion-mode power semiconductor structure, thereby improving the reliability of the depletion-mode power device.

Further, a first resistor is connected in series with the gate of each stage of depletion-mode power device, and the other end of each first resistor is connected to the gate of the next-stage depletion-mode power device through a capacitor.

Beneficial effects: the gates of each level of depletion-mode power devices are connected in series with a first resistor, synchronously adjusting the first resistors of all gates can control the overall switching speed of the series structure, thereby achieving a flexible balance between EMI and switching performance switch. At the same time, the other end of each first resistor is connected to the gate of the next-stage depletion-type power device through a capacitor, and the gate series capacitor can regulate the transient gate current, thereby fine-tuning the time sequence of the depletion-type power device switch, In this way, the zero adjustment of the time error at the moment of switching is realized. The series capacitor between the gate of the depletion-mode power device and the first resistor can realize the voltage balance in the switching transient. The sum of the charged and discharged gate charge plus the charge flowing through the upper stage capacitor.

Further, a Zener diode is connected in parallel with the capacitor.

Beneficial effect: the parallel connection of the voltage stabilizing diode between the capacitors can realize the voltage balance for the long time off period.

Further, in the case of high voltage, the Zener diode adopts a PIN type diode.

Beneficial effects: under high voltage conditions, the Zener diode adopts a PIN diode, and the avalanche characteristic of the PIN diode can realize the Zener diode, and the static turn-off voltage drop of each stage of the series structure is approximately equal to the current bias current of the Zener diode. The lower voltage regulation value.

Further, the second resistor is connected in series with the Zener diode.

Beneficial effects: the series connection of the second resistor with the Zener diode can reduce the peak current and average current of the Zener diode during the dynamic and static conversion process and when the series structure has an avalanche breakdown, thereby improving the reliability of the series structure.

Further, the capacitor adopts the parasitic capacitance of a PIN diode.

Intentional effect: Because the gate charge of the JFET structure is highly correlated with the interstage voltage, in order to ensure that the series structure can always maintain the interstage voltage balance within a wide operating voltage range, the capacitance should simulate the non-linear capacitance of the gate of the JFET structure characteristics, so the capacitance is realized by the parasitic capacitance of the PIN diode, which can meet the above requirements.

Further, the gate of the first-stage depletion-type power device is connected to the collector of the first-stage depletion-type power device through a resistor bias network, and the other end of the first resistor connected in series with the gate of the last-stage depletion-type power device is connected to Source of the Low Voltage MOSFET.

Beneficial effects: the other end of the first resistor connected in series with the gate of the final depletion power device to the source of the MOSFET can ensure that when the MOSFET is turned off, the current flowing through the series structure will pull up the drain voltage of the MOSFET, that is, the final The source voltage of the first-stage depletion-type power device is pulled up, because the gate of the last-stage depletion-type power device is connected to the source of the MOSFET through the first resistor, and the voltage from the gate to the emitter of the last-stage depletion-type power device is negative voltage, so the input stage of its JFET structure pinches off, thus shutting down. Similarly, the shutdown of the last-stage depletion-mode power device triggers the shutdown of the upper-stage depletion-mode power device until the first-stage depletion-mode power device is turned off. When the MOSFET is turned on, the process is vice versa, that is, the first-stage depletion-mode power device starts to turn off, and turns off step by step. Combining the above-mentioned dynamic balance using capacitors and static balance using Zener diodes, the series structure can realize self-driving and self-balancing, so its characteristics are similar to ultra-high voltage MOSFETs from the outside, and can achieve ultra-high voltage that is difficult to achieve with a single device .

The third object of the present invention is to provide a processing technology for a depletion-type power semiconductor structure that does not need to grow a gate oxide film and is easy to be connected in series, so as to produce a power semiconductor structure that does not need to grow a gate oxide film and is easy to connect in series.

The present invention provides a third basic solution: a depletion-type power semiconductor structure processing technology, including the following content:

Provide semiconductor substrates;

epitaxially growing a drift layer of the second conductivity type and a channel layer of the second conductivity type in sequence on the semiconductor substrate;

Beneficial effects of the basic scheme three: Compared with the traditional semiconductor structure processing technology, the depletion power semiconductor structure produced by this process is processed by implanting impurities, etching grooves and depositing metal in the channel layer to form a JFET front stage The structure replaces the MOSFET structure of the input stage of the IGBT device, and does not affect the function of the original IGBT device, and after replacing the MOSFET structure, the JFET front-end structure does not need to be equipped with a gate oxide layer for a silicon carbide planar MOSFET or a gate for a trench MOSFET Oxide layer, so it solves the actual manufacturability problems caused by the setting of various gate oxide layers, reduces processing difficulty, improves the yield rate, and reduces production costs;

And the JFET pre-stage structure can realize large-scale, self-balancing, and simple series cascading through the Super Cascode topology. In the semiconductor structure produced by this process, the JFET pre-stage structure replaces the MOSFET structure of the input stage of the IGBT device, and the JFET pre-stage structure can be used. Large-scale, self-balancing, and simple series cascading of the structure can solve the problem that the existing series applications are complex and difficult to achieve high-efficiency large-scale series connection.

Further, the impurity implantation, groove etching and metal deposition are performed on the channel layer to form a JFET front-end structure, including:

Selectively implanting impurities of the first conductivity type and impurities of the second conductivity type in the channel layer to form a collector region of the first conductivity type of the BJT rear-end structure and a source region of the second conductivity type of the JFET front-end structure;

A trench is etched in the channel layer, and impurities of the first conductivity type are implanted or diffused into the trench to form a trench region (channel region) of the JFET pre-structure, and metal is deposited to complete the gate structure.

Beneficial effects: according to the above-mentioned processing technology, the JFET pre-stage structure can be processed, and when a negative voltage is added, the groove area of the JFET pre-stage structure is subjected to negative pressure to form a depletion layer, and the depletion layer increases with the absolute value of the negative voltage And widen, when the absolute value of the negative pressure reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the channel layer of the second conductivity type, and completely occupies the channel region of the second conductivity type, so that the front stage of the JFET The structure is not conductive, so the subsequent structure of the BJT is not conductive, so the subsequent structure of the BJT is turned off, the current flowing through the entire device approaches zero, and the device is in an off state. No voltage or positive voltage is applied, the trench region of the JFET front-stage structure will not form a depletion layer, and the device is in a conduction state; and as the applied current increases, the conduction of the BJT rear-stage structure and the JFET front-stage structure resistance will decrease.

Further, the subsequent processing includes:

Complete the intercellular interconnection of the top gate and the collector and form the external electrode through the metal layer and the insulating layer;

The wafer is thinned and backside metallized to form a finished wafer.

Beneficial effects: Thinning the wafer can reduce the thickness of the drift region, thereby reducing the conduction voltage drop and internal resistance, and the thinning is beneficial to improve the heat dissipation capability.

Further, the semiconductor substrate includes: a semiconductor substrate of the first conductivity type or a semiconductor substrate of the second conductivity type;

If the semiconductor substrate is a semiconductor substrate of the first conductivity type, before the drift layer of the second conductivity type and the channel layer of the second conductivity type are epitaxially grown on the semiconductor substrate in sequence, the second conductivity type is also epitaxially grown on the semiconductor substrate. field stop/buffer layer of two conductivity types;

If the semiconductor substrate is a semiconductor substrate of the second conductivity type, after the wafer is thinned, impurities of the first conductivity type are injected into the back surface to form an emitter region of the first conductivity type.

Beneficial effect: it is compatible with two kinds of semiconductor substrates, so that the technical adaptability is wider.

Further, the first conductivity type is P-type, the second conductivity type is N-type, and the doping concentration of each layer and each region is not all the same.

Beneficial effects: the doping concentration of each layer and each region is not the same, and the doping concentration of each layer and each region is adjusted according to actual needs, so as to realize the functions of each layer and each region.

Description of drawings

1 is a schematic diagram of a cell structure of an embodiment of a depletion-mode power semiconductor structure in the present invention;

2 is a schematic diagram of a depletion-mode power semiconductor series structure in an embodiment of the depletion-mode power semiconductor series structure of the present invention;

FIG. 3 is a schematic flowchart of an embodiment of a depletion-mode power semiconductor structure processing process according to the present invention.

Detailed ways

The following is further described in detail through specific implementation methods:

The reference signs in the drawings of the description include: metal collector 1, collector region 2 of the first conductivity type, drift/base region 3 of the second conductivity type, buffer zone or field stop region 4 of the second conductivity type, Emitter region 5 of the first conductivity type, metal emitter 6, insulator 7, metal gate 8, gate region 9 of the first conductivity type, source region 10 of the second conductivity type, channel of the second conductivity type Region 11, drift/drain region 12 of the second conductivity type.

Embodiment one

This embodiment is basically shown in Figure 1: a depletion-type power semiconductor structure, the structure is a semiconductor device, the device is made up of cells arranged in parallel, and its cell structure includes: BJT post-stage structure and JFET previous structure;

The JFET front-stage structure is set in the BJT post-stage structure, that is, the JFET front-stage structure is used to replace the MOSFET structure of the input stage of the IGBT device. Compared with the MOSFET structure in the IGBT device in the prior art, the gate oxide layer for the silicon carbide planar MOSFET or the gate oxide layer for the trench MOSFET is required, and the JFET front-end structure replaces the MOSFET structure of the input stage of the IGBT device without affecting the original IGBT device. function, and after replacing the MOSFET structure, the JFET front-end structure does not need to set the gate oxide layer for the silicon carbide planar MOSFET or the gate oxide layer for the trench MOSFET, so it solves the practical problems caused by the setting of various gate oxide layers. manufacturability issues. And the JFET pre-stage structure can realize large-scale, self-balancing, and simple series cascading through the Super Cascode topology. It is complicated and difficult to achieve high-efficiency large-scale series connection. There is no need to grow a gate oxide film, and the depletion-type power semiconductor structure that is easy to connect in series can achieve higher yield and lower production cost.

The BJT post-stage structure is arranged in order from top to bottom: metal collector 1, collector region 2 of the first conductivity type, drift/base region 3 of the second conductivity type, buffer zone or field stop of the second conductivity type Region 4, the emitter region 5 of the first conductivity type, and the metal emitter 6; the emitter region 5 of the first conductivity type is also its ohmic contact region;

The JFET front-end structure is arranged in order from top to bottom: a gate structure, a source region 10 of the second conductivity type, a channel region 11 of the second conductivity type, and a drift/drain region 12 of the second conductivity type; The source region 10 of the second conductivity type is also its ohmic contact region; the JFET pre-structure is arranged in the drift/base region 3 top layer of the second conductivity type, and the drift/drain region 12 of the second conductivity type is connected to the second conductivity type The drift/base region 3 of the second conductivity type is in contact with each other. In this embodiment, the drift/drain region 12 of the second conductivity type is shared with the drift/base region 3 of the second conductivity type; the collector region 2 of the first conductivity type is set On both sides of the top layer of the drift/base region 3 of the second conductivity type, it is in contact with the source region 10 of the second conductivity type and the channel region 11 of the second conductivity type;

The gate structure is arranged in the channel region 11 of the second conductivity type, and is arranged in sequence from top to bottom: an insulator 7, a metal gate 8, and a gate region 9 of the first conductivity type; wherein the metal gate 8 is arranged in the second In the gate region 9 of a conductivity type; the gate region 9 of the first conductivity type is arranged in the channel region 11 of the second conductivity type, and the source region 10 of the second conductivity type is arranged in the channel of the second conductivity type Both sides of the top layer of the region 11 are in contact with the gate region 9 of the first conductivity type, and the metal gate 8 and the metal collector 1 are separated by an insulator 7 .

The above-mentioned first conductive semiconductor is a P-type semiconductor, and the second conductive semiconductor is an N-type semiconductor; the doping concentration of each region is not the same, specifically:

The collector region 2 of the first conductivity type is a heavily doped collector region 2 of the first conductivity type;

The emitter region 5 of the first conductivity type is a heavily doped emitter region 5 of the first conductivity type;

The source region 10 of the second conductivity type is a heavily doped source region 10 of the second conductivity type;

The drift/base region 3 of the second conductivity type is a lightly doped drift/base region 3 of the second conductivity type;

The drift/drain region 12 of the second conductivity type is a lightly doped drift/drain region 12 of the second conductivity type.

In this embodiment, the doping concentration of doping is on the order of 10 ¹⁷ to 10 ¹⁸ , the doping concentration of heavy doping is on the order of 10 ¹⁸ to 10 ¹⁹ , and the doping concentration of light doping is on the order of 10 ¹⁵ to 10 ¹⁶ ; and the gate region 9 of the first conductivity type is a gate P/P+ region, and the doping concentration is on the order of 10 ¹⁷ -10 ¹⁹ .

Working principle: A negative voltage is applied between the metal gate 8 and the metal emitter 6, and the P/P+ region of the gate in the JFET front-end structure is subjected to negative pressure to form a depletion layer, and the depletion layer increases with the absolute value of the negative voltage High and wide, when the absolute value of the negative pressure reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the N-region of the channel, and completely occupies the N-region of the channel. At this time, the source of the JFET front-end structure The current between the N+ region and the drift/drain N- region approaches zero, that is, the current between the source and drain of the JFET pre-stage structure approaches zero, and almost no current flows. Because the drift/drain N-region of the JFET front-stage structure is in contact with the drift/base N-region of the BJT post-stage structure, the source N+ region of the JFET pre-stage structure is in contact with the collector P+ region of the BJT post-stage structure , that is, the drain of the JFET front-stage structure is connected to the base of the BJT post-stage structure, and the source of the JFET front-stage structure is connected to the collector of the BJT post-stage structure, so when the JFET front-stage structure is not turned on, the BJT The drift/base N-region to the collector P+ region of the subsequent structure is not conductive, that is, the base to the collector of the BJT subsequent structure is not conductive, so the BJT subsequent structure is turned off, and the current flowing through the entire device tends to Near zero, the device is in the off state.

No voltage or positive voltage is applied between the metal gate 8 and the metal emitter 6. In the JFET pre-stage structure, the P region of the gate does not form a depletion layer, so the N region of the channel allows current to flow. At this time, the BJT The drift/base N-region and the collector P+ region of the subsequent stage structure are connected through the JFET pre-stage structure, that is, the base and collector of the BJT post-stage structure are connected through the JFET pre-stage structure, after the hFE amplification of the BJT post-stage structure Next, there is current flowing from the emitter P+ area to the collector P+ area of the BJT post-stage structure, that is, there is current flowing from the emitter to the collector of the BJT post-stage structure, and the device is in the on state.

As the applied current increases, that is, the positive voltage between the metal gate 8 and the metal emitter 6 increases, the drift of the BJT rear-stage structure/carrier concentration in the base N-region increases, and the JFET front-stage structure The carrier concentration of the drift/drain N-region also increases simultaneously, thereby reducing the on-resistance of the BJT rear-stage structure and the JFET front-stage structure. At the same time, as the applied current increases, the voltage of the collector P+ region of the BJT rear-stage structure rises, thereby injecting carriers into the channel N region of the JFET front-stage structure, thereby further reducing the on-resistance of the JFET front-stage structure . Both effects work together to reduce the variation of the device's turn-on voltage drop with current.

Embodiment two

This embodiment is basically as shown in accompanying drawing 2: a kind of depletion mode power semiconductor series structure, comprises the depletion mode power device of above-mentioned depletion mode power semiconductor structure by multistage (J1, J2, J3, J4, J4 in Fig. 2 J5 and J6) and a low-voltage MOSFET (M1 in Figure 2) are connected in series, the emitter of each depletion-mode power device is connected to the collector of the next-level depletion-mode power device, and the final depletion-mode power device (Figure 2 The emitter of J6) is connected to the drain of the low-voltage MOSFET. In Figure 2, DRAIN represents the positive electrode of the overall device after series connection, GATE represents the control electrode of the overall device after series connection, and SOURCE represents the negative electrode of the overall device after series connection. In this embodiment, six stages are connected in series.

A first resistor (RG1, RG2, RG3, RG4, RG5, and RG6 in Figure 2) is connected in series with the gate of each stage of depletion-mode power device, and the other end of each first resistor is connected to the next-stage depletion-mode power device The gate of the gate is connected through a capacitor (CG1, CG2, CG3, CG4, and CG5 in Figure 2), and a Zener diode (DA1, DA2, DA3, DA4, and DA5 in Figure 2) is connected in parallel to the capacitor; each Zener diode is connected in series A second resistor (RA1, RA2, RA3, RA4, and RA5 in Figure 2), the second resistor in series with the Zener diode can reduce the peak current and average current, thereby improving the reliability of the series structure. Because the gate charge of the JFET structure is highly correlated with the interstage voltage, in order to ensure that the series structure can always maintain the interstage voltage balance within a wide operating voltage range, the capacitor should simulate the non-linear capacitance characteristics of the gate of the JFET structure, so The capacitance is realized by the parasitic capacitance of a PIN diode, which can meet the above requirements. In the case of high voltage, the Zener diode adopts a PIN diode. The cut-off voltage drop is approximately equal to the voltage regulation value of the Zener diode under the current bias current.

The gates of each depletion-mode power device mentioned above are connected in series with a first resistor, synchronously adjusting the first resistors of all gates can control the overall switching speed of the series structure, so as to achieve flexible switching between EMI and switching performance . At the same time, the other end of each first resistor is connected to the gate of the next-stage depletion-type power device through a capacitor, and the gate series capacitor can regulate the transient gate current, thereby fine-tuning the time sequence of the depletion-type power device switch, In this way, the zero adjustment of the time error at the moment of switching is realized. The series capacitor between the gate of the depletion-mode power device and the first resistor can realize the voltage balance in the switching transient. The sum of the charged and discharged gate charge plus the charge flowing through the upper stage capacitor. Parallel Zener diodes between capacitors can achieve voltage balancing for long off periods.

The gate of the first-stage depletion-mode power device (J1 in Figure 2) is connected to the collector of the first-stage depletion-mode power device through a resistor bias network (RB1 in Figure 2), and each stage of depletion-mode power device The gate is connected to the gate of the next-stage depletion-type device through the first gate resistor, the Zener diode and the second gate resistor, and the gate of the final-stage depletion-type power device is connected to the low-voltage MOSFET through the first gate resistor. source. The other end of the first resistor connected in series with the gate of the final-stage depletion-type power device is connected to the source of the MOSFET to ensure that when the MOSFET is turned off, the current flowing through the series structure will pull up the drain voltage of the MOSFET, that is, the final stage is depleted The source voltage of the depletion-type power device is pulled up, because the gate of the final-stage depletion-mode power device is connected to the source of the MOSFET through the first resistor, and the voltage from the gate to the emitter of the final-stage depletion-mode power device is negative, so The input stage of its JFET structure pinches off, thus shutting down. Similarly, the shutdown of the last-stage depletion-mode power device triggers the shutdown of the upper-stage depletion-mode power device until the first-stage depletion-mode power device is turned off. When the MOSFET is turned on, the process is vice versa, that is, the first-stage depletion-mode power device starts to turn off, and turns off step by step. Combining the above-mentioned dynamic balance using capacitors and static balance using Zener diodes, the series structure can realize self-driving and self-balancing, so its characteristics are similar to ultra-high voltage MOSFETs from the outside, and can achieve ultra-high voltage that is difficult to achieve with a single device .

In the series structure of depletion-mode power semiconductors, the collector of the first-stage depletion-mode power device is the positive stage of the series structure, the source of the MOSFET is the negative pole of the series structure, and the gate of the MOSFET is the control electrode of the series structure. The entire series structure It can be regarded as a voltage-controlled switching device, and its specific use is similar to that of a MOSFET. Depletion-type power devices are connected in series, which improves the voltage tolerance and reduces the dependence on single voltage in the ultra-high voltage system, thereby improving the yield of depletion-type power devices and reducing production costs. At the same time, the lower monomer voltage can suppress the parasitic BJT of the input stage of the depletion-mode power semiconductor structure, thereby improving the reliability of the depletion-mode power device.

Embodiment Three

This embodiment is basically shown in Figure 3: a depletion-type power semiconductor structure processing technology, including the following:

A semiconductor substrate is provided; the semiconductor substrate includes: a semiconductor substrate of a first conductivity type or a semiconductor substrate of a second conductivity type;

A drift layer of the second conductivity type and a channel layer of the second conductivity type are epitaxially grown sequentially on the semiconductor substrate; Before the drift layer of the conductivity type and the channel layer of the second conductivity type, a field stop/buffer layer of the second conductivity type is epitaxially grown on the semiconductor substrate;

Implant impurities, etch trenches and deposit metal in the channel layer to form the JFET front-end structure; specifically:

Selective implantation of impurities of the first conductivity type and impurities of the second conductivity type in the channel layer to form the collector region 2 of the first conductivity type of the BJT rear-end structure and the source region of the second conductivity type of the JFET front-end structure 10;

Etch the trench in the channel layer, and inject or diffuse impurities of the first conductivity type into the trench to form the trench region of the JFET pre-stage structure, that is, the gate region 9 of the first conductivity type, and deposit metal to complete the gate polar structure;

Carry out follow-up processing, that is, the back-end process; specifically: complete the inter-cell interconnection of the top gate and collector through the metal layer and insulating layer, and form external electrodes; in addition, the follow-up process also includes general processing technology, such as: using field The ring realizes the termination of the single device, the use of selective PI coating to realize the top layer protection, the metal plate setting and wiring of the top layer gate and source of the single device, etc.; the field ring is used to realize the termination of the single device, including: in the cell array Impurities of the first conductivity type and/or impurities of the second conductivity type are implanted alternately in the periphery to achieve the termination of a single device; the general processing technology is an existing technology, and its selection and implementation are determined by the implementer, and will not be described in this embodiment .

Thinning and metallizing the back of the wafer to form a finished wafer; if the semiconductor substrate is a semiconductor substrate of the second conductivity type, after the wafer is thinned, impurities of the first conductivity type are injected into the back, An emitter region 5 of the first conductivity type is formed. The depletion-mode power semiconductor structure is implemented on a wafer, that is, the above-mentioned processing techniques are all performed on the wafer.

In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and the doping concentration of each layer and each region is not the same, specifically: the drift layer of the second conductivity type is an N-type drift layer; the second The channel layer of the conductivity type is an N-type channel layer; the field stop/buffer layer of the second conductivity type is an N-type field stop/buffer layer; impurities of the first conductivity type and the second conductivity type are selectively injected into the channel layer The impurities are P+ type impurities and N+ type impurities, which form the collector P+ region of the BJT rear-stage structure and the source N+ region of the JFET front-stage structure; the impurities of the first conductivity type implanted or diffused into the trench are P/P+ type Impurities: Impurities of the first conductivity type are implanted into the back surface as P+ type impurities to form the P+ region of the emitter. The semiconductor structure produced by this processing technology is the depletion-type power semiconductor structure described in Embodiment 1. The effect and working principle of the depletion-type power semiconductor structure will not be repeated in this embodiment.

What is described above is only an embodiment of the present invention, and the common knowledge such as the specific structure and characteristics known in the scheme is not described too much here, and those of ordinary skill in the art know all the common knowledge in the technical field to which the invention belongs before the filing date or the priority date Technical knowledge, being able to know all the existing technologies in this field, and having the ability to apply conventional experimental methods before this date, those of ordinary skill in the art can improve and implement this plan based on their own abilities under the inspiration given by this application, Some typical known structures or known methods should not be obstacles for those of ordinary skill in the art to implement the present application. It should be pointed out that for those skilled in the art, under the premise of not departing from the structure of the present invention, several modifications and improvements can also be made, and these should also be regarded as the protection scope of the present invention, and these will not affect the implementation of the present invention. Effects and utility of patents. The scope of protection required by this application shall be based on the content of the claims, and the specific implementation methods and other records in the specification may be used to interpret the content of the claims.

Claims (15)

1. A depletion mode power semiconductor structure, characterized in that: its cell structure comprises: a BJT rear stage structure and a JFET front stage structure; The JFET front-stage structure is set in the BJT post-stage structure, and the JFET front-stage structure is used to replace the MOSFET structure of the input stage of the IGBT device; The BJT post-stage structure is arranged in order from top to bottom: a metal collector, a collector region of the first conductivity type, a first drift region of the second conductivity type, that is, a base region, a buffer zone of the second conductivity type or a field stop region, an emitter region of the first conductivity type, a metal emitter; The JFET front-stage structure is arranged sequentially from top to bottom: the source region of the second conductivity type, the channel region of the second conductivity type, the second drift region of the second conductivity type, that is, the drain region; the JFET front-stage A gate structure is also arranged in the structure; The JFET front-stage structure is arranged in the top layer of the first drift region of the second conductivity type, and the second drift region of the second conductivity type is in contact with the first drift region of the second conductivity type; The collector region of the first conductivity type is arranged on both sides of the top layer of the first drift region of the second conductivity type, and is in contact with the source region of the second conductivity type and the channel region of the second conductivity type; The gate structure is arranged in the channel region of the second conductivity type, and is arranged in sequence from top to bottom: an insulator, a metal gate, and a gate region of the first conductivity type; wherein the metal gate is arranged on the gate region of the first conductivity type. In the electrode region; the gate region of the first conductivity type is arranged in the channel region of the second conductivity type, and the source region of the second conductivity type is arranged on both sides of the top layer of the channel region of the second conductivity type, and the first conductivity type The gate region of the type is in contact; the metal gate and the metal collector are separated by an insulator; A negative voltage is applied between the metal gate and the metal emitter, and the gate region of the first conductivity type in the JFET pre-structure is subjected to negative pressure to form a depletion layer, and the depletion layer changes with the increase of the absolute value of the negative voltage Wide, when the absolute value of the negative voltage reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the channel region of the second conductivity type. 2. The depletion-mode power semiconductor structure according to claim 1, characterized in that: the collector region of the first conductivity type is a heavily doped collector region of the first conductivity type; The emitter region of the first conductivity type is a heavily doped emitter region of the first conductivity type; The source region of the second conductivity type is a heavily doped source region of the second conductivity type; The first drift region of the second conductivity type is a lightly doped first drift region of the second conductivity type; The second drift region of the second conductivity type is a lightly doped second drift region of the second conductivity type. 3. The depletion-mode power semiconductor structure according to claim 1, wherein the first conductivity type is P-type, and the second conductivity type is N-type. 4. A depletion-type power semiconductor series structure, characterized in that: the depletion-type power device comprising the depletion-type power semiconductor structure described in any one of claims 1-3 is adopted, comprising: multi-stages comprising all The depletion-mode power device and low-voltage MOSFET are connected in series, the emitter of each depletion-mode power device is connected to the collector of the next-stage depletion-mode power device, and the emitter of the last-stage depletion-mode power device is connected to the drain of the low-voltage MOSFET pole. 5. The depletion-mode power semiconductor series structure according to claim 4, characterized in that: the gate of each stage of depletion-mode power devices is connected in series with a first resistor, and the other end of each first resistor is connected to the next stage The gates of depletion-mode power devices are connected through capacitors. 6. The series structure of depletion-mode power semiconductors according to claim 5, characterized in that a voltage regulator diode is connected in parallel to the capacitor. 7. The series structure of depletion-mode power semiconductors according to claim 6, characterized in that: under high voltage conditions, the Zener diodes are PIN diodes. 8 . The depletion-mode power semiconductor series structure according to claim 6 , wherein the second resistor is connected in series with the Zener diode. 9 . The depletion-mode power semiconductor series structure according to claim 5 , wherein the capacitor is a parasitic capacitance of a PIN diode. 10. The depletion-mode power semiconductor series structure according to claim 6, characterized in that: the gate of the first-stage depletion-mode power device is connected to the collector of the first-stage depletion-mode power device through a resistor bias network, The other end of the first resistor connected in series with the gate of the final depletion power device is connected to the source of the low-voltage MOSFET. 11. A process for processing a depletion-mode power semiconductor structure, for processing the depletion-mode power semiconductor structure according to any one of claims 1-3, comprising the following content: Provide semiconductor substrates; epitaxially growing a drift layer of the second conductivity type and a channel layer of the second conductivity type in sequence on the semiconductor substrate; It is characterized in that it also includes: Implant impurities, etch trenches and deposit metal in the channel layer to form the JFET front-end structure; For subsequent processing. 12. The depletion-type power semiconductor structure processing technology according to claim 11, characterized in that: said implanting impurities, etching trenches and depositing metal in the channel layer to form a JFET front-stage structure, comprising: Selectively implanting impurities of the first conductivity type and impurities of the second conductivity type in the channel layer to form a collector region of the first conductivity type of the BJT rear-end structure and a source region of the second conductivity type of the JFET front-end structure; A trench is etched in the channel layer, and impurities of the first conductivity type are implanted or diffused into the trench to form a trench region of a JFET front-stage structure, and metal is deposited to complete a gate structure. 13. The depletion-mode power semiconductor structure processing technology according to claim 11, characterized in that: the subsequent processing includes: Complete the intercellular interconnection of the top gate and the collector and form the external electrode through the metal layer and the insulating layer; The wafer is thinned and backside metallized to form a finished wafer. 14. The depletion-mode power semiconductor structure processing process according to claim 11, characterized in that: the semiconductor substrate comprises: a semiconductor substrate of the first conductivity type or a semiconductor substrate of the second conductivity type; If the semiconductor substrate is a semiconductor substrate of the first conductivity type, before the drift layer of the second conductivity type and the channel layer of the second conductivity type are epitaxially grown on the semiconductor substrate in sequence, the second conductivity type is also epitaxially grown on the semiconductor substrate. Field stop zone or buffer layer of two conductivity types; If the semiconductor substrate is a semiconductor substrate of the second conductivity type, after the wafer is thinned, impurities of the first conductivity type are injected into the back surface to form an emitter region of the first conductivity type. 15. The depletion-type power semiconductor structure processing technology according to claim 12, characterized in that: the first conductivity type is P-type, the second conductivity type is N-type, and the doping concentration of each layer and each region is not all the same .

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