CN113949225B - Signal processing device of sine and cosine encoder - Google Patents
Signal processing device of sine and cosine encoder Download PDFInfo
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Abstract
The application discloses signal processing device of sine and cosine encoder includes: the differential offset module is used for carrying out differential offset processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain an analog signal; the voltage tracking module is used for carrying out voltage tracking on the analog signal to obtain an analog tracking signal; the comparison module is used for converting the analog signal into a digital signal; the digital filtering module is used for filtering out a jitter signal and a spike interference signal in the digital signal to obtain a digital filtering signal; the switching power supply noise filtering module is used for processing noise interference generated by the switching power supply to obtain a target signal with noise filtered; and the signal processing module is used for determining the running speed of the target permanent magnet synchronous motor according to the analog tracking signal and the target signal. The device can reduce the cost and expense when processing the output signals of the sine and cosine encoder, and can improve the accuracy when determining the running speed of the permanent magnet synchronous motor.
Description
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a signal processing apparatus for a sine-cosine encoder.
Background
The sine and cosine encoder is usually used for position detection of a permanent magnet synchronous motor closed-loop control system, so that the precision of an output signal of the sine and cosine encoder directly influences the control precision of the permanent magnet synchronous motor closed-loop control system. In practical applications, the phase a and phase B signals output by the sine and cosine encoders are generally used for detecting the operating speed of the permanent magnet synchronous motor. Each phase signal output by the sine and cosine encoder consists of two paths of signals, namely, the A phase signal consists of an A + signal and an A-signal, and the B phase signal consists of a B + signal and a B-signal. If the A +, A-, B + and B-signals are interfered, the speed measurement of the permanent magnet synchronous motor is adversely affected.
In the prior art, when the operating speed of the permanent magnet synchronous motor is determined by using the phase a and phase B signals of a sine and cosine encoder, a differential bias circuit is first required to convert the phase a and phase B analog signals of-0.5V- +0.5V output by the sine and cosine encoder into a target analog signal of 0-3.3V that can be received by an MCU (Micro Controller Unit), a comparison circuit is used to convert the target analog signal into a target digital signal, and then the target digital signal and the target analog signal of 0-3.3V are input to a processing chip, and a software processing algorithm stored in the processing chip is used to calculate the operating speed of the permanent magnet synchronous motor.
Because the analog signal and the digital signal are interfered by factors such as a switching power supply, a control switch and the like, the processing chip cannot accurately acquire the running speed of the permanent magnet synchronous motor. Moreover, the development of the software processing algorithm requires high cost investment, which also greatly increases the signal processing cost of the sine and cosine encoder. At present, no effective solution exists for the technical problem.
Disclosure of Invention
In view of the above, the present invention provides a signal processing apparatus for a sine-cosine encoder, so as to reduce the cost overhead when processing the output signal of the sine-cosine encoder, and improve the accuracy when determining the operating speed of the permanent magnet synchronous motor. The specific scheme is as follows:
a signal processing apparatus of a sine-cosine encoder, comprising:
the differential offset module is used for carrying out differential offset processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a target analog signal;
the voltage tracking module is used for carrying out voltage tracking on the target analog signal to obtain a target analog tracking signal;
the comparison module is used for converting the target analog signal into a target digital signal;
the digital filtering module is used for filtering out a jitter signal and a spike interference signal in the target digital signal to obtain a target digital filtering signal;
the switching power supply noise filtering module is used for processing noise interference generated when the switching power supply is switched on or switched off to obtain a target signal for filtering the noise;
and the signal processing module is used for determining the running speed of the target permanent magnet synchronous motor according to the target analog tracking signal and the target signal.
Preferably, the differential bias module includes:
and the two differential bias circuits with the same structure are used for respectively carrying out differential bias processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a first analog signal and a second analog signal.
Preferably, the differential bias circuit includes: eleven resistors, thirteen capacitors and a first differential amplifier;
wherein, the first end of the first resistor is respectively connected with the first end of the second capacitor, the first end of the third capacitor and the first end of the fourth resistor, the second end of the second capacitor is grounded, the second end of the first resistor is respectively connected with the first end of the second resistor and the first end of the third resistor, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the second resistor is respectively connected with the second end of the third capacitor, the first end of the fourth capacitor and the first end of the sixth resistor, the second end of the fourth capacitor is grounded, the second end of the second capacitor is respectively connected with the first end of the fifth capacitor and the first end of the eighth capacitor, the second end of the fifth capacitor is respectively connected with the second end of the fourth resistor, the first end of the fifth resistor and the first end of the sixth capacitor, a second end of the sixth capacitor is connected to the second end of the sixth resistor, the first end of the seventh capacitor and the first end of the seventh resistor, a second end of the seventh capacitor is grounded, a second end of the eighth capacitor is connected to the first end of the eighth resistor, the first end of the ninth capacitor and the second end of the fifth resistor, a second end of the ninth capacitor is connected to the second end of the seventh resistor and the first end of the tenth capacitor, a second end of the tenth capacitor is grounded, a second end of the eighth resistor is connected to the first end of the ninth resistor, a second end of the ninth resistor is used for receiving a voltage of 1.5V, a second end of the ninth resistor is connected to the first end of the twelfth capacitor and the first end of the eleventh capacitor, a second end of the twelfth capacitor is grounded, and a second end of the eleventh capacitor is connected to the first end of the eighth resistor and the positive input end of the first differential amplifier, respectively The negative input end of the first differential amplifier is respectively connected with the second end of the seventh resistor, the first end of the tenth resistor and the first end of the thirteenth capacitor, and the second end of the tenth resistor is connected with the first end of the eleventh resistor;
correspondingly, a first end of the first resistor and a second end of the second resistor are respectively used for receiving a positive-phase signal and a negative-phase signal in the a-phase signal, and a common end formed by an output end of the first differential amplifier, a second end of the eleventh resistor, and a second end of the thirteenth capacitor is used for outputting the first analog signal.
Preferably, the voltage tracking module includes:
and the two voltage tracking circuits with the same arrangement structure are used for respectively carrying out voltage tracking on the first analog signal and the second analog signal.
Preferably, the voltage tracking circuit includes: the circuit comprises a twelfth resistor, a thirteenth resistor, a second differential amplifier, a first inductor, a fourteenth capacitor, a fifteenth capacitor, a first diode and a second diode;
a second end of the twelfth resistor is connected to a positive input end of the second differential amplifier, a ground end of the second differential amplifier is grounded, a negative input end of the second differential amplifier is connected to an output end of the second differential amplifier, power ends of the second differential amplifier are respectively connected to a first end of the first inductor and a first end of the fourteenth capacitor, a second end of the first inductor is configured to receive a 5V voltage, a second end of the fourteenth capacitor is grounded, an output end of the second differential amplifier is connected to a first end of the thirteenth resistor, a second end of the thirteenth resistor is respectively connected to a negative electrode of the first diode, a positive electrode of the second diode and a first end of the fifteenth capacitor, a positive electrode of the first diode is grounded, a negative electrode of the second diode is configured to receive a 3Vref voltage, and a second end of the fifteenth capacitor is grounded;
correspondingly, a first end of the twelfth resistor is configured to receive the first analog signal, and a second end of the thirteenth resistor is configured to output the first analog signal.
Preferably, the comparator includes:
and the two comparison circuits are arranged in the same structure and are used for respectively converting the first analog signal and the second analog signal into a first digital signal and a second digital signal.
Preferably, the comparison circuit includes: the first resistor, the second third resistor, the second fourth resistor, the second fifth resistor, the second sixth resistor, the second capacitor, the second capacitor, the second third capacitor and the first comparator;
the first end of the second first resistor is configured to receive a 1.5V voltage, the second end of the second first resistor is connected to the first end of the second resistor, the first end of the second capacitor, the first end of the second third resistor and the positive input end of the first comparator, the second end of the second resistor is connected to the second end of the second first capacitor and grounded, the second end of the second third resistor is connected to the first end of the second fourth resistor, the output end of the first comparator and the first end of the second sixth resistor, the second end of the second fourth resistor is configured to receive a 5V voltage, the second end of the second sixth resistor is connected to the first end of the second third capacitor, the second end of the second third capacitor is grounded, the negative input end of the first comparator is connected to the first end of the second fifth resistor and the first end of the second capacitor, and the second end of the second capacitor is grounded;
correspondingly, the second end of the second fifth resistor is configured to receive the first analog signal, and the second end of the second sixth resistor is configured to output the first digital signal.
Preferably, the digital filtering module includes:
and the digital filtering circuit is used for respectively filtering the jitter signal and the spike interference signal in the first digital signal and the second digital signal to obtain a first digital filtering signal and a second digital filtering signal.
Preferably, the digital filter circuit includes: the first inverter, the second inverter, the third inverter, the fourth inverter, the first exclusive-or gate, the second exclusive-or gate, the first D trigger, the second D trigger, the third first resistor, the third second resistor, the third fourth resistor, the third fifth resistor, the third sixth resistor, the third pseudo-resistor, the third first capacitor, the third second capacitor, the third capacitor, the third fourth capacitor, the third fifth capacitor, the third sixth capacitor, the third diode, the fourth diode, the fifth diode and the sixth diode;
the input end of the first phase inverter is respectively connected with the first end of a third resistor and the first end of a third capacitor, the second end of the third capacitor is grounded, the output end of the first phase inverter is respectively connected with the first input end of the first exclusive-or gate, the first end of a third resistor and the D end of a second D trigger, the second end of the third resistor is respectively connected with the second input end of the first exclusive-or gate and the first end of the third capacitor, the second end of the third capacitor is grounded, the output end of the first exclusive-or gate is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the C end of the first D trigger, the Q end of the first D trigger is connected with the first end of the third resistor, the second end of the third resistor is respectively connected with the cathode of a third diode, the anode of a fourth diode and the first end of the third capacitor, the anode of the third resistor is grounded, and the cathode of the third diode is used for receiving the Verf 3 of the third capacitor; the input end of the third inverter is respectively connected with the first end of a third fourth resistor and the first end of a third fourth capacitor, the second end of the third fourth capacitor is grounded, the output end of the third inverter is respectively connected with the D end of the first D flip-flop, the first input end of the second exclusive-OR gate and the first end of a third fifth resistor, the second end of the third fifth resistor is respectively connected with the second input end of the second exclusive-OR gate and the first end of the third fifth capacitor, the second end of the third fifth capacitor is grounded, the output end of the second exclusive-OR gate is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the C end of the second D flip-flop, the Q end of the second D flip-flop is connected with the first end of the third sixth resistor, the second end of the third resistor is respectively connected with the cathode of the fifth diode, the anode of the sixth diode and the first end of the third sixth capacitor, the anode of the fifth diode is grounded, and the cathode of the sixth diode is used for receiving the third end of the Verf 3; the S end of the first D trigger is respectively connected with the R end of the first D trigger, the S end of the second D trigger, the R end of the second D trigger, the first end of the third resistor and the first end of the third capacitor, the second end of the third resistor is used for receiving 5V voltage, and the second end of the third capacitor is grounded;
correspondingly, the first terminal of the third first resistor is configured to receive the first digital signal, the first terminal of the third fourth resistor is configured to receive the second digital signal, the second terminal of the third resistor is configured to output the first digital filtered signal, and the second terminal of the third sixth resistor is configured to output the second digital filtered signal.
Preferably, the noise filtering module of the switching power supply includes: the first capacitor is connected with the first resistor, the second capacitor is connected with the second capacitor, and the first capacitor is connected with the second capacitor;
a second end of the fourth resistor is connected to a first end of the fourth capacitor and a first input end of the third exclusive or gate, respectively, a second end of the fourth capacitor is grounded, an output signal of the third exclusive or gate is inverted to an enable signal of the first buffer, and an output end of the first buffer is connected to an enable end of the second buffer;
correspondingly, the first end of the fourth resistor, the second input end of the third exclusive-or gate, and the input end of the second buffer are all configured to receive an original signal, the input end of the first buffer is configured to receive a driving signal output by the switching power supply, and the output end of the second buffer is configured to output the target signal.
Therefore, in the signal device provided by the invention, because the hardware circuit is used for processing the A-phase signal and the B-phase signal output by the sine and cosine encoder to determine and obtain the operating speed of the target permanent magnet synchronous motor, compared with the prior art, the setting mode provides a processing method for effectively solving the interference problem caused by factors such as a switching power supply, a control switch and the like, and meanwhile, the development cost required by using a software processing algorithm for the operating speed of the permanent magnet synchronous motor can be saved, so the cost overhead when the output signal of the sine and cosine encoder is processed can be obviously reduced through the signal processing device. In addition, the signal processing device can filter out jitter signals, peak interference signals, switching power supplies, control switches and other interference factors in A-phase signals and B-phase signals output by the sine and cosine encoder, so that the influence of the interference signals on the running speed of the permanent magnet synchronous motor can be avoided, and the precision in determining the running speed of the permanent magnet synchronous motor can be further improved through the signal processing device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural diagram of a signal processing apparatus of a sine and cosine encoder according to an embodiment of the present invention;
FIG. 2 is a block diagram of a differential bias circuit and voltage tracking module according to an embodiment of the present invention;
FIG. 3 is a block diagram of a comparison circuit according to an embodiment of the present invention;
FIG. 4 is a block diagram of a digital filter circuit according to an embodiment of the present invention;
fig. 5 is a structural diagram of a noise filtering module of a switching power supply according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an output signal of a sine-cosine encoder;
fig. 7 is a timing diagram of the noise filtering module of the switching power supply.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a structural diagram of a signal processing apparatus of a sine-cosine encoder according to an embodiment of the present invention, where the signal processing apparatus includes:
the differential offset module 11 is configured to perform differential offset processing on the a-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a target analog signal;
the voltage tracking module 12 is used for performing voltage tracking on the target analog signal to obtain a target analog tracking signal;
a comparison module 13, configured to convert the target analog signal into a target digital signal;
the digital filtering module 14 is configured to filter a jitter signal and a spike interference signal in the target digital signal to obtain a target digital filtering signal;
the switching power supply noise filtering module 15 is used for processing noise interference generated when the switching power supply is switched on or switched off to obtain a target signal with noise filtered;
and the signal processing module 16 is used for determining the running speed of the target permanent magnet synchronous motor according to the target analog tracking signal and the target signal.
In the present embodiment, a signal processing apparatus for a sine and cosine encoder is provided, by which an a-phase signal and a B-phase signal output by the sine and cosine encoder are processed, which not only can reduce the cost overhead required for processing the output signal of the sine and cosine encoder, but also can improve the accuracy in determining the operating speed of the permanent magnet synchronous motor.
Specifically, the signal processing apparatus provided in this embodiment is provided with a differential bias module 11, a voltage tracking module 12, a comparison module 13, a digital filtering module 14, a switching power supply noise filtering module 15, and a signal processing module 16. When the differential offset module 11 receives the a-phase signal and the B-phase signal output by the sine-cosine encoder, the differential offset module 11 performs differential offset processing on the a-phase signal and the B-phase signal output by the sine-cosine encoder to obtain a target analog signal, and then the voltage tracking module 12 performs voltage tracking on the target analog signal output by the differential offset module 11 to obtain a target analog tracking signal and transmits the target tracking signal to the signal processing module 16.
When the differential offset module 11 outputs the target analog signal, the comparison module 13 converts the target analog signal into a target digital signal, and the digital filtering module 14 connected to the rear end of the comparison module 13 is used to filter out the jitter signal and the spike interference signal in the target digital signal, so as to obtain a digital filtering signal. After the digital filtering module 14 filters out the jitter signal and the spike interference signal in the target digital signal, the noise filtering module 15 of the switching power supply filters out noise interference generated when the switching power supply is turned on or turned off, so as to obtain a target signal after noise is filtered out.
It is conceivable that after the hardware circuit digital filtering module 14 and the switching power supply noise filtering module 15 are used to filter out the jitter signal, the spike interference signal, and the noise interference generated when the switching power supply is turned on or off in the target digital signal, the interference of the impurity signal to the a-phase signal and the B-phase signal output by the sine-cosine encoder can be avoided, and in this case, the signal processing module 16 can accurately determine the operating speed of the target permanent magnet synchronous motor according to the target signal and the target analog signal output by the voltage tracking module 12.
Compared with the prior art, the signal processing device provided by the embodiment is completely composed of the hardware circuit, so that the investment cost required when the running speed of the permanent magnet synchronous motor is processed by using a software processing algorithm can be saved, and the cost overhead when the output signal of the sine and cosine encoder is processed can be remarkably reduced through the signal processing device.
It can be seen that, in the signal apparatus provided in this embodiment, because the hardware circuit is used to process the a-phase signal and the B-phase signal output by the sine and cosine encoder to determine the operation speed of the target permanent magnet synchronous motor, compared with the prior art, the setting method provides a processing method for effectively solving the interference problem caused by factors such as the switching power supply and the control switch, and meanwhile, the development cost required by using a software processing algorithm for the operation speed of the permanent magnet synchronous motor can be eliminated, so the cost overhead when the signal output by the sine and cosine encoder is processed can be significantly reduced by the signal processing apparatus. In addition, the signal processing device can filter out jitter signals, peak interference signals, switching power supplies, control switches and other interference factors in A-phase signals and B-phase signals output by the sine and cosine encoder, so that the influence of the interference signals on the running speed of the permanent magnet synchronous motor can be avoided, and the precision in determining the running speed of the permanent magnet synchronous motor can be further improved through the signal processing device.
Based on the foregoing embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the differential bias module 11 includes:
the two differential bias circuits with the same structure are used for respectively carrying out differential bias processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a first analog signal and a second analog signal.
It can be understood that, because the differential bias module needs to perform differential bias processing on the a-phase signal and the B-phase signal output by the sine-cosine encoder, in the present embodiment, two differential bias circuits with the same structure are provided in the differential bias module.
Namely, a differential bias circuit is used for carrying out differential bias processing on the A phase signal output by the sine and cosine encoder to obtain a first analog signal; and performing differential bias processing on the B-phase signal output by the sine and cosine encoder by using another differential bias circuit to obtain a second analog signal.
Referring to fig. 2, fig. 2 is a structural diagram of a differential bias circuit and a voltage tracking module according to an embodiment of the present invention. As a preferred embodiment, the differential bias circuit includes: eleven resistors, thirteen capacitors and a first differential amplifier;
wherein, the first end of the first resistor R1 is connected with the first end of the second capacitor C2, the first end of the third capacitor C3 and the first end of the fourth resistor R4 respectively, the second end of the second capacitor C2 is grounded, the second end of the first resistor R1 is connected with the first end of the second resistor R2 and the first end of the third resistor R3 respectively, the second end of the third resistor R3 is connected with the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the second end of the second resistor R2 is connected with the second end of the third capacitor C3, the first end of the fourth capacitor C4 and the first end of the sixth resistor R6 respectively, the second end of the fourth capacitor C4 is grounded, the second end of the second capacitor C2 is connected with the first end of the fifth capacitor C5 and the first end of the eighth capacitor C8 respectively, the second end of the fifth capacitor C5 is connected with the second end of the fourth resistor R4, the first end of the fifth capacitor R5 and the first end of the sixth capacitor C6 respectively, the second end of the sixth capacitor C6 is connected to the second end of the sixth resistor R6, the first end of the seventh capacitor C7 and the first end of the seventh resistor R7, respectively, the second end of the seventh capacitor C7 is connected to ground, the second end of the eighth capacitor C8 is connected to the first end of the eighth resistor R8, the first end of the ninth capacitor C9 and the second end of the fifth resistor R5, respectively, the second end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7 and the first end of the tenth capacitor C10, respectively, the second end of the tenth capacitor C10 is connected to ground, the second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is used for receiving a voltage of 1.5V, the second end of the ninth resistor R9 is connected to the first end of the twelfth capacitor C12 and the first end of the eleventh capacitor C11, respectively, the second end of the twelfth capacitor C12 is connected to ground, and the second end of the eleventh capacitor C11 is connected to the first end of the eighth resistor R8 and the positive input terminal of the first differential amplifier N1, a negative input end of the first differential amplifier N1 is respectively connected to a second end of the seventh resistor R7, a first end of the tenth resistor R10, and a first end of the thirteenth capacitor C13, and a second end of the tenth resistor R10 is connected to a first end of the eleventh resistor R11;
correspondingly, the first end of the first resistor R1 and the second end of the second resistor R2 are respectively configured to receive the positive-phase signal and the negative-phase signal of the a-phase signal, and a common end formed by the output end of the first differential amplifier N1, the second end of the eleventh resistor R11, and the second end of the thirteenth capacitor C13 is configured to output the first analog signal.
In the present embodiment, a specific structure of the differential bias circuit is provided. In the circuit diagram shown in fig. 2, PGA _ Ad1 represents a first analog signal. Compared with the common differential bias circuit in the prior art, the T-shaped filter circuit formed by the matching resistors is added in the differential bias circuit, and the signal transmission capability and the interference signal filtering capability of the differential bias circuit can be further improved through the arrangement structure.
As a preferred embodiment, the voltage tracking module comprises:
and the two voltage tracking circuits are arranged and have the same structure and are used for respectively carrying out voltage tracking on the first analog signal and the second analog signal to obtain the first analog signal and the second analog signal.
In order to adapt to the differential bias circuit provided in the foregoing embodiment, the voltage tracking module provided in this embodiment is provided with two voltage tracking circuits having the same structure, where one voltage tracking circuit is configured to perform voltage tracking on the first analog signal to obtain the first analog signal; and the other voltage tracking circuit is used for carrying out voltage tracking on the second analog signal to obtain the second analog signal.
As a preferred embodiment, the voltage tracking circuit includes: a twelfth resistor R12, a thirteenth resistor R13, a second differential amplifier N2, a first inductor L1, a fourteenth capacitor C14, a fifteenth capacitor C15, a first diode D1, and a second diode D2;
a second end of the twelfth resistor R12 is connected to a positive input end of the second differential amplifier N2, a ground end of the second differential amplifier N2 is grounded, a negative input end of the second differential amplifier N2 is connected to an output end of the second differential amplifier N2, power ends of the second differential amplifier N2 are respectively connected to a first end of the first inductor L1 and a first end of the fourteenth capacitor C14, a second end of the first inductor L1 is configured to receive a 5V voltage, a second end of the fourteenth capacitor C14 is grounded, an output end of the second differential amplifier N2 is connected to a first end of the thirteenth resistor R13, a second end of the thirteenth resistor R13 is respectively connected to a negative electrode of the first diode D1, a positive electrode of the second diode D2, and a first end of the fifteenth capacitor C15, a positive electrode of the first diode D1 is grounded, a negative electrode of the second diode D2 is configured to receive a Vref 3 voltage, and a second end of the fifteenth capacitor C15 is grounded;
accordingly, a first end of the twelfth resistor R12 is configured to receive the first analog signal, and a second end of the thirteenth resistor R13 is configured to output the first analog signal.
Referring to the circuit diagram shown in fig. 2, the voltage tracking module provided in this embodiment is used for performing voltage tracking on the first analog signal PGA _ Ad1 output by the differential bias circuit and outputting the first analog signal PGA _ Ad. Compared with the prior art, the front end of the first differential amplifier N1 is changed into a pi-type filtering mode from a traditional RC (resistance capacitance) filtering circuit or an LC (inductance capacitance) filtering circuit, so that the capability of the circuit for filtering interference signals can be further improved.
In the circuit diagram shown in fig. 2, the differential amplifier circuit can amplify the differential signal, suppress the common-mode signal, and condition the a-phase signal output by the sine-cosine encoder, so that the dc error signal can be eliminated, and at the same time, the common-mode noise and the even harmonic can be eliminated. The differential amplifying circuit works on the principle that the difference value of an input signal is amplified in an inverted mode, then the level is increased to a reference voltage point, and the voltage range of an output signal is determined by the peak value of the amplified signal and a reference potential point. Therefore, the differential signal is adjusted by the differential amplifying circuit and then conditioned to be a sine and cosine signal amplified by taking the reference voltage as the center and the peak value as the peak value of the input signal.
Specifically, in the circuit diagram shown in fig. 2, the amplification factor of the differential amplifier circuit is (R8 + R9)/(R4 + R5) =1.5, the input differential signal is a sine-cosine signal having a peak value of about 1V, and after passing through the differential amplifier circuit, the input differential signal becomes a sine wave having a peak value of 1.5V (a potential changes between 0.75V and 2.25V) with +1.5V as a center; then, the signal enters a signal processing module through a voltage follower circuit, an RC filter circuit and a clamping circuit to be subjected to AD sampling.
In this embodiment, the voltage tracking circuit has the isolation and impedance matching functions, and the clamp circuit limits the analog signal voltage input to the signal processing module to-0.7V-3.7V, so that the overall reliability of the signal processing module in the operation process can be effectively ensured, the sampling precision of the signal processing module can be improved, and the chip where the signal processing module is located can be protected.
As a preferred embodiment, the comparator includes:
and the two comparison circuits are arranged in the same structure and are used for respectively converting the first analog signal and the second analog signal into a first digital signal and a second digital signal.
In this embodiment, in order to convert the first analog signal and the second analog signal output by the voltage tracking module into corresponding digital signals, two comparison circuits with the same structure are provided in the comparator, wherein one comparison circuit is used to convert the first analog signal into the first digital signal, and the other comparison circuit is used to convert the second analog signal into the second digital signal.
Referring to fig. 3, fig. 3 is a structural diagram of a comparison circuit according to an embodiment of the invention. As a preferred embodiment, the comparison circuit comprises: a second first resistor R21, a second resistor R22, a second third resistor R23, a second fourth resistor R24, a second fifth resistor R25, a second sixth resistor R26, a second first capacitor C21, a second capacitor C22, a second third capacitor C23 and a first comparator N3;
the first end of the second resistor R21 is configured to receive a voltage of 1.5V, the second end of the second resistor R21 is connected to the first end of the second resistor R22, the first end of the second capacitor C21, the first end of the second third resistor R23, and the positive input end of the first comparator N3, the second end of the second resistor R22 is connected to the second end of the second capacitor C21 and grounded, the second end of the second third resistor R23 is connected to the first end of the second fourth resistor R24, the output end of the first comparator N3, and the first end of the second sixth resistor R26, the second end of the second fourth resistor R24 is configured to receive a voltage of 5V, the second end of the second sixth resistor R26 is connected to the first end of the second capacitor C23, the second end of the second capacitor C23 is grounded, the negative input end of the first comparator N3 is connected to the first end of the second resistor R25 and the first end of the second capacitor C22, and the second end of the second capacitor C22 is grounded;
accordingly, the second terminal of the fifth resistor R25 is configured to receive the first analog signal, and the second terminal of the sixth resistor R26 is configured to output the first digital signal.
In this embodiment, the comparator may convert the first analog signal PGA _ ad1 output by the voltage tracking circuit into a first digital signal PGA _1, that is, convert the first analog signal PGA _ ad1 into a corresponding square wave signal, so as to facilitate a subsequent process of measuring a speed of the pulse of the target permanent magnet synchronous motor.
It can be understood that when the analog signal and the pulse signal are used in cooperation to measure the speed of the target permanent magnet synchronous motor, the accuracy of determining the running speed of the target permanent magnet synchronous motor can be improved. In the comparator circuit, small disturbances in the vicinity of the comparison point can be suppressed by the hysteresis section of the comparator circuit.
As a preferred embodiment, the digital filtering module includes:
and the digital filtering circuit is used for respectively filtering the jitter signal and the spike interference signal in the first digital signal and the second digital signal to obtain a first digital filtering signal and a second digital filtering signal.
It can be understood that, in practical applications, the first digital signal and the second digital signal may be interfered by the switching power supply, the IGBT switch, and other signals, and in this embodiment, in order to filter out these interference signals, a digital filter circuit is disposed in the digital filter module, and the digital filter circuit is used to filter out the jitter signal and the spike interference signal in the first digital signal and the second digital signal, and thus obtain the first digital filtered signal and the second digital filtered signal.
Referring to fig. 4, fig. 4 is a structural diagram of a digital filter circuit according to an embodiment of the present invention. As a preferred embodiment, the digital filter circuit includes: a first inverter M1, a second inverter M2, a third inverter M3, a fourth inverter M4, a first exclusive or gate XOR1, a second exclusive or gate XOR2, a first D flip-flop Q1, a second D flip-flop Q2, a third first resistor R31, a third second resistor R32, a third resistor R33, a third fourth resistor R34, a third fifth resistor R35, a third sixth resistor R36, a third resistor R37, a third capacitor C31, a third second capacitor C32, a third capacitor C33, a third fourth capacitor C34, a third fifth capacitor C35, a third sixth capacitor C36, a third diode D3, a fourth diode D4, a fifth diode D5 and a sixth diode D6;
the input end of the first inverter M1 is connected to the first end of the third resistor R31 and the first end of the third capacitor C31, the second end of the third capacitor C31 is grounded, the output end of the first inverter M1 is connected to the first input end of the first XOR gate XOR1, the first end of the third resistor R32 and the D end of the second D flip-flop Q2, the second end of the third resistor R32 is connected to the second input end of the first XOR gate XOR1 and the first end of the third capacitor C32, the second end of the third capacitor C32 is grounded, the output end of the first XOR gate 1 is connected to the input end of the second inverter M2, the output end of the second inverter M2 is connected to the C end of the first D flip-flop Q1, the Q end of the first D flip-flop Q1 is connected to the first end of the third resistor R33, the second end of the third resistor R33 is connected to the negative electrode of the third diode D3, the positive electrode of the fourth diode D4 and the negative electrode of the third capacitor C33, the negative electrode of the third diode D33 is grounded, and the second end of the third diode D3 f is connected to the negative electrode of the third diode D3, and the fourth diode D3 is connected to the negative electrode of the third diode D3 f; an input end of a third inverter M3 is respectively connected with a first end of a third fourth resistor R34 and a first end of a third fourth capacitor C34, a second end of the third fourth capacitor C34 is grounded, an output end of the third inverter M3 is respectively connected with a D end of a first D flip-flop Q1, a first input end of a second exclusive or gate XOR2 and a first end of a third fifth resistor R35, a second end of the third fifth resistor R35 is respectively connected with a second input end of the second exclusive or gate XOR2 and a first end of a third fifth capacitor C35, a second end of the third fifth capacitor C35 is grounded, an output end of the second exclusive or gate XOR2 is connected with an input end of a fourth inverter M4, an output end of the fourth inverter M4 is connected with a C end of the second D flip-flop Q2, a Q end of the second D flip-flop Q2 is connected with a first end of a third sixth resistor R36, a second end of the third sixth resistor R36 is respectively connected with a cathode of a fifth diode D5, an anode of a sixth diode D6, a cathode of the sixth capacitor C36 is connected with a sixth diode D5, and a cathode of the sixth diode is grounded, and a cathode of the sixth diode is used for receiving a fifth diode Verf 3D 6; the S end of the first D trigger Q1 is respectively connected with the R end of the first D trigger Q1, the S end of the second D trigger Q2, the R end of the second D trigger Q2, the first end of the third-column resistor R37 and the first end of the third-column capacitor, the second end of the third-column resistor R37 is used for receiving 5V voltage, and the second end of the third-column capacitor is grounded;
accordingly, a first terminal of the third resistor R31 is configured to receive the first digital signal, a first terminal of the third fourth resistor R34 is configured to receive the second digital signal, a second terminal of the third resistor R33 is configured to output the first digital filtered signal, and a second terminal of the third sixth resistor R36 is configured to output the second digital filtered signal.
In the circuit diagram shown in fig. 4, PGA _1 and PGB _1 represent the first digital signal and the second digital signal, respectively, and PGA and PGB represent the first digitally filtered signal and the second digitally filtered signal, respectively. In order to facilitate the processing of the A-phase signal and the B-phase signal output by the sine and cosine encoder, the A-phase signal and the B-phase signal are sent to an ADC (analog-to-digital converter) unit in a signal processing module for processing, and simultaneously, the A-phase signal and the B-phase signal are converted into orthogonal square wave pulse signals and sent to a QEP (quantum dot inversion) orthogonal coding pulse unit in the signal processing module for counting the edge pulses of the orthogonal square wave pulse signals.
The third resistor R31, the third capacitor 31, the third fourth resistor R34 and the third fourth capacitor each form a low-pass filter circuit for filtering interference signals in PGA1_1 and PGB _2, and the third resistor R33, the third capacitor C33, the third sixth resistor R36 and the third sixth capacitor C36 each form a low-pass filter for filtering interference signals in square wave signals output by the two D flip-flops. The third diode D3 and the fourth diode D4 form a clamping circuit for limiting the voltage of the square wave signal input to the DSP chip to-0.7-3.7V, so that the safety of the DSP chip can be effectively ensured.
The first digital signal and the second digital signal can be converted into corresponding square wave signals through the inverter, the xor gate and the D flip-flop shown in fig. 4, wherein the inverter can effectively eliminate oscillation generated by high-frequency noise at a sinusoidal signal reference potential through positive threshold voltage and negative threshold voltage, and perform inverse shaping on the square wave signals output by the comparison circuit to obtain shaped signals. And then, one path of the shaping signal is indirectly sent to the exclusive-or gate through RC filtering, and the shaping signal has time delay during rising and falling due to the existence of the RC filtering circuit, so that two pulses are generated in one period, and after passing through the phase inverter, the rising edges of the two pulses are just in the stable state of the other phase of square wave, so that the signal can be ensured to be output in the most stable area, and an interference signal is prevented from being output at the jumping edge of the square wave, and thus, great jitter and a peak interference signal can be well inhibited.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, please refer to fig. 5, and fig. 5 is a structural diagram of a noise filtering module of a switching power supply according to an embodiment of the present invention. As a preferred embodiment, the switching power supply noise filtering module includes: a fourth first resistor R41, a fourth second resistor R42, a fourth capacitor C41, a third XOR gate XOR3, a first buffer B1 and a second buffer B2;
a second end of the fourth resistor R41 is connected to a first end of the fourth capacitor C41 and a first input end of the third exclusive or gate XOR3, respectively, a second end of the fourth capacitor C41 is grounded, an output signal of the third exclusive or gate XOR3 is inverted to an enable signal of the first buffer B1, and an output end of the first buffer B1 is connected to an enable end of the second buffer B2;
correspondingly, the first terminal of the fourth resistor R41, the second input terminal of the third XOR gate XOR3, and the input terminal of the second buffer B2 are all configured to receive the original signal, the input terminal of the first buffer B1 is configured to receive the driving signal output by the switching power supply, and the output terminal of the second buffer B2 is configured to output the target signal.
In fig. 5, signal a is the original communication signal, with power supply noise. If the signal is not processed, the communication signal is oscillated at the moment of noise generation, so that the level is turned over instantaneously, and the processor is in error identification. In the embodiment, the original communication signal a is delayed to obtain the signal B, and because the resistor and the capacitor in the delay circuit have a filtering effect, noise can be reduced. And performing exclusive or processing on the signals A and B to obtain a signal C. The signal C is a signal that converts the rising and falling edges of the original signal into level signals. See table 1 for truth table of signal C.
TABLE 1
| Signal A | Signal | Signal C | |
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 |
The noise in the original communication signal a is generated instantaneously by the switching tube in the switching power supply, and the driving signal D for the switching tube is needed here. The signal C is used as an enabling signal of the first buffer, and the signal E is obtained after the signal D passes through the first buffer. See table 2 for truth table for signal E:
TABLE 2
| Signal C | Signal | Signal E | |
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | * | |
| 1 | 1 | * |
Since the output signal of the buffer is in a high impedance state when the buffer is not enabled, the output terminal of the buffer should be pulled down to a low level. The final output signal F can then be obtained using the signal E as a latch signal for the original signal a. Due to the particularity of the signal E, the original signal is in a stable level state, and the last state is latched when the noise of the switching power supply enters, so that the potential hazard that the level of the original signal A is overturned is avoided. Therefore, the timing of the output signal F coincides with the timing of the original signal a.
Referring to fig. 6, fig. 6 is a schematic diagram of an output signal of a sine-cosine encoder. In fig. 6, a signal a is an original signal, a signal B is a delayed signal, a signal C is a signal obtained by performing exclusive or processing on the a signal and the B signal, a signal D is a driving signal synchronized with noise, a signal E is a buffered signal obtained by enabling the signal D using the signal C, and a signal F is a processed signal.
Referring to fig. 7, fig. 7 is a timing diagram of the noise filtering module of the switching power supply. In fig. 7, a, B, C, D, and R denote an a-phase signal, a B-phase signal, a C-phase signal, a D-phase signal, and an R-phase signal output from the sine-cosine encoder, respectively.
In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The signal processing apparatus of a sine-cosine encoder provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A signal processing apparatus of a sine-cosine encoder, comprising:
the differential offset module is used for carrying out differential offset processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a target analog signal;
the voltage tracking module is used for carrying out voltage tracking on the target analog signal to obtain a target analog tracking signal;
the comparison module is used for converting the target analog signal into a target digital signal;
the digital filtering module is used for filtering out a jitter signal and a spike interference signal in the target digital signal to obtain a target digital filtering signal;
the switching power supply noise filtering module is used for processing noise interference generated when the switching power supply is switched on or switched off to obtain a target signal for filtering the noise;
and the signal processing module is used for determining the running speed of the target permanent magnet synchronous motor according to the target analog tracking signal and the target signal.
2. The signal processing apparatus of claim 1, wherein the differential bias module comprises:
and the two differential bias circuits with the same structure are used for respectively carrying out differential bias processing on the A-phase signal and the B-phase signal output by the sine and cosine encoder to obtain a first analog signal and a second analog signal.
3. The signal processing apparatus of claim 2, wherein the differential bias circuit comprises: eleven resistors, thirteen capacitors and a first differential amplifier;
wherein, the first end of the first resistor is respectively connected with the first end of the second capacitor, the first end of the third capacitor and the first end of the fourth resistor, the second end of the second capacitor is grounded, the second end of the first resistor is respectively connected with the first end of the second resistor and the first end of the third resistor, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the second resistor is respectively connected with the second end of the third capacitor, the first end of the fourth capacitor and the first end of the sixth resistor, the second end of the fourth capacitor is grounded, the second end of the second capacitor is respectively connected with the first end of the fifth capacitor and the first end of the eighth capacitor, the second end of the fifth capacitor is respectively connected with the second end of the fourth resistor, the first end of the fifth resistor and the first end of the sixth capacitor, a second end of the sixth capacitor is connected to the second end of the sixth resistor, the first end of the seventh capacitor, and the first end of the seventh resistor, a second end of the seventh capacitor is grounded, a second end of the eighth capacitor is connected to the first end of the eighth resistor, the first end of the ninth capacitor, and the second end of the fifth resistor, a second end of the ninth capacitor is connected to the second end of the seventh resistor and the first end of the tenth capacitor, a second end of the tenth capacitor is grounded, a second end of the eighth resistor is connected to the first end of the ninth resistor, a second end of the ninth resistor is configured to receive a voltage of 1.5V, a second end of the ninth resistor is connected to the first end of the twelfth capacitor and the first end of the eleventh capacitor, a second end of the twelfth capacitor is grounded, and a second end of the eleventh capacitor is connected to the first end of the eighth resistor and the positive input end of the first differential amplifier, a negative input end of the first differential amplifier is connected with a second end of the seventh resistor, a first end of the tenth resistor and a first end of the thirteenth capacitor respectively, and a second end of the tenth resistor is connected with a first end of the eleventh resistor;
correspondingly, a first end of the first resistor and a second end of the second resistor are respectively used for receiving a positive-phase signal and a negative-phase signal in the a-phase signal, and a common end formed by an output end of the first differential amplifier, a second end of the eleventh resistor, and a second end of the thirteenth capacitor is used for outputting the first analog signal.
4. The signal processing apparatus of claim 2, wherein the voltage tracking module comprises:
and the two voltage tracking circuits are arranged in the same structure and are used for respectively carrying out voltage tracking on the first analog signal and the second analog signal.
5. The signal processing apparatus of claim 4, wherein the voltage tracking circuit comprises: the circuit comprises a twelfth resistor, a thirteenth resistor, a second differential amplifier, a first inductor, a fourteenth capacitor, a fifteenth capacitor, a first diode and a second diode;
a second end of the twelfth resistor is connected to a positive input end of the second differential amplifier, a ground end of the second differential amplifier is grounded, a negative input end of the second differential amplifier is connected to an output end of the second differential amplifier, power ends of the second differential amplifier are respectively connected to a first end of the first inductor and a first end of the fourteenth capacitor, a second end of the first inductor is configured to receive a 5V voltage, a second end of the fourteenth capacitor is grounded, an output end of the second differential amplifier is connected to a first end of the thirteenth resistor, a second end of the thirteenth resistor is respectively connected to a negative electrode of the first diode, a positive electrode of the second diode and a first end of the fifteenth capacitor, a positive electrode of the first diode is grounded, a negative electrode of the second diode is configured to receive a 3Vref voltage, and a second end of the fifteenth capacitor is grounded;
correspondingly, a first end of the twelfth resistor is configured to receive the first analog signal, and a second end of the thirteenth resistor is configured to output the first analog signal.
6. The signal processing apparatus of claim 4, wherein the comparison module comprises:
and the two comparison circuits are arranged in the same structure and are used for respectively converting the first analog signal and the second analog signal into a first digital signal and a second digital signal.
7. The signal processing apparatus of claim 6, wherein the comparison circuit comprises: the first resistor, the second third resistor, the second fourth resistor, the second fifth resistor, the second sixth resistor, the second capacitor, the second capacitor, the second third capacitor and the first comparator;
the first end of the second resistor is used for receiving a 1.5V voltage, the second end of the second resistor is respectively connected with the first end of the second resistor, the first end of the second capacitor, the first end of the second third resistor and the positive input end of the first comparator, the second end of the second resistor is connected with the second end of the second capacitor and grounded, the second end of the second third resistor is respectively connected with the first end of the second fourth resistor, the output end of the first comparator and the first end of the second sixth resistor, the second end of the second fourth resistor is used for receiving a 5V voltage, the second end of the second sixth resistor is connected with the first end of the second third capacitor, the second end of the second third capacitor is grounded, the negative input end of the first comparator is respectively connected with the first end of the second fifth resistor and the first end of the second capacitor, and the second end of the second capacitor is grounded;
correspondingly, the second end of the second fifth resistor is configured to receive the first analog signal, and the second end of the second sixth resistor is configured to output the first digital signal.
8. The signal processing apparatus of claim 6, wherein the digital filtering module comprises:
and the digital filtering circuit is used for respectively filtering the jitter signal and the spike interference signal in the first digital signal and the second digital signal to obtain a first digital filtering signal and a second digital filtering signal.
9. The signal processing apparatus of claim 8, wherein the digital filter circuit comprises: the three-phase inverter comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a first exclusive-OR gate, a second exclusive-OR gate, a first D trigger, a second D trigger, a third first resistor, a third second resistor, a third resistor, a third fourth resistor, a third fifth resistor, a third sixth resistor, a third pseudo-resistor, a third first capacitor, a third second capacitor, a third fourth capacitor, a third fifth capacitor, a third sixth capacitor, a pseudo-capacitor, a third diode, a fourth diode, a fifth diode and a sixth diode;
the input end of the first inverter is respectively connected with the first end of the third resistor and the first end of the third capacitor, the second end of the third capacitor is grounded, the output end of the first inverter is respectively connected with the first input end of the first exclusive-or gate, the first end of the third resistor and the D end of the second D trigger, the second end of the third resistor is respectively connected with the second input end of the first exclusive-or gate and the first end of the third capacitor, the second end of the third capacitor is grounded, the output end of the first exclusive-or gate is connected with the input end of the second inverter, the output end of the second inverter is connected with the C end of the first D trigger, the Q end of the first D trigger is connected with the first end of the third resistor, the second end of the third resistor is respectively connected with the negative electrode of the third diode, the positive electrode of the fourth diode and the first end of the third capacitor, the positive electrode of the third diode is grounded, the negative electrode of the fourth diode is used for receiving the Verf 3 negative electrode of the third capacitor; the input end of the third inverter is respectively connected with the first end of a third fourth resistor and the first end of a third fourth capacitor, the second end of the third fourth capacitor is grounded, the output end of the third inverter is respectively connected with the D end of the first D flip-flop, the first input end of the second exclusive-OR gate and the first end of a third fifth resistor, the second end of the third fifth resistor is respectively connected with the second input end of the second exclusive-OR gate and the first end of the third fifth capacitor, the second end of the third fifth capacitor is grounded, the output end of the second exclusive-OR gate is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the C end of the second D flip-flop, the Q end of the second D flip-flop is connected with the first end of the third sixth resistor, the second end of the third resistor is respectively connected with the cathode of the fifth diode, the anode of the sixth diode and the first end of the third sixth capacitor, the anode of the fifth diode is grounded, and the cathode of the sixth diode is used for receiving the third end of the Verf 3; the S end of the first D trigger is respectively connected with the R end of the first D trigger, the S end of the second D trigger, the R end of the second D trigger, the first end of the pseudo-ginseng resistor and the first end of the pseudo-ginseng capacitor, the second end of the pseudo-ginseng resistor is used for receiving 5V voltage, and the second end of the pseudo-ginseng capacitor is grounded;
correspondingly, the first terminal of the third first resistor is configured to receive the first digital signal, the first terminal of the third fourth resistor is configured to receive the second digital signal, the second terminal of the third resistor is configured to output the first digital filtered signal, and the second terminal of the third sixth resistor is configured to output the second digital filtered signal.
10. The signal processing apparatus of any one of claims 1 to 9, wherein the switching power supply noise filtering module comprises: the first capacitor is connected with the first resistor, the second capacitor is connected with the second capacitor, and the first capacitor is connected with the second capacitor;
a second end of the fourth resistor is connected to a first end of the fourth capacitor and a first input end of the third exclusive or gate, respectively, a second end of the fourth capacitor is grounded, an output signal of the third exclusive or gate is inverted to an enable signal of the first buffer, and an output end of the first buffer is connected to an enable end of the second buffer;
correspondingly, the first end of the fourth resistor, the second input end of the third exclusive-or gate, and the input end of the second buffer are all configured to receive an original signal, the input end of the first buffer is configured to receive a driving signal output by the switching power supply, and the output end of the second buffer is configured to output the target signal.
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| CN102472640A (en) * | 2010-01-07 | 2012-05-23 | 川崎重工业株式会社 | Resolver signal conversion device and method |
| CN105486329A (en) * | 2014-10-01 | 2016-04-13 | Ad技术有限公司 | Decoding circuit for rotary encoder |
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| CN202009380U (en) * | 2011-03-15 | 2011-10-12 | 无锡市展鹏科技有限公司 | Acquisition card for sine and cosine encoder |
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