CN113948026A - Zoom controller, display device and data processing method - Google Patents
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Abstract
本公开涉及缩放控制器、显示装置与数据处理方法。一种缩放控制器包括输入接口、输出垂直同步脉冲产生电路与数据缓存电路。输入接口用以接收一输入垂直同步脉冲与输入影像数据。输出垂直同步脉冲产生电路耦接输入接口，用以响应于输入垂直同步脉冲对应地产生第一输出垂直同步脉冲与第一输出请求。数据缓存电路用以缓存输入影像数据，并且响应于第一输出请求对应地根据输入影像数据输出第一输出帧。输出垂直同步脉冲产生电路更根据第一输出垂直同步脉冲与第一既定周期产生第二输出垂直同步脉冲与第二输出请求，并且数据缓存电路更响应于第二输出请求对应地根据输入影像数据输出第二输出帧。
The present disclosure relates to a zoom controller, a display device, and a data processing method. A scaling controller includes an input interface, an output vertical synchronization pulse generating circuit and a data buffer circuit. The input interface is used for receiving an input vertical sync pulse and input image data. The output vertical sync pulse generating circuit is coupled to the input interface, and is used for correspondingly generating a first output vertical sync pulse and a first output request in response to the input vertical sync pulse. The data buffer circuit is used for buffering the input image data, and correspondingly outputting the first output frame according to the input image data in response to the first output request. The output vertical sync pulse generating circuit further generates a second output vertical sync pulse and a second output request according to the first output vertical sync pulse and the first predetermined period, and the data buffer circuit is further responsive to the second output request and outputs correspondingly according to the input image data Second output frame.
Description
Technical Field
The present invention relates to a data processing method, and more particularly, to a data processing method for dynamically performing frame rate conversion, so as to generate an output video signal with a frame rate (frame rate) that can be supported by a display panel according to an input video signal with a frame rate that cannot be supported by the display panel.
Background
Generally, to ensure low latency and synchronization of the output video signal, the input interface and the output interface of the scaler (scaler) may operate in a Frame sync mode (Frame sync mode). In the frame synchronization mode, the vertical synchronization signals vsync (vertical synchronization) sent from the output interface and provided to the rear display panel are synchronously generated according to the vertical synchronization signals received from the image source by the input interface.
However, when the input video signal is at a frame rate that cannot be supported by the display panel, if the display panel is operated in the frame synchronization mode, the frame rate of the output video signal is also at a frame rate that cannot be supported by the display panel, and thus a display abnormality occurs.
To solve the above problems, a novel data processing method is needed, which can dynamically perform frame rate conversion when needed, so as to generate an output video signal with a frame rate that can be supported by a display panel according to an input video signal with a frame rate that cannot be supported by the display panel, and the delay of the output video signal can also meet the low delay of the specification requirement.
Disclosure of Invention
An object of the present invention is to generate an output video signal having a frame rate supportable by a display panel based on an input video signal having a frame rate not supportable by the display panel, and to generate a low delay in which a delay of the output video signal meets a specification requirement.
According to an embodiment of the present invention, a scaling controller includes an input interface, an output vertical synchronization pulse generating circuit, and a data buffer circuit. The input interface is used for receiving an input vertical synchronous pulse and input image data. The output vertical synchronization pulse generating circuit is coupled to the input interface and is used for responding to the input vertical synchronization pulse to correspondingly generate a first output vertical synchronization pulse and a first output request. The data buffer circuit is used for buffering input image data and correspondingly outputting a first output frame according to the input image data in response to the first output request. The output vertical synchronization pulse generating circuit further generates a second output vertical synchronization pulse and a second output request according to the first output vertical synchronization pulse and the first predetermined period, and the data buffer circuit correspondingly outputs a second output frame according to the input image data in response to the second output request.
According to another embodiment of the present invention, a display device includes a zoom controller and a display panel. The scaling controller receives an input vertical synchronization pulse and input image data from an image source, generates a plurality of output vertical synchronization pulses according to the input vertical synchronization pulse, and generates a plurality of output frames according to the input image data. The display panel is coupled to the scaling controller for displaying the output frame according to the output vertical synchronization pulse. The output vertical synchronization pulse includes at least a first output vertical synchronization pulse and a second output vertical synchronization pulse, the output frame includes at least a first output frame and a second output frame, the scaling controller correspondingly generates a first output vertical synchronization pulse in response to the input vertical synchronization pulse, and correspondingly outputs the first output frame in response to the first output vertical synchronization pulse. The scaling controller further generates a second output vertical synchronization pulse according to the first output vertical synchronization pulse and a first predetermined period, and correspondingly outputs a second output frame in response to the second output vertical synchronization pulse.
According to another embodiment of the present invention, a data processing method includes: receiving an input vertical synchronization pulse and input image data from an image source; generating a plurality of output vertical synchronization pulses according to the input vertical synchronization pulses; and generating a plurality of output frames according to the input image data. The step of generating the output vertical synchronization pulse according to the input vertical synchronization pulse further comprises: correspondingly generating a first output vertical synchronous pulse in response to the input vertical synchronous pulse; and generating a second output vertical synchronization pulse according to the first output vertical synchronization pulse and the first predetermined period, and generating an output frame according to the input image data further comprises: correspondingly outputting the input frame as a first output frame in response to the first output vertical synchronization pulse; and correspondingly outputting the input frame as a second output frame in response to the second output vertical synchronization pulse.
Drawings
Fig. 1 is a block diagram of a display device according to an embodiment of the invention.
FIG. 2 is a flow chart of a data processing method according to an embodiment of the invention.
FIG. 3 shows an example of an input image signal and an output image signal according to an embodiment of the present invention.
FIG. 4 shows an example of an input image signal and an output image signal according to another embodiment of the present invention.
Detailed Description
Fig. 1 is a block diagram of a display device according to an embodiment of the invention. The display device 100 may include a zoom controller (scaler) 110 and a display panel 120. The scaling controller 110 receives an input vertical synchronization signal Vsync _ in and input image Data from an image source 200. The image source 200 is an electronic device capable of providing image data, such as a computer host, a mobile communication device, a set-top box, etc. The input vertical synchronization signal Vsync _ in may include a plurality of input vertical synchronization pulses (hereinafter, referred to as Vsync pulses), and the input image Data may include a plurality of input frames.
Generally, the image source 200 sequentially outputs a Vsync pulse and image data (e.g., a frame) corresponding thereto to the display device 100, so that the display panel 120 can display the corresponding frame after a predetermined delay in response to the Vsync pulse. In addition, the scaling controller 110 may perform data processing operations such as frame scaling, frame rate conversion, etc. on the received frame data, and then provide the processed data (including Vsync pulses and image data) to the display panel 120.
According to an embodiment of the present invention, the scaling controller 110 may include at least an input interface 110-1, an output interface 110-2, a measurement circuit 110-3, an output vertical synchronization pulse generation circuit 110-4, and a data buffer circuit 110-5. It is noted that fig. 1 is a simplified block diagram of a display device, in which only the elements relevant to the present invention are shown. Those skilled in the art will appreciate that the display device may include many elements not shown in FIG. 1 to perform the display and related data processing functions.
The input interface 110-1 is used for receiving an input vertical synchronization signal Vsync _ in, input video Data, and a frame rate control signal FPS _ Ctrl from the video source 200. The frame rate control signal FPS _ Ctrl is a switching signal for informing the display apparatus 100 whether the image data provided by the image source 200 is to be the image data of a low frame rate. For example, the signal level of the frame rate control signal FPS _ Ctrl can be switched between a first state (e.g., logic 0) and a second state (e.g., logic 1). The first state represents that the subsequent image data is image data with a non-low frame rate, and the second state represents that the subsequent image data is image data with a low frame rate. The image source 200 can notify the display device 100 at least in advance of the previous frame. For example, assuming that the current Frame is the video data transmitted according to the High Definition Multimedia Interface (abbreviated HDMI) Variable Refresh Rate specification (abbreviated VRR), the next Frame is the video data transmitted according to the HDMI 2.1 Cinema VRR, and the Frame Rate (fpabbreviated s) specified by the HDMI 2.1 Cinema VRR (e.g., 24FPS, 25FPS, 30FPS) is very low compared to the currently commonly used Frame Rate, the video source 200 may switch the signal level of the Frame Rate control signal FPS _ Ctrl from the first state to the Second state in the control signal transmission interval of the current Frame to notify the display device 100 that the next Frame is the low Frame Rate video data transmitted according to the HDMI 2.1 Cinema VRR.
The measurement circuit 110-3 can obtain the input vertical synchronization signal Vsync _ in and the input image Data from the input interface 110-1, and measure the frame rate corresponding to each frame according to the input vertical synchronization signal Vsync _ in and the input image Data. Generally, the frame rate corresponding to one frame is defined by the Vsync pulse corresponding to this frame and the Vsync pulse corresponding to the next frame, and the measurement circuit 110-3 can obtain the frame rate corresponding to one frame according to the reciprocal of the time interval between two adjacent Vsync pulses.
The output vertical synchronization pulse generating circuit 110-4 is configured to generate an output vertical synchronization signal Vsync _ Out, which may include a plurality of output Vsync pulses, and an output request Out _ Req according to the input vertical synchronization signal Vsync _ in and the frame rate control signal FPS _ Ctrl.
The Data buffer circuit 110-5 is used for buffering the input video Data and outputting the buffered video Data as the output video Data _ Out according to the output request Out _ Req, wherein the output video Data _ Out may include a plurality of output frames.
The output interface 110-2 is coupled to the display panel 120 for providing the output vertical synchronization signal Vsync _ Out and the output image Data _ Out to the display panel 120. The display panel 120 may correspondingly display an output frame according to the output Vsync pulse of the output vertical synchronization signal Vsync _ out.
In order to avoid the above-mentioned display abnormality problem, according to an embodiment of the present invention, when processing the image Data with a low frame rate (for example, lower than the lowest frame rate supported by the display panel 120), the scaling controller 110 may generate a plurality of output Vsync pulses according to one input Vsync pulse, and generate a plurality of output frames according to the input image Data, thereby increasing the frame rate corresponding to the output frames to the frame rate range supported by the display panel 120, and simultaneously ensuring the low latency and synchronization of the output image signals. The frame rate range supported by the display panel 120 is usually recorded in Extended display capability identification data (EDID), which may be stored in an internal memory (not shown) of the zoom controller 110 or defined in the system program code thereof.
FIG. 2 is a flow chart of a data processing method according to an embodiment of the invention. The data processing method may include the following steps performed by the zoom controller 110:
in step S202, an input Vsync pulse and input image data are received from an image source.
In step S204, a plurality of output Vsync pulses are generated according to the input Vsync pulses.
In step S206, a plurality of output frames are generated according to the input image data.
More specifically, in response to the input Vsync pulse, the output vertical synchronization pulse generating circuit 110-4 may first correspondingly generate a first output Vsync pulse. In the embodiment of the invention, as in the frame synchronization mode, the first output Vsync pulse is synchronously generated according to the input Vsync pulse, for example, the output vertical synchronization pulse generating circuit 110-4 may directly provide the received input Vsync pulse to the display panel 120. Herein, synchronously generating the output Vsync pulse according to the input Vsync pulse means that only a reasonable circuit transfer delay, for example, a delay time required through several line buffer circuits inside the scaling controller 110, is included between the time point when the input Vsync pulse is received and the time point when the output Vsync pulse is generated.
In addition, the output vertical synchronization pulse generating circuit 110-4 also correspondingly generates the first output request according to the first output Vsync pulse. In response to the first output request, the data buffer circuit 110-5 correspondingly generates a first output frame according to the buffered input image data. For example, the data buffer circuit 110-5 outputs the received input frame as a first output frame in response to the first output request, so that the scaling controller 110 may correspondingly output the input frame as the first output frame through the output interface 110-2 in response to the first output Vsync pulse.
Then, the output vertical synchronization pulse generating circuit 110-4 further generates a second output Vsync pulse according to the first output Vsync pulse and a predetermined period. In an embodiment of the invention, the interval between the first output Vsync pulse and the second output Vsync pulse may be designed according to the predetermined period. For example, the interval between the first output Vsync pulse and the second output Vsync pulse may be equal to the predetermined period. The output vertical synchronization pulse generating circuit 110-4 also correspondingly generates a second output request according to the second output Vsync pulse.
In response to the second output request, the data buffer circuit 110-5 correspondingly generates a second output frame according to the buffered input image data. For example, the data buffer circuit 110-5 outputs the received input frame as a second output frame again in response to the second output request, so that the scaling controller 110 may correspondingly output the input frame as a second output frame through the output interface 110-2 in response to the second output Vsync pulse.
In the embodiment of the invention, the number of output Vsync pulses (and output frames) generated by the scaling controller 110 corresponding to an input Vsync pulse (and an input frame) may be determined according to the difference or multiple relationship between the frame rate supportable by the display panel 120 and the input frame rate. For example, when the N times of the input frame rate is within the frame rate range supported by the display panel 120, the scaling controller 110 may generate N output Vsync pulses (and N output frames) according to one input Vsync pulse (and one input frame), so that the output frame rate corresponding to each output frame is higher than the input frame rate, and the output frame rates corresponding to each output frame are all the frame rates supported by the display panel 120.
Fig. 3 shows an example of input and output video signals according to an embodiment of the present invention, in which the horizontal axis is the time axis, the input/output video signals include input/output Vsync pulses (indicated by upward arrows in fig. 3) and input/output video data (a square in fig. 3 represents a frame).
In this example, N is 2, i.e., one input frame time is equal to two output frame times. The scaling controller 110 generates two output Vsync pulses 311 and 312 corresponding to the input Vsync pulse 301, and two output Vsync pulses 321 and 322 corresponding to the input Vsync pulse 302. In addition, the scaling controller 110 also generates two output frames F11 and F12 according to the input frame F1, and two output frames F21 and F22 according to the input frame F2.
Assuming that the interval between the input Vsync pulses 301 and 302 is 40 milliseconds (ms), the input frame rate of the input frame F1 is 25Hz, which is lower than the lowest frame 40Hz that the display panel 120 can support. In the embodiment of the present invention, the predetermined time may be set to 20 milliseconds, which corresponds to a frame rate of 50Hz supported by the display panel 120. The scaling controller 110 (or, the output vertical sync pulse generating circuit 110-4) may first synchronously generate the output Vsync pulse 311 from the input Vsync pulse 301, and the data buffer circuit 110-5 correspondingly outputs the buffered frame as the output frame F11. Then the scaler 110 generates another output Vsync pulse 312 by itself after counting 20 ms, and the data buffer circuit 110-5 outputs the buffered frame as the output frame F12 again, wherein the output frame F11, the output frame F12 may be the same as the input frame F1. By this operation, the output frame rate of the output frame F11 and the output frame F12 is increased to 50Hz, which is higher than the input frame rate of 25Hz, and is a frame rate that the display panel 120 can support.
In the embodiment of the present invention, the scaling controller 110 is not limited to increasing the output frame rate by dividing the time between two input Vsync pulses equally. The time between the two input Vsync pulses may also be divided unequally, which also results in an increased output frame rate.
Assuming that the input frame rate of the input frame F2 is 25Hz, the lowest frame that the display panel 120 can support is 30 Hz. The scaling controller 110 (or the output vertical synchronization pulse generating circuit 110-4) may also set the predetermined time to 10 milliseconds, which corresponds to a frame rate of 100Hz supported by the display panel 120. Similarly, the scaling controller 110 (or, the output vertical sync pulse generating circuit 110-4) may first synchronously generate the output Vsync pulse 321 from the input Vsync pulse 302, and the data buffer circuit 110-5 correspondingly outputs the buffered frame as the output frame F21. Then the scaler 110 generates another output Vsync pulse 322 by itself after counting 10 ms, and the data buffer circuit 110-5 outputs the buffered frame as the output frame F22 again, wherein the output frame F21, the output frame F22 may be the same as the input frame F2. By this operation, the output frame rates of the output frame F21 and the output frame F22 are respectively increased to 100Hz and 33Hz, which are higher than the input frame rate of 25Hz and are a frame rate that the display panel 120 can support.
In the embodiment of the present invention, N may also be a positive integer greater than 2.
FIG. 4 shows an example of an input image signal and an output image signal according to another embodiment of the present invention. In this example, N is 3, i.e., one input frame time is equal to three output frame times. The scaling controller 110 correspondingly generates three output Vsync pulses 411, 412, and 413 from the input Vsync pulse 401, and three output frames F11, F12, and F13 from the input frame F1. Assuming that the input frame rate of the input frame F1 is 24Hz, which is lower than the lowest frame 40Hz supported by the display panel 120, the predetermined time may be set to 1/72 seconds, which corresponds to a frame rate 72Hz supported by the display panel 120.
The scaling controller 110 (or, the output vertical sync pulse generating circuit 110-4) may first synchronously generate the output Vsync pulse 411 from the input Vsync pulse 401, and the data buffer circuit 110-5 correspondingly outputs the buffered frame as the output frame F11. Then, the scaling controller 110 generates another Vsync pulse 412 by itself after counting 1/72 seconds, and the data buffer circuit 110-5 outputs the buffered frame as an output frame F12 again. Then, the scaling controller 110 generates a further output Vsync pulse 413 by itself after counting 1/72 seconds, and the data buffer circuit 110-5 outputs the buffered frame as the output frame F13 again, wherein the output frames F11, F12 and F13 may be identical in content to the input frame F1.
By this operation, the output frame rates corresponding to the output frames F11, F12, and F13 are increased to 72Hz, which is higher than the input frame rate of 24Hz, and a frame rate that can be supported by the display panel 120.
It should be noted that, in the embodiment of the present invention, the predetermined time period is selected and designed according to the frame rate range supported by the display panel 120, so that the output frame rate falls within the frame rate range supported by the display panel 120.
Assuming that the input frame rate is f1 and the output frame rates are fa and fb1, assuming that N is 2, the predetermined time corresponding to the output frame rate fa should be designed so that the following formula (1) is satisfied, and fa and fb1 should be the frame rates supported by the display panel:
in the embodiment of the present invention, since the scaling controller 110 needs to measure the time interval between two Vsync pulses adjacent to the current frame (input frame) through the measurement circuit 110-3 to know the input frame rate corresponding to the input frame, when the possible input frame rate is known, the output frame rate to be achieved can be designed according to the possible input frame rate and the value of N, and one or more sets of corresponding setting values are generated, so that after the scaling controller 110 adopts the setting values, the output frame rate can be increased and fall within the frame rate range supported by the display panel 120 regardless of the input low frame rate.
Table 1 shows the output frame rate achieved by the first set of settings according to an embodiment of the present invention.
| 24Hz | 25H | 30Hz | |
| First output frame rate | 48Hz | 48Hz | 48Hz |
| Second output frame rate | 48Hz | 52Hz | 80Hz |
TABLE 1 output frame Rate achieved by first set of settings
In this example, N is 2, and possible input frame rates are 24Hz, 25Hz, and 30 Hz. In the first set of settings, the time interval (i.e., the predetermined period) between the first output Vsync pulse and the second output Vsync pulse is fixed to 1/48 seconds, so that the first output frame rate is fixed to 48Hz, the second output frame rate is the reciprocal of the remaining frame time obtained by subtracting the predetermined period from the input frame time, and varies depending on the input frame rate, and the second output frame rate may be 48Hz, 52Hz, or 80Hz as shown in table 1.
In other words, when the scaling controller 110 determines to process the low frame rate image data with the first set of settings, and detects that the image source 200 switches the signal level of the frame rate control signal FPS _ Ctrl from the first state to the second state, the scaling controller 110 synchronously generates the first output Vsync pulse according to the input Vsync pulse received later, and then automatically generates the second output Vsync pulse after counting 1/48 seconds. By doing so, the output frame rate of the first output frame is increased to 48Hz, and the output frame rate of the second output frame can be 48Hz, 52Hz or 80Hz as shown in Table 1. On the other hand, when it is detected that the image source 200 switches the signal level of the frame rate control signal FPS _ Ctrl from the second state to the first state, the scaling controller 110 does not need to perform the frame rate conversion.
Table 2 shows the frame rate achieved by the second set of settings according to another embodiment of the present invention.
| 24Hz | 25H | 30Hz | |
| First output frame rate | 60Hz | 60Hz | 60Hz |
| Second output frame rate | 40Hz | 42Hz | 60Hz |
TABLE 2 output frame Rate achieved by the second set of settings
In this example, N is 2, and possible input frame rates are 24Hz, 25Hz, and 30 Hz. In the second set of settings, the predetermined period is fixed to 1/60 seconds, the first output frame rate can be fixed to 60Hz, and the second output frame rate can be 40Hz, 42Hz or 60Hz, depending on the input frame rate, as shown in Table 1.
When determining the set value for processing the low frame rate image data, if N is 3, the time interval (e.g., the first predetermined period) between the first output Vsync pulse and the second output Vsync pulse may be fixed to a first fixed value, and the time interval (e.g., the second predetermined period) between the second output Vsync pulse and the third output Vsync pulse may be fixed based on the similar concept. By setting the first output frame rate and the second output frame rate, the third output frame rate can be naturally formed. The case where N >3 is analogized.
In embodiments of the present invention, the first output frame rate in a setting may be selected to be an integer multiple of one of the possible input frame rates. In addition, when there are more than one set of setting values available for processing the low frame rate image data, which set of setting values is used can be selected according to the frame rate range supported by the display panel 120 and the output frame rate achieved by each set of setting. For example, if the output frame rates achieved by the first set of settings all fall within the frame rate range supported by the display panel 120, the first set of settings may be selected. Conversely, if the output frame rates achieved by the first set of settings do not all fall within the frame rate range supported by the display panel 120, but the output frame rates achieved by the second set of settings all fall within the frame rate range supported by the display panel 120, the second set of settings may be selected.
By the data processing method provided by the present invention, the frame rate conversion is dynamically performed according to the signal level of the frame rate control signal FPS _ Ctrl and the setting value of the low frame rate image data, so as to generate the output image signal with the frame rate that the display panel can support, and the delay of the output image signal can also meet the low delay of the standard requirement. Furthermore, the present invention is not limited to processing HDMI 2.1 Cinema VRR low frame rate video, but can be applied to processing any data processing scenario requiring frame rate conversion.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
[ notation ] to show
100 display device
110 zoom controller
110-1 input interface
110-2 output interface
110-3 measuring circuit
110-4 output vertical synchronous pulse generating circuit
110-5 data buffer circuit
120 display panel
200 image source
Data input image Data
Data _ Out for outputting image Data
FPS _ Ctrl frame rate control signal
Out _ Req output request
Vsync _ in input vertical synchronization signal
Vsync _ out outputting vertical synchronization signal
301,302,401,402 input Vsync pulse
311,312,321,322,411,412,413 outputting Vsync pulse
F1, F2, F11, F12, F13, F21, F22 frames
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| CN102300107A (en) * | 2010-06-28 | 2011-12-28 | 宏碁股份有限公司 | Video conversion device and video signal conversion method |
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