CN113946532B - A method for protecting satellite-borne 1553B control bus from failure - Google Patents
A method for protecting satellite-borne 1553B control bus from failure Download PDFInfo
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- CN113946532B CN113946532B CN202110988293.9A CN202110988293A CN113946532B CN 113946532 B CN113946532 B CN 113946532B CN 202110988293 A CN202110988293 A CN 202110988293A CN 113946532 B CN113946532 B CN 113946532B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
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Abstract
A satellite-borne 1553B control bus failure protection method comprises the steps that cold and hot reset identifiers and autonomous reset counts are stored in a storage module of a satellite-borne data transmission control unit; when the data transmission control unit is powered off and powered on again, the cold and hot reset mark is a cold reset mark, and the data transmission control unit enters a full-function mode; when the 1553B control bus has abnormal functions, the data transmission control unit cannot enter telemetry interruption, and at the moment, the cold and hot reset mark is a hot reset mark; the data transmission control unit performs autonomous reset, and the autonomous reset count is +1 after each autonomous reset, and if the number of continuous autonomous reset times is smaller than a set threshold value N, the data transmission control unit realizes autonomous reset, and the autonomous reset count is cleared; if the number of continuous autonomous reset times is greater than or equal to a set threshold value N, the data transmission control unit enters a minimum system mode. The invention can intelligently judge 1553B control bus failure, autonomously enter a minimum system mode, and does not need ground intervention, so that the data transmission control unit can still execute the most basic operation under the condition of 1553B control bus failure.
Description
Technical Field
The invention belongs to the technical field of satellite-borne data transmission control, and relates to a satellite-borne 1553B control bus failure protection method.
Background
The 1553B control bus is a data transmission bus with high reliability and good real-time performance, is suitable for working in severe environments with strong vibration, high noise, multiple dust and large temperature variation, is widely used in aerospace equipment and weaponry, and particularly has no manual maintenance opportunity when a satellite computer control system on satellite-borne equipment such as satellites, rockets, spacecraft and the like fails, so that the reliability of the satellite-borne equipment needs to be improved to the greatest extent in the design process.
In the prior art, in order to improve the operation reliability of the data transmission control unit, the data transmission control unit is generally provided with two systems capable of working independently, one of the systems is a full-function mode system, the other system is a minimum-function mode system, the full-function mode system can support all functional requirements under normal working conditions of the satellite-borne equipment, the minimum-function mode system can only realize the most basic and necessary telemetry and remote control functions, and the systems of the two modes are matched for use, so that the reliability of the satellite-borne equipment is greatly improved. However, in the on-orbit running process of the satellite-borne equipment, the interface chip of the 1553B control bus is damaged, so that the data transmission control unit cannot receive the bus command, and the switching of the two systems in different modes cannot be realized in a remote control mode or the like under the necessary condition, so that the data transmission control unit cannot work normally, and the task execution is affected.
Disclosure of Invention
The invention solves the technical problems that: the defect of the prior art is overcome, a satellite-borne 1553B control bus failure protection method is provided, and the technical problem that the task execution is affected due to the fact that a data transmission control unit cannot work normally under the condition that an interface chip of a 1553B control bus is damaged in the prior art is solved.
The solution of the invention is as follows:
A satellite-borne 1553B control bus failure protection method comprises the following steps:
a cold and hot reset identifier and an autonomous reset count are stored in a data transmission control unit storage module;
When the data transmission control unit is powered off and powered on again, the cold and hot reset identification is a cold reset identification, and when the data transmission control unit identifies the cold and hot reset identification as the cold reset identification, the data transmission control unit judges that the data transmission control unit is cold started and enters a full-function mode;
In a full-function mode, the data transmission control unit periodically executes telemetry interrupt according to signals of the 1553B control bus, and when the 1553B control bus is abnormal in function, the data transmission control unit cannot enter the telemetry interrupt, and at the moment, the cold and hot reset mark is a hot reset mark;
When the data transmission control unit recognizes that the cold and hot reset mark is the hot reset mark, performing autonomous reset, and counting +1 after each autonomous reset, if the number of continuous autonomous reset is smaller than a set threshold value N, the data transmission control unit realizes autonomous reset, and simultaneously, resetting the autonomous reset count; if the number of continuous autonomous reset times is greater than or equal to a set threshold value N, the data transmission control unit enters a minimum system mode.
After the data transmission control unit enters the minimum system mode, the playback serial instruction is executed, and after the playback serial instruction is executed, the data transmission control unit circularly feeds dogs and is in a standby state.
The data transmission control unit is provided with a timer, and the storage module is also stored with M seconds;
In the minimum system mode, when the data transmission control unit is in a standby state, judging the M second count through a timer, counting +1 every time the timer counts M seconds, if the M second count is greater than a preset count value P, the data transmission control unit enters a dog biting trap, and the data transmission control unit waits for the reset of the dog biting;
In the dog biting reset process, the data transmission control unit autonomously resets once every M seconds counted by the timer, and the data transmission control unit autonomously resets once every time, wherein the autonomous reset count is +1, when the autonomous reset count is greater than or equal to a set dog biting reset count threshold Q, the data transmission control unit enters a minimum system mode again to execute a playback string instruction, and the M seconds count is cleared, and the autonomous reset count is cleared.
In the storage module, the three variables of the cold and hot reset mark, the autonomous reset count and the M second count are stored in three parts respectively, and are modified in three parts when each time is required to be modified, and are read in two parts when judgment is required.
After the data transmission control unit enters the minimum system mode, when the ground transmits a data transmission power-off instruction and a data transmission power-on instruction, the data transmission control unit is started in a cold mode, and when the data transmission control unit is started in a cold mode, the autonomous reset count is cleared.
The data transmission control unit receives instructions of the ground or an upper computer through a 1553B control bus; in the full-function mode, the satellite computer sends corresponding instructions to the data transmission control unit according to the instructions of the ground or the upper computer to control the data transmission control unit to realize complete functions; the minimum system mode is an emergency state, and the data transmission control unit needs to realize basic functions in the mode.
The memory module is built in the data transmission control unit.
Compared with the prior art, the invention has the beneficial effects that:
1. According to the data transmission control unit storage module, the cold and hot reset identification and the automatic reset count are stored, when the 1553B control bus is abnormal in function, the satellite-borne 1553B control bus failure protection method can automatically control the data transmission control unit to enter a minimum system mode according to the cold and hot reset identification and the automatic reset count, so that the data transmission control unit can realize the most basic function. The satellite-borne 1553B control bus failure protection method is used for intelligently judging that the 1553B control bus fails, automatically entering a minimum system mode, and ensuring that the data transmission control unit can still execute the most basic operation under the condition that the 1553B control bus fails without ground intervention, so that task execution is ensured.
2. The data transmission control unit enters the minimum system mode after being automatically reset for more than a plurality of times, so that the fault that the data transmission control unit can recover under abnormal conditions is filtered, the condition that a 1553B control bus does not really fail and enters the minimum system mode is avoided, and the reliability is improved.
Drawings
FIG. 1 is a schematic diagram of the hardware connection principle of the present invention;
FIG. 2 is a schematic diagram of a data transfer control unit entering a minimum system mode;
FIG. 3 is a flow chart of the minimum system mode operation execution of the data transmission control unit;
Fig. 4 is a flowchart illustrating the standby state operation in the minimum system mode of the ecu.
Detailed Description
The invention is further elucidated below in connection with the accompanying drawings.
Example 1:
a satellite-borne 1553B control bus failure protection method is disclosed with reference to FIG. 1.
In this embodiment, as shown in fig. 1, the failure protection method of the satellite-borne 1553B control bus is implemented by a built-in storage module of the data transmission control unit, after the data transmission control unit is started, the data transmission control unit receives an instruction and sends telemetry through the 1553B control bus, and the 1553B control bus is used for transmitting the instruction of the satellite computer to the data transmission control unit and controlling the data transmission control unit to implement related functions through the instruction. And simultaneously, the 1553B control bus collects remote measurement of the data transmission control unit and transmits the remote measurement to the star computer.
The data transmission control unit is provided with a main control chip, for example, the main control chip can be an 80C32 singlechip, and the data transmission control unit is also provided with an interface chip of a 1553B control bus, for example, the interface chip can be a B65170 chip. Two sets of systems are fixedly stored in the main control chip, namely a full-function mode and a minimum system mode, and in the full-function mode, the data transmission control unit can receive 1553B control bus instructions to realize complete functions. And in the emergency state, the minimum system mode is the basic function which the data transmission control unit needs to realize.
The storage module can adopt a KW064 storage chip, cold and hot reset identification and autonomous reset count are stored in the storage module, the data transmission control unit is internally provided with the storage module, and the satellite-borne 1553B control bus failure protection method can realize the following functions:
When the data transmission control unit is powered off and powered on again, the data transmission control unit is cold started, for example, when the ground sends a data transmission power-off instruction and a data transmission power-on instruction, the data transmission control unit is restarted, the restarting process is the cold start, in the cold start process, the cold and hot reset mark is the cold reset mark, the cold reset mark is a random number, and after the main control chip in the data transmission control unit recognizes the cold reset mark, the data transmission control unit is judged to be cold start, and the data transmission control unit enters a full-function mode.
In the full-function mode, the data transmission control unit executes telemetry interrupt periodically according to the signal of the 1553B control bus, when the 1553B control bus is abnormal in function, the data transmission control unit cannot enter telemetry interrupt, at the moment, the cold and hot reset mark is a hot reset mark, the hot reset mark in the embodiment is a 0×5555 code, when the main control chip recognizes the hot reset mark, the data transmission control unit performs autonomous reset, each autonomous reset is performed, the autonomous reset count in the storage unit is +1, and in the process, if the continuous autonomous reset times are smaller than a set threshold value of 5, the data transmission control unit realizes autonomous reset, and the autonomous reset count is cleared. If the number of continuous autonomous reset times is greater than or equal to a set threshold value 5, the data transmission control unit enters a minimum system mode. As shown in fig. 2.
Therefore, the satellite-borne 1553B control bus failure protection method can intelligently judge that the 1553B control bus fails, automatically enter a minimum system mode, does not need ground intervention, and ensures that the data transmission control unit can still execute the most basic operation under the condition of the 1553B control bus failure. Because the data transmission control unit can enter the minimum system mode after being automatically reset for more than 5 times continuously, the fault that the data transmission control unit can recover under the abnormal condition is filtered, and the condition that the 1553B control bus does not really fail but enters the minimum system mode is avoided.
Example 2:
Referring to fig. 2 to 4, a method for protecting a satellite-borne 1553B control bus from failure is disclosed.
As shown in fig. 2, the method for protecting the satellite-borne 1553B control bus from failure includes: when 1553B control bus is abnormal in function, the data transmission control unit cannot enter telemetry interruption, at this time, the hot and cold reset mark is a hot reset mark, the hot reset mark in the embodiment is a 0×5555 code, when the main control chip recognizes the hot reset mark, the data transmission control unit performs autonomous reset, and each time of autonomous reset, the autonomous reset count in the storage module is +1, in the process, if the number of continuous autonomous reset is smaller than a set threshold value 5, the data transmission control unit realizes autonomous reset, and the autonomous reset count is cleared, and if the number of continuous autonomous reset is larger than or equal to the set threshold value 5, the data transmission control unit enters a minimum system mode.
As shown in fig. 3, when the data transmission control unit enters the minimum system mode, a playback string instruction is executed, where the playback string instruction is an instruction in the minimum system mode, and is an instruction for the data transmission control unit to execute the most basic function, a watchdog is disposed in the data transmission control unit, and after the playback string instruction is executed, the data transmission control unit loops feeding the watchdog and is in a standby state.
Further, the data transmission control unit is further provided with a timer, and the storage unit is further stored with a 20 second count for the data transmission control unit in a standby state to execute the playback string instruction again.
Specifically, in combination with fig. 4, in the minimum system mode, when the data transmission control unit is in a standby state, the timer is interrupted once every 50ms, in the timer interruption process, the main control chip judges the 20 second count, when the timer counts for 20 seconds every time, the 20 second count is +1, if the 20 second count is greater than 400, the data transmission control unit enters a dog bite trap, the data transmission control unit waits for dog bite reset, in the dog bite reset process, when the timer counts for 20 seconds every time, the data transmission control unit autonomously resets once, and performs autonomous reset count +1 every time, when the autonomous reset count is greater than 3, the data transmission control unit enters the minimum system mode again to execute a playback serial instruction, and the 20 second count is cleared, and the autonomous reset count is cleared.
When the data transmission control unit is in the standby state again, the minimum system mode can be entered again according to the flow of fig. 4.
Further, in the storage module, three variables of the cold and hot reset mark, the autonomous reset count and the 20 second count are stored in three parts respectively, each time the three variables are modified when the modification is needed, and when the judgment is needed, the three variables are read in two, so that the accuracy of the three variables of the cold and hot reset mark, the autonomous reset count and the 20 second count is ensured.
In addition, after the data transmission control unit enters the minimum system mode, when the ground transmits a data transmission power-off command and a data transmission power-on command, the data transmission control unit enters a cold start after receiving the commands, and when the data transmission control unit enters the cold start, the autonomous reset count is cleared, so that the situation that the data transmission control unit is corrected and restored to the full-function mode after entering the minimum system mode by mistake is prevented.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
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| US5528749A (en) * | 1994-08-05 | 1996-06-18 | Thomson Consumer Electronics, Inc. | Automatic instrument turn off/on for error correction |
| US6378021B1 (en) * | 1998-02-16 | 2002-04-23 | Hitachi, Ltd. | Switch control method and apparatus in a system having a plurality of processors |
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