CN113945830B

CN113945830B - Method for detecting integrated circuit

Info

Publication number: CN113945830B
Application number: CN202111227774.4A
Authority: CN
Inventors: 余琨; 熊忠应; 叶守银; 叶建明; 吴勇佳
Original assignee: Sino IC Technology Co Ltd
Current assignee: Sino IC Technology Co Ltd
Priority date: 2021-10-21
Filing date: 2021-10-21
Publication date: 2024-04-26
Anticipated expiration: 2041-10-21
Also published as: CN113945830A

Abstract

A method of testing an integrated circuit, the method comprising: performing appearance detection on a plurality of convex test electrodes of a plurality of chip areas on a wafer, and forming a first identification chart based on a test result; determining a test walking diagram of the probe card based on the probe card and the first identification diagram, wherein the probe card corresponds to at least two chip areas when performing probe detection once; forming a second identification graph based on the first identification graph and the test walking graph; and controlling a probe card to perform a probe test on a plurality of bump test electrodes of a plurality of chip areas on the wafer based on the test walking diagram and the second identification diagram, wherein the probe card is controlled not to perform the probe test on the bump test electrodes of the chip areas corresponding to the bad identification pattern in response to the existence of the bad identification pattern in the second identification diagram.

Description

Method for detecting integrated circuit

Technical Field

The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a method for detecting an integrated circuit.

Background

With the increasing demands of modern electronic devices for miniaturization, light weight, high performance, multifunction, low power consumption and low cost, the feature size of chips is continuously reduced, the integration scale is rapidly expanding, the chip packaging technology is continuously innovated, and the bump processing technology (Bump process flow) is also developed. The processing technology of the bump test electrode mainly comprises the processes of sputtering, photoetching, electroplating and the like, and if the processing engineering has problems, various defects such as falling off, infirm length, incompleteness, affected bump verticality, and out-of-range height and the like of the bump test electrode can be caused. The above defects of bump test clicks of a chip area on a wafer may cause damage to probes during probe testing of the chip area.

Disclosure of Invention

Some embodiments of the present disclosure provide a method for detecting an integrated circuit, the method comprising:

Performing appearance detection on a plurality of convex test electrodes of a plurality of chip areas on a wafer, and forming a first identification chart based on a test result;

determining a test walking diagram of the probe card based on the probe card and the first identification diagram, wherein the probe card corresponds to at least two chip areas when performing probe detection once;

forming a second identification graph based on the first identification graph and the test walking graph; and

Based on the test walking diagram and the second identification diagram, controlling a probe card to execute probe test on a plurality of convex test electrodes of a plurality of chip areas on the wafer,

And responding to the second identification pattern, and controlling the probe card to not execute probe test on the convex test electrode of the chip area corresponding to the bad identification pattern.

In some embodiments, the performing appearance inspection on the plurality of bump test electrodes of the plurality of chip regions on the wafer and forming the first identification pattern based on the test result includes:

adopting an appearance detection device to perform appearance detection on each convex test electrode of each chip area;

And marking the chip area corresponding to the bump test electrode with a qualified mark in response to the bump test electrode meeting the standard, and marking the chip area corresponding to the bump test electrode with a defect mark in response to the bump test electrode having a defect.

In some embodiments, the marking the chip area corresponding to the bump test electrode with the defect mark in response to the bump test electrode having the defect includes:

Marking a chip area corresponding to a convex test electrode with a falling defect mark in response to the fact that the convex test electrode has the falling defect; in response to the bump test electrode having a defect, marking a chip area corresponding to the bump test electrode with a defect mark; and in response to the bump test electrode having the overrun defect, marking the chip area corresponding to the bump test electrode with the overrun defect mark.

In some embodiments, the first identification chart includes a positional relationship of the plurality of chip areas and corresponding first identification information of the plurality of chip areas, the probe card includes at least two probe areas, and when the probe card performs probe probing once, the at least two probe areas perform probe probing on the at least two chip areas respectively.

In some embodiments, determining a test walking pattern for the probe card based on the probe card and the first identification pattern includes: determining a test walking diagram of the probe board card based on the position relation of the plurality of chip areas and the number and arrangement mode of the probe board card including upper probe areas, wherein the test walking diagram includes a plurality of probe areas, each probe area is an area detected by the probe board card by executing probe detection once, and each probe area includes at least two chip areas.

In some embodiments, the test walking pattern includes a plurality of probe regions, each probe region performing a probe probing of the probe card for a probed region, each probe region including at least two chip regions,

The forming a second identification graph based on the first identification graph and the test walking graph comprises the following steps:

And marking the chip area with the defect mark with the bad mark, and marking other chip areas belonging to the same detection area with the chip area with the defect mark with the bad mark, wherein for any detection area, the bad mark of the chip area of the detection area forms the bad mark pattern in response to the chip area of the detection area.

In some embodiments, the forming a second identification map based on the first identification map and the test walking map further includes:

The chip area with the qualified mark is marked by the mark,

Wherein, for any detection area, the probe card performs probe testing on the detection area in response to the chip area in the detection area having at least one pass flag.

In some embodiments, wherein the test walking pattern includes a plurality of probe regions, each probe region performing a probe probing of the probe card for a probed region, each probe region including at least two chip regions,

Forming a second identification graph based on the first identification graph and the test walking graph comprises:

And marking the chip area with the overrun defect mark with bad marks, and marking other chip areas belonging to the same detection area with the chip area with the overrun defect mark with bad marks, wherein for any detection area, the bad marks of the chip areas of the detection area form the bad mark pattern in response to the chip area of the detection area.

marking the chip area with qualified mark with mark, marking the chip area with falling defect mark and incomplete defect mark with bad mark,

Compared with the related art, the scheme of the embodiment of the disclosure has at least the following beneficial effects:

detecting the appearance of the raised test electrode of the chip area on the wafer, marking the chip area with defects, determining the probe card to selectively execute probe test on the detection area on the wafer according to the test walking diagram of the probe card, and avoiding probe damage.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:

FIG. 1 is a schematic diagram of a wafer provided in some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of the chip area in FIG. 1;

FIG. 3 is a flow chart of a method of testing an integrated circuit provided in some embodiments of the present disclosure;

FIG. 4 is a flowchart showing the step S310 in FIG. 3;

FIG. 5 is a cross-sectional view of a bump test electrode in some embodiments of the present disclosure, wherein (a) corresponds to a standard compliant bump test electrode and (b), (c), and (d) correspond to a detachment defect, a defect, and an overrun defect, respectively;

FIG. 6 is a schematic diagram of a first identification map provided by some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a probe card provided in some embodiments of the present disclosure;

FIG. 8 is a schematic diagram of a test walking diagram of a probe card provided by some embodiments of the present disclosure;

FIG. 9 is a schematic diagram of a second identification map in some embodiments of the present disclosure;

FIG. 10 is a schematic diagram of a second identification map in some embodiments of the present disclosure;

Fig. 11 is a schematic diagram of an electronic device in some embodiments of the present disclosure.

Detailed Description

For the purpose of promoting an understanding of the principles and advantages of the disclosure, reference will now be made in detail to the drawings, in which it is apparent that the embodiments described are only some, but not all embodiments of the disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

The terminology used in the embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure of embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present disclosure, these should not be limited to these terms. These terms are only used to distinguish one from another. For example, a first may also be referred to as a second, and similarly, a second may also be referred to as a first, without departing from the scope of embodiments of the present disclosure.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a commodity or device comprising such element.

The present disclosure provides a method of testing an integrated circuit, the method comprising the steps of:

The appearance of the convex test electrode of the chip area on the wafer is detected, the chip area with the defects is identified, whether the defects and the defect types exist in each chip area are marked on the first identification chart, and the detection area where the chip area with the specific defects exists is marked on the second identification chart, so that the probe card does not execute probe detection in the detection area, and probe damage is avoided.

Alternative embodiments of the present disclosure are described in detail below with reference to the drawings.

Fig. 1 is a schematic structural diagram of a wafer provided in some embodiments of the present disclosure, and fig. 2 is a schematic structural diagram of a chip area in fig. 1, where, as shown in fig. 1 and 2, a plurality of chip areas 10 are disposed on a wafer 10, and the plurality of chip areas 10 are regularly arranged on the wafer 100. In the present embodiment, the die 100 is a wafer, which is also called a wafer, and the chip area 10 is square, and the die 100 is arranged in a plurality of rows and columns. Those skilled in the art will appreciate that in other embodiments, the wafer 100 may have other shapes, such as rectangular, square, etc., and the chip area 10 may have other shapes, such as rectangular, circular, diamond, etc.

Each chip area is patterned to produce an integrated circuit thereon, such as a chip 11 and raised test electrodes 12 on the upper surface of the chip 11. The bump test electrode 12 is electrically connected with the chip 11 through an electronic wiring manufactured on a wafer, and the bump test electrode 12 can be used as a pin of the chip 11 to be connected with an external circuit, so that signal communication between the chip 11 and the external circuit is realized. In the performance test of the chip, the bump test electrodes 12 may be electrically connected to a test circuit to perform the test of the electrical characteristics of each chip to determine whether the chip 11 meets the standard. The bump test electrodes 12 corresponding to the chip 11 are probed, for example, by probes on a probe card, which are in electrical contact with the bump test electrodes 12.

Fig. 3 is a flowchart of a method for detecting an integrated circuit according to some embodiments of the present disclosure, where, as shown in fig. 3, the method includes at least the following steps:

s310: performing appearance detection on a plurality of convex test electrodes of a plurality of chip areas on a wafer, and forming a first identification chart based on a test result;

S330: determining a test walking diagram of the probe card based on the probe card and the first identification diagram, wherein the probe card corresponds to at least two chip areas when performing probe detection once;

s350: forming a second identification graph based on the first identification graph and the test walking graph; and

S370: and controlling a probe card to execute probe testing on a plurality of convex testing electrodes of a plurality of chip areas on the wafer based on the testing walking diagram and the second identification diagram.

In step S310, the first identification chart may indicate the chip area corresponding to the bump electrode having the appearance defect. Fig. 4 shows a specific flowchart of step S310 in fig. 3, and as shown in fig. 4, step S310 may specifically include the following steps:

S311: and adopting an appearance detection device to detect the appearance of each convex test electrode in each chip area.

The external light detection device is a camera, a light detection device and the like, and can accurately detect the appearance of the bump test electric electrode to determine whether the bump test electrode has appearance defects. The bump test electrode includes, for example, a detachment defect, a defect, an overrun defect, etc., and a cross-sectional view of the bump test electrode in some embodiments of the present disclosure is shown in fig. 5. In fig. 5, (a) shows a bump test electrode conforming to a standard, for example, a hemispherical shape in section, having a predetermined radius and height, for example, 20-30 μm. Since the bump test electrodes are formed on the wafer by deposition, sputtering, photolithography, electroplating, etc., defects may exist during the manufacturing process. (b) (c) and (d) show bump test electrodes with detachment defects, incomplete defects, and overrun defects, respectively. The hemispherical bump test electrode is completely detached from the wafer as shown in (b), belongs to detachment defects, has a missing part as shown in (c), belongs to incomplete defects, and has an overrun defect as shown in (d) due to the fact that the height of the bump test electrode exceeds the standard height due to the fact that excessive materials are deposited.

S313: and marking the chip area corresponding to the bump test electrode with a qualified mark in response to the bump test electrode meeting the standard, and marking the chip area corresponding to the bump test electrode with a defect mark in response to the bump test electrode having a defect.

Specifically, the chip area corresponding to the bump test electrode is marked according to the appearance detection result of the bump test electrode, so that a first identification chart is formed. If the bump test electrode meets the standard, marking the chip area corresponding to the bump test electrode with a qualified mark, for example, marking O; if the bump test electrode has a falling defect, marking a chip area corresponding to the bump test electrode with a falling defect mark, for example, marking A; if the bump test electrode has a defect, marking a chip area corresponding to the bump test electrode with a defect mark, for example, marking B; if the bump test electrode has an overrun defect, the chip area corresponding to the bump test electrode is marked with an overrun defect mark, for example, a mark C.

Fig. 6 is a schematic diagram of a first identification chart provided in some embodiments of the present disclosure, and as shown in fig. 6, the chip areas on the wafer 100 are all marked with first identification information based on the marking rule described above. It will be appreciated by those skilled in the art that the various identifiers O, A, B, C in fig. 6 are for illustration only, and that other indicia that are easily recognized by a computer may be used by those skilled in the art to mark the chip regions as long as it is ensured that the chip regions corresponding to bump test electrodes that meet the appearance criteria are distinguishable from the chip regions corresponding to bump test electrodes that have defects, and that the chip regions corresponding to bump test electrodes that have different defects are distinguishable.

In step S330, the probe card corresponds to two or more chip areas when performing one probe probing. Fig. 7 is a schematic diagram of a probe card according to some embodiments of the present disclosure, and as shown in fig. 7, a probe card 200 includes at least two probe regions 20, where the probe regions 20 are also referred to as probing stations, and two probe regions are illustrated in this embodiment. Each probe region 20 includes therein a plurality of probes 21 extending from the card body in a direction perpendicular to the card body. When probe probing is performed on the wafer 100 using the probe card 200, for each probe probing, each probe region 20 corresponds to one chip region 10, and the probes 21 in the probe regions 20 perform contact probe probing on the bump test electrodes 11 of the corresponding chip region 10.

With the probe card, each time the probe detection is executed, the contact type probe detection of two or more chip areas can be completed, wherein the two or more chip areas can be adjacent or arranged at intervals, and compared with the probe card with only one probe area, the probe efficiency of the chip area on a wafer can be obviously improved.

In step S330, specifically, a test walking chart of the probe card is determined based on the positional relationship of the plurality of chip areas in the first identification chart and the number and arrangement modes of the probe areas included in the probe card. The probe card executes an optimized walking route to finish probe detection of the chip area on the wafer so as to improve detection efficiency.

Fig. 8 is a schematic diagram of a test walking diagram of a probe card provided in some embodiments of the present disclosure. As shown in fig. 8, the test walking chart includes a plurality of probe regions T, each probe region T is a region detected by performing probe probing once for the probe card, that is, a region corresponding to the at least two probe regions 20 on the probe card 200. Each detection region T comprises at least two chip regions 10, which at least two chip regions 10 are, for example, adjacent. In other embodiments, the at least two chip regions 10 may also be spaced apart to avoid cross-talk caused by simultaneous testing of adjacent chip regions.

And the walking route of the detection board card is reasonably designed in the test walking diagram, so that the detection efficiency is improved. For example, the detection area T is detected row by row from top to bottom. In some embodiments, the contact probe detection can be performed one by one according to the numbers 1-56 of the detection areas T in FIG. 8, so as to improve the detection efficiency. In other embodiments, the probe card may also take other walkways, such as interlaced probing, progressive probing, spaced probing, and the like.

In this embodiment, as shown in fig. 8, the detection of all the chip areas on the multi-wafer can be completed without overlapping areas in each detection area T. However, it will be understood by those skilled in the art that in some cases, for example, the number of chip regions in the wafer is not an integer multiple of the number of chip regions corresponding to the probe regions, some of the chip regions may be missed by using a manner that the probe regions do not overlap, and at this time, the probe regions T may be overlapped to ensure that the probe of all the chip regions on the wafer is completed.

In step S350, a second identification chart is formed based on the first identification chart and the test walking chart, where the second identification chart may embody a bad identification pattern, the bump test electrodes in the chip area corresponding to the bad identification pattern may damage the probes of the probe card, and in response to the existence of the bad identification pattern in the second identification chart, in a subsequent operation, the probe card is controlled to not perform a probe test on the bump test electrodes in the chip area corresponding to the bad identification pattern, so as to avoid probe damage of the probe card.

In some embodiments, in the process of forming the second identification map, the chip area with the qualified identification is marked by identification, for example, marked as P, the chip area with the defect identification is marked with poor identification, for example, marked as N, and other chip areas belonging to the same detection area as the chip area with the defect identification are marked with poor identification, for example, marked as N, for any detection area, the poor identification of the chip area of the detection area forms the poor identification pattern in response to the chip area of the detection area being marked with poor identification.

Fig. 9 is a schematic diagram of a second logo in some embodiments of the present disclosure, as shown in connection with fig. 6, 8, 9. The chip area with the qualified mark O is marked with a mark, such as P, the chip area with the defect mark A, B or C is marked with a bad mark, such as N, and the other chip areas which belong to the same detection area T with the chip area with the defect mark A, B or C are marked with bad marks, such as N. For any detection area T, the defective mark N is marked in response to the chip area of the detection area T, and the defective mark of the chip area of the detection area constitutes the defective mark pattern NG.

In this embodiment, the probe card is controlled not to perform probe detection in the detection area T by marking all the chip areas with the defect identifications a, B, and C with the defect identification N, and marking all other chip areas (which may include the chip area with the qualified identification O) in the detection area T with the defect identifications N, so that the detection area T with the defect identifications a, B, and C corresponds to the defect identification pattern NG, thereby avoiding probe damage. In this case, although some chip regions with the qualified mark O are not detected by the probe, in the subsequent process, the chip regions with the qualified mark O may be discarded as bad products, so that for the whole integrated circuit detection, the detection efficiency can be improved, and meanwhile, the probe is prevented from being damaged, so that serious cost is increased.

In step S370, based on the test walking chart and the second identification chart, the probe card is controlled to perform a probe test on a plurality of bump test electrodes of a plurality of chip areas on the wafer, specifically, for any probe area, the probe card performs a probe test on the probe area in response to the chip area in the probe area having at least one pass identification P, and controls not to perform a probe test on the probe area in response to the probe area corresponding to the bad identification pattern NG, so as to avoid probe damage of the probe card.

In some embodiments, the fine classification process may also be performed for chip regions with different types of appearance defect identifications as described above. For the chip area with the falling defect mark A or the incomplete defect mark B, the convex test electrode of the chip area with the overrun defect mark C cannot influence the probe of the probe card, and for the chip area with the overrun defect mark C, the convex test electrode exceeds the standard height, so that the probe of the probe card can be damaged during probe detection.

Therefore, in the process of forming the second identification chart, the chip area with the qualified identification is marked by identification, such as P, the chip area with the detachment defect identification, the incomplete defect identification and the overrun defect identification is marked by bad identification, such as N, and the other chip areas which belong to the same detection area with the overrun defect identification are marked by bad identification, such as N, for any detection area, the bad identification of the chip area of the detection area is marked by bad identification in response to the chip area of the detection area, and the bad identification of the chip area of the detection area forms the bad identification pattern.

Fig. 10 is a schematic diagram of a second logo in some embodiments of the present disclosure, as shown in connection with fig. 6, 8, 10. In the process of forming the second identification graph, the chip area with the qualified identification O is marked by an identification, such as P, the chip areas with the detachment defect identification A, the incomplete defect identification B and the overrun defect identification C are marked by a bad identification, such as N, and other chip areas which belong to the same detection area T with the overrun defect identification C are marked by a bad identification, such as N, for any detection area, the bad identification of the chip area of the detection area T forms the bad identification pattern NG in response to the chip area of the detection area T.

In this embodiment, the chip areas with the detachment defect mark a, the incomplete defect mark B and the overrun defect mark C are marked with the bad mark N, and the other chip areas (which may include the chip area with the qualified mark O) in the detection area T where the chip area with the overrun defect mark C is located are marked with the bad mark N, so that the detection area T where the chip area with the overrun defect mark C is located corresponds to the bad mark pattern NG, and the probe card is controlled to not perform probe detection in the detection area T, thereby avoiding probe damage. In this case, although some chip regions with the pass mark O are not detected by the probe, in the subsequent process, the chip regions with the pass mark O may be discarded as bad products, so that the inspection efficiency of the integrated circuit is improved, and meanwhile, the probe is prevented from being damaged, which causes serious cost increase.

In the foregoing embodiments, the probe card has two probe regions arranged in a horizontal manner, and in other embodiments, the number of probe regions of the probe card may be more, for example, 3, 4,5, etc., and the probe regions may also be arranged in a vertical manner, or in an array of multiple rows and multiple columns, which will not be described herein.

The disclosed embodiments provide a non-transitory computer storage medium storing computer executable instructions that perform the method steps described in the embodiments above.

The present disclosure provides a computer program product comprising a computer program which, when executed by a processor, implements the method as described in the above embodiments.

As shown in fig. 11, the present embodiment provides an electronic apparatus including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to enable the at least one processor to perform the method steps described in the embodiments above.

Referring now to fig. 11, a schematic diagram of an electronic device suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 11 is merely an example, and should not impose any limitations on the functionality and scope of use of embodiments of the present disclosure.

As shown in fig. 11, the electronic device may include a processing means (e.g., a central processor, a graphics processor, etc.) 1101 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1102 or a program loaded from a storage means 1108 into a Random Access Memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the electronic device are also stored. The processing device 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. An input/output (I/O) interface 1105 is also connected to bus 1104.

In general, the following devices may be connected to the I/O interface 1105: input devices 1106 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 11011 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 1108, including for example, magnetic tape, hard disk, etc.; and a communication device 1109. The communication means 1109 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. While fig. 11 shows an electronic device having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via communications device 1109, or from storage device 1108, or from ROM 1102. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 1101.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Finally, it should be noted that: in the present specification, each embodiment is described by way of example, and each embodiment is mainly described in a different manner from other embodiments, so that identical and similar parts between the embodiments are all mutually referred to. The system or the device disclosed in the embodiments are relatively simple in description, and the relevant points refer to the description of the method section because the system or the device corresponds to the method disclosed in the embodiments.

The above embodiments are merely for illustrating the technical solution of the present disclosure, and are not limiting thereof; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A method of testing an integrated circuit, the method comprising:

2. The inspection method of claim 1, wherein the performing appearance inspection on the plurality of bump test electrodes of the plurality of chip areas on the wafer and forming the first identification map based on the test result comprises:

3. The inspection method of claim 2, wherein the marking the chip area corresponding to the bump test electrode with a defect mark in response to the bump test electrode having a defect comprises:

4. The detection method according to any one of claims 1 to 3, wherein the first identification map includes positional relationships of the plurality of chip regions and corresponding first identification information of the plurality of chip regions, the probe card includes at least two probe regions, and when the probe card performs probe probing once, the at least two probe regions perform probe probing on the at least two chip regions, respectively.

5. The inspection method of claim 4, wherein determining a test walking pattern of the probe card based on the probe card and the first identification pattern comprises: determining a test walking diagram of the probe board card based on the position relation of the plurality of chip areas and the number and arrangement modes of the probe areas on the probe board card, wherein the test walking diagram comprises a plurality of detection areas, each detection area is an area detected by executing one-time probe detection for the probe board card, and each detection area comprises at least two chip areas.

6. The inspection method of claim 2, wherein the test walking pattern includes a plurality of inspection areas, each inspection area including at least two chip areas, each inspection area performing one inspection of the probe card,

7. The detection method of claim 6, wherein the forming a second identification map based on the first identification map and the test walking map further comprises:

The chip area with the qualified mark is marked by the mark,

8. The inspection method of claim 3, wherein the test walking pattern comprises a plurality of inspection areas, each inspection area comprising at least two chip areas, each inspection area being an area where the probe card performs one probe inspection,

9. The detection method of claim 8, wherein the forming a second identification map based on the first identification map and the test walking map further comprises: