CN113937149A - Termination structure of semiconductor power device and manufacturing method thereof - Google Patents
Termination structure of semiconductor power device and manufacturing method thereof Download PDFInfo
- Publication number
- CN113937149A CN113937149A CN202010670054.4A CN202010670054A CN113937149A CN 113937149 A CN113937149 A CN 113937149A CN 202010670054 A CN202010670054 A CN 202010670054A CN 113937149 A CN113937149 A CN 113937149A
- Authority
- CN
- China
- Prior art keywords
- epitaxial layer
- type epitaxial
- region
- semiconductor power
- power device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 230000001413 cellular effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件的终端结构及其制造方法，包括：n型外延层；凹陷在所述n型外延层内的至少一个终端区沟槽，所述终端区沟槽环绕包围半导体功率器件的元胞区；位于所述n型外延层内且位于所述终端区沟槽底部的p型掺杂区，所述p型掺杂区的几何中心位于所述终端区沟槽的几何中心远离所述元胞区的一侧。本发明可以提高半导体功率器件的击穿电压。
The invention belongs to the technical field of semiconductor power devices, and specifically discloses a terminal structure of a semiconductor power device and a manufacturing method thereof, comprising: an n-type epitaxial layer; at least one terminal area trench recessed in the n-type epitaxial layer, the The termination region trench surrounds the cell region surrounding the semiconductor power device; the p-type doped region located in the n-type epitaxial layer and located at the bottom of the termination region trench, the geometric center of the p-type doped region is located at The geometric center of the trench in the terminal region is away from one side of the cell region. The present invention can improve the breakdown voltage of the semiconductor power device.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a terminal structure of a semiconductor power device and a manufacturing method thereof.
Background
The semiconductor power device comprises a cell area and a terminal area, wherein the terminal area surrounds the cell area, and the design of the cell area determines the characteristics of the semiconductor power device, such as on-resistance, capacitance, breakdown voltage and the like, but is limited by the effectiveness and the area of the protection design of the terminal area. To ensure the reliability of the semiconductor power device, the voltage breakdown point should fall in the cell region, not in the termination region. In order to reduce the characteristic on-resistance of the semiconductor power device in the prior art, the doping concentration of the n-type epitaxial layer needs to be increased, so that the terminal region is difficult to be depleted in the transverse direction, the withstand voltage of the terminal region is lower than that of the cell region, and the withstand voltage of the semiconductor power device is affected.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a termination structure of a semiconductor power device and a method for manufacturing the same, so as to solve the problem that the withstand voltage of the semiconductor power device in the prior art is difficult to adjust.
To achieve the above object, the present invention provides a terminal structure of a semiconductor power device, including:
an n-type epitaxial layer;
at least one termination region trench recessed within the n-type epitaxial layer, the termination region trench surrounding a cell region of a semiconductor power device;
and the geometric center of the p-type doped region is positioned on one side, far away from the cellular region, of the geometric center of the terminal region groove.
Optionally, the bottom of the termination region trench is lower than the top of the p-type doped region.
Optionally, the device further includes a field oxide layer and a conductive polysilicon layer located in the termination region trench.
Optionally, the conductive polysilicon in at least one of the termination region trenches is externally connected to a source voltage.
Optionally, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer, and the doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different.
Optionally, the doping concentration of the second n-type epitaxial layer is greater than the doping concentration of the first n-type epitaxial layer.
Optionally, the p-type doped region is located in the first n-type epitaxial layer.
Optionally, the p-type doped region is located in the first n-type epitaxial layer and extends upward into the second n-type epitaxial layer.
The manufacturing method of the terminal structure of the semiconductor power device comprises the following steps:
forming at least one p-type injection region in the first part of the n-type epitaxial layer, wherein the p-type injection region surrounds a cellular region of the semiconductor power device;
forming an n-type epitaxial layer second division part on the n-type epitaxial layer first division part, wherein the n-type epitaxial layer first division part and the n-type epitaxial layer second division part form an n-type epitaxial layer of the semiconductor power device;
and forming a terminal area groove sunken in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal area groove corresponds to the p-type injection area one by one, and the geometric center of the p-type injection area is positioned on one side of the geometric center of the terminal area groove far away from the cellular area.
Optionally, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer;
the first part of the n-type epitaxial layer is the first n-type epitaxial layer, the second part of the n-type epitaxial layer is the second n-type epitaxial layer, and the doping concentration of the second part of the n-type epitaxial layer is greater than that of the first part of the n-type epitaxial layer.
According to the terminal structure of the semiconductor power device, the p-type doped region is positioned at the bottom of the terminal region groove, and the geometric center of the p-type doped region is positioned on one side, away from the cellular region, of the geometric center of the terminal region groove, so that the breakdown voltage of the terminal region of the semiconductor power device can be improved, and further the withstand voltage and the reliability of the semiconductor power device are improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present invention;
fig. 2 to fig. 3 are schematic cross-sectional structures of main structures in a manufacturing process of one embodiment of a manufacturing method of a semiconductor power device provided by the present invention.
Detailed Description
The technical solution of the present invention will be fully described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a termination structure of a semiconductor power device provided by the present invention, and as shown in fig. 1, the termination structure of the semiconductor power device provided by the present invention includes an n-type epitaxial layer 20, the material of the n-type epitaxial layer 20 is usually silicon, and the n-type epitaxial layer 20 is usually formed on an n-type silicon substrate (not shown in fig. 1). At least one termination trench, only three termination trenches are shown by way of example in the embodiment of fig. 1, recessed within the n-type epitaxial layer 20, in which termination trenches field oxide 22 and conductive polysilicon 23 are formed, optionally with at least one conductive polysilicon 23 externally connected to the source voltage. The semiconductor power device includes a cell region and a terminal region, the terminal region surrounds the cell region, and the terminal region structure of the terminal region is only exemplarily shown in the embodiment of the present invention.
And the p-type doped region 21 is positioned in the n-type epitaxial layer 20 and at the bottom of the terminal region trench, and the geometric center of the p-type doped region 21 is positioned on one side of the geometric center of the terminal region trench, which is far away from the cell region. In the terminal region of the semiconductor power device, the highest point of voltage is located on one side of the terminal region groove far away from the cellular region, and the geometric center of the p-type doped region 21 is arranged on one side of the geometric center of the terminal region groove far away from the cellular region, so that the withstand voltage of the terminal region can be improved, and further the withstand voltage and the reliability of the semiconductor power device can be improved.
Optionally, the bottom of the termination region trench may be higher than the top of the p-type doped region 21, that is, the bottom of the termination region trench extends into the p-type doped region 21 (as shown in fig. 1), so that under the condition that the depth of the termination region trench is kept unchanged, the distance between the p-type doped region and the bottom of the n-type epitaxial layer 20 may be increased, and the withstand voltage of the semiconductor power device may be further improved.
Optionally, in the semiconductor power device provided by the present invention, the n-type epitaxial layer 20 may include a first n-type epitaxial layer and a second n-type epitaxial layer (not shown in the figure) located above the first n-type epitaxial layer, and the doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different. Optionally, the doping concentration of the second n-type epitaxial layer is greater than that of the first n-type epitaxial layer, so that the first n-type epitaxial layer with low doping concentration is used for improving the withstand voltage of the semiconductor power device, and the second n-type epitaxial layer with high doping concentration is used for reducing the on-resistance of the semiconductor power device.
Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the bottom of the termination region trench may be located in the second n-type epitaxial layer, or the bottom of the termination region trench may be located in the first n-type epitaxial layer (not shown in the figure), which is not limited in the embodiment of the present invention.
Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the p-type doped region may be located in the first n-type epitaxial layer, or the p-type doped region may be located in the first n-type epitaxial layer and extend upward into the second n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present invention.
Fig. 2 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a termination structure of a semiconductor power device provided by the present invention, first, as shown in fig. 2, an n-type epitaxial layer first sub-portion 31 is formed on an n-type substrate 30, then ion implantation is performed to form at least one p-type implantation region 41 in the n-type epitaxial layer first sub-portion 31, the p-type implantation region 41 should surround a cell region (not shown in fig. 2) of the semiconductor power device, and only three p-type implantation regions 41 are exemplarily shown in fig. 2.
Next, as shown in fig. 3, an n-type epitaxial layer second division 32 is formed on the n-type epitaxial layer first division 31, and the n-type epitaxial layer first division 31 and the n-type epitaxial layer second division 32 form an n-type epitaxial layer of the termination structure of the semiconductor power device of the present invention. Preferably, the doping concentration of the n-type epitaxial layer second subsection 32 is greater than the doping concentration of the n-type epitaxial layer first subsection 31, so that the n-type epitaxial layer first subsection 31 is used for improving the withstand voltage of the semiconductor power device, and the n-type epitaxial layer second subsection 32 is used for reducing the on-resistance of the semiconductor power device. And then, forming a terminal region groove 42 recessed in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal region groove 42 corresponds to the p-type injection region 41 one by one, and the geometric center of the p-type injection region 41 is positioned on one side, away from the cellular region, of the geometric center of the terminal region groove 42.
Optionally, in the terminal structure of the semiconductor power device according to the embodiment of the present invention, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer; the first part of the n-type epitaxial layer is a first n-type epitaxial layer, and the second part of the n-type epitaxial layer is a second n-type epitaxial layer.
Finally, the terminal structure of the semiconductor power device of the present invention can be manufactured by a conventional process, and it should be noted that, by controlling the implantation concentration and depth of the p-type implantation region 41, the position of the p-type doped region formed after the diffusion of the p-type implantation region 41 in the subsequent process can be controlled, for example, the p-type doped region may be only located in the first n-type epitaxial layer partition 31, or the p-type doped region may also be located in the first n-type epitaxial layer partition 31 and diffused into the second n-type epitaxial layer partition 32. Meanwhile, through the etching depth of the terminal region trench 42, the top of the p-type doped region formed after the diffusion of the p-type injection region 41 can be higher than the bottom of the terminal region trench, which is equivalent to the fact that the bottom of the terminal region trench extends into the p-type doped region; the top of the p-type doped region formed by the p-type implanted region 41 after diffusion may also be made lower than the bottom of the termination trench.
The terminal structure of the semiconductor power device can be suitable for semiconductor power devices with different grid structures, for example, the grid structure and the source polycrystalline silicon are in an up-and-down position relationship, or the grid structure and the source polycrystalline silicon are in a left-and-right position relationship, meanwhile, in order to match the grid structure in the cell region groove, a grid structure corresponding to the grid structure can be formed in the terminal region groove, and the grid structure in the terminal region groove is arranged in a floating mode or externally connected with source voltage.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A termination structure for a semiconductor power device, comprising:
an n-type epitaxial layer;
at least one termination region trench recessed within the n-type epitaxial layer, the termination region trench surrounding a cell region of a semiconductor power device;
and the geometric center of the p-type doped region is positioned on one side, far away from the cellular region, of the geometric center of the terminal region groove.
2. The termination structure of claim 1, wherein a bottom of the termination region trench is lower than a top of the p-type doped region.
3. The termination structure of a semiconductor power device according to claim 1, further comprising a field oxide layer and conductive polysilicon located within said termination region trench.
4. The termination structure of claim 3, wherein at least one of said termination region trenches has conductive polysilicon therein which is external to a source voltage.
5. The termination structure of a semiconductor power device according to claim 1, wherein the n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer located over the first n-type epitaxial layer, the first n-type epitaxial layer and the second n-type epitaxial layer having different doping concentrations.
6. The termination structure of a semiconductor power device according to claim 5, wherein the second n-type epitaxial layer has a doping concentration greater than the doping concentration of the first n-type epitaxial layer.
7. The termination structure of a semiconductor power device according to claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer.
8. The termination structure of a semiconductor power device according to claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer and extends up into the second n-type epitaxial layer.
9. A method of fabricating a termination structure for a semiconductor power device, comprising:
forming at least one p-type injection region in the first part of the n-type epitaxial layer, wherein the p-type injection region surrounds a cellular region of the semiconductor power device;
forming an n-type epitaxial layer second division part on the n-type epitaxial layer first division part, wherein the n-type epitaxial layer first division part and the n-type epitaxial layer second division part form an n-type epitaxial layer of the semiconductor power device;
and forming a terminal area groove sunken in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal area groove corresponds to the p-type injection area one by one, and the geometric center of the p-type injection area is positioned on one side, far away from the cellular area, of the geometric center of the terminal area groove.
10. The method of fabricating a termination structure for a semiconductor power device according to claim 9, wherein said n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer over said first n-type epitaxial layer;
the first part of the n-type epitaxial layer is the first n-type epitaxial layer, the second part of the n-type epitaxial layer is the second n-type epitaxial layer, and the doping concentration of the second part of the n-type epitaxial layer is greater than that of the first part of the n-type epitaxial layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010670054.4A CN113937149A (en) | 2020-07-13 | 2020-07-13 | Termination structure of semiconductor power device and manufacturing method thereof |
| PCT/CN2020/117287 WO2022011834A1 (en) | 2020-07-13 | 2020-09-24 | Terminal structure for semiconductor power device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010670054.4A CN113937149A (en) | 2020-07-13 | 2020-07-13 | Termination structure of semiconductor power device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113937149A true CN113937149A (en) | 2022-01-14 |
Family
ID=79273454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010670054.4A Pending CN113937149A (en) | 2020-07-13 | 2020-07-13 | Termination structure of semiconductor power device and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113937149A (en) |
| WO (1) | WO2022011834A1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080042172A1 (en) * | 2006-08-03 | 2008-02-21 | Infineon Technologies Austria Ag | Semiconductor component having a space saving edge structure |
| CN102947937A (en) * | 2010-06-11 | 2013-02-27 | 丰田自动车株式会社 | Semiconductor device and method for fabricating semiconductor device |
| CN104617147A (en) * | 2015-01-23 | 2015-05-13 | 无锡同方微电子有限公司 | Trench MOSFET structure and manufacturing method thereof |
| US20150270334A1 (en) * | 2014-03-24 | 2015-09-24 | Sanken Electric Co., Ltd. | Semiconductor device |
| CN106024863A (en) * | 2016-06-27 | 2016-10-12 | 电子科技大学 | High-voltage power device terminal structure |
| JP2017038016A (en) * | 2015-08-12 | 2017-02-16 | サンケン電気株式会社 | Semiconductor device |
| JP2017069464A (en) * | 2015-09-30 | 2017-04-06 | サンケン電気株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6037499B2 (en) * | 2011-06-08 | 2016-12-07 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP2016189369A (en) * | 2015-03-30 | 2016-11-04 | サンケン電気株式会社 | Semiconductor device |
-
2020
- 2020-07-13 CN CN202010670054.4A patent/CN113937149A/en active Pending
- 2020-09-24 WO PCT/CN2020/117287 patent/WO2022011834A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080042172A1 (en) * | 2006-08-03 | 2008-02-21 | Infineon Technologies Austria Ag | Semiconductor component having a space saving edge structure |
| CN102947937A (en) * | 2010-06-11 | 2013-02-27 | 丰田自动车株式会社 | Semiconductor device and method for fabricating semiconductor device |
| US20150270334A1 (en) * | 2014-03-24 | 2015-09-24 | Sanken Electric Co., Ltd. | Semiconductor device |
| CN104617147A (en) * | 2015-01-23 | 2015-05-13 | 无锡同方微电子有限公司 | Trench MOSFET structure and manufacturing method thereof |
| JP2017038016A (en) * | 2015-08-12 | 2017-02-16 | サンケン電気株式会社 | Semiconductor device |
| JP2017069464A (en) * | 2015-09-30 | 2017-04-06 | サンケン電気株式会社 | Semiconductor device |
| CN106024863A (en) * | 2016-06-27 | 2016-10-12 | 电子科技大学 | High-voltage power device terminal structure |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022011834A1 (en) | 2022-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5089284B2 (en) | Semiconductor device having a space-saving edge structure | |
| CN103730372B (en) | A kind of superjunction manufacture method improving device withstand voltage | |
| US20130334598A1 (en) | Semiconductor device and method for manufacturing same | |
| KR101955055B1 (en) | Power semiconductor device and method of fabricating the same | |
| KR20020086726A (en) | Method of forming a trench dmos having reduced threshold voltage | |
| JP2006510198A (en) | Trench MOSFET with implanted drain drift region and process for manufacturing the same | |
| CN103094324B (en) | Trench-type insulated gate bipolar transistor and preparation method thereof | |
| CN105590844B (en) | The manufacturing method of super-junction structure deep trench | |
| CN210110783U (en) | Integrated high-performance LDMOS structure | |
| CN106298479B (en) | A junction terminal extension structure of a power device and a manufacturing method thereof | |
| CN104009087B (en) | Electrostatic shielding effect transistor and design method thereof | |
| CN113937167B (en) | VDMOS device and its manufacturing method | |
| CN103681817B (en) | IGBT device and manufacturing method thereof | |
| TW201314905A (en) | Method for manufacturing laterally diffused metal oxide semiconductor device | |
| CN114203824A (en) | Super junction power semiconductor device and manufacturing method thereof | |
| CN113437142A (en) | Trench type IGBT structure and manufacturing method thereof | |
| CN110416079A (en) | Manufacturing method of trench gate IGBT chip | |
| CN102005472B (en) | Manufacturing method of power semiconductor device | |
| CN113299750A (en) | Semiconductor power device | |
| CN117373914A (en) | Transistor device and manufacturing method thereof, semiconductor integrated circuit and manufacturing method thereof | |
| CN113629152B (en) | JFET device and manufacturing method thereof | |
| CN113937149A (en) | Termination structure of semiconductor power device and manufacturing method thereof | |
| CN104900703A (en) | Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof | |
| CN113937150B (en) | Method for manufacturing semiconductor power device | |
| CN114823532A (en) | Manufacturing method of super junction device, super junction device, chip and circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220114 |
|
| RJ01 | Rejection of invention patent application after publication |