CN113934668B - Circuit structure for download and debug control of multi-FPGA chip circuit system - Google Patents
Circuit structure for download and debug control of multi-FPGA chip circuit system Download PDFInfo
- Publication number
- CN113934668B CN113934668B CN202111388712.1A CN202111388712A CN113934668B CN 113934668 B CN113934668 B CN 113934668B CN 202111388712 A CN202111388712 A CN 202111388712A CN 113934668 B CN113934668 B CN 113934668B
- Authority
- CN
- China
- Prior art keywords
- usb
- circuit
- chip
- resistor
- inverting buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000012356 Product development Methods 0.000 description 2
- 241000218691 Cupressaceae Species 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
本发明涉及一种针对多FPGA芯片电路系统实现下载调试控制的电路结构，包括USB Hub电路、USB转JTAG模块、USB Mux芯片、滑动开关、反相缓冲器芯片、电阻器和USB接口，USB接口的输出端与滑动开关和USB Mux芯片相连，USB Mux芯片的输出端与USB Hub电路相连，USB Hub电路的输出端与多个USB转JTAG模块相连，滑动开关还与电阻器和外部的VBUS电压相连，电阻器的一端与反相缓冲器芯片的输入端相连，另一端接地，反相缓冲器芯片的输出端分别与USB Mux芯片和外部待调试目标FPGA电路系统相连。采用了本发明的针对多FPGA芯片电路系统实现下载调试控制的电路结构，实现整个系统JTAG调试电路的可靠连接，并保证连接速率最大化，不需要额外设计的调试接口。
The present invention relates to a circuit structure for realizing download debugging control for a multi-FPGA chip circuit system, comprising a USB Hub circuit, a USB to JTAG module, a USB Mux chip, a slide switch, an inverting buffer chip, a resistor and a USB interface, wherein the output end of the USB interface is connected to the slide switch and the USB Mux chip, the output end of the USB Mux chip is connected to the USB Hub circuit, the output end of the USB Hub circuit is connected to multiple USB to JTAG modules, the slide switch is also connected to the resistor and an external VBUS voltage, one end of the resistor is connected to the input end of the inverting buffer chip, and the other end is grounded, and the output end of the inverting buffer chip is respectively connected to the USB Mux chip and an external target FPGA circuit system to be debugged. The circuit structure for realizing download debugging control for a multi-FPGA chip circuit system of the present invention is adopted to realize reliable connection of the JTAG debugging circuit of the entire system, and to ensure that the connection rate is maximized, without the need for an additionally designed debugging interface.
Description
技术领域Technical Field
本发明涉及可编程逻辑器件开发领域，尤其涉及多FPGA芯片系统的下载调试领域，具体是指一种针对多FPGA芯片电路系统实现下载调试控制的电路结构。The present invention relates to the field of programmable logic device development, and in particular to the field of download and debugging of a multi-FPGA chip system, and specifically refers to a circuit structure for implementing download and debugging control for a multi-FPGA chip circuit system.
背景技术Background Art
在可编程逻辑器件开发过程中，经常要使用到JTAG接口对FPGA芯片进行配置或者对逻辑进行调试。对于含有较多数量FPGA芯片的系统或产品，传统的做法是采用串行链式JTAG或者并联式JTAG电路作为调试接口电路，如附图1与附图2所示。然而，串行链式或并联式JTAG电路有如下缺点：In the process of developing programmable logic devices, the JTAG interface is often used to configure the FPGA chip or debug the logic. For systems or products containing a large number of FPGA chips, the traditional approach is to use a serial chain JTAG or parallel JTAG circuit as the debugging interface circuit, as shown in Figures 1 and 2. However, the serial chain or parallel JTAG circuit has the following disadvantages:
1、对于串行链式JTAG电路，当FPGA芯片数量过多的时候，TDI至TDO时延加大，导致JTAG接口速率快速降低。这时，对于容量比较大的高端FPGA芯片而言，其配置时长将变得不可接受，极大的增加了调试成本。1. For the serial chain JTAG circuit, when there are too many FPGA chips, the TDI to TDO delay increases, causing the JTAG interface rate to drop rapidly. At this time, for high-end FPGA chips with relatively large capacity, the configuration time will become unacceptable, greatly increasing the debugging cost.
2、对于并联式JTAG电路，当FPGA芯片数量过多的时候，一方面要考虑JTAG HOST的驱动能力，另一方面要考虑分支走线导致的信号反射引起信号完整性问题。这对电路与PCB设计有较高要求，在多板卡系统中，通常难以兼顾，严重时会引起电路故障，无法使用。2. For parallel JTAG circuits, when there are too many FPGA chips, on the one hand, the driving capability of the JTAG HOST must be considered, and on the other hand, the signal integrity problem caused by the signal reflection caused by the branch wiring must be considered. This places high demands on circuit and PCB design. In a multi-board system, it is usually difficult to take both into account. In serious cases, it will cause circuit failure and unusable.
发明内容Summary of the invention
本发明的目的是克服了上述现有技术的缺点，提供了一种满足可靠性高、速率高、耗时低的针对多FPGA芯片电路系统实现下载调试控制的电路结构。The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a circuit structure that meets the requirements of high reliability, high speed and low time consumption for implementing download and debug control for a multi-FPGA chip circuit system.
为了实现上述目的，本发明的针对多FPGA芯片电路系统实现下载调试控制的电路结构如下：In order to achieve the above-mentioned purpose, the circuit structure of the present invention for implementing download and debug control for a multi-FPGA chip circuit system is as follows:
该针对多FPGA芯片电路系统实现下载调试控制的电路结构，其主要特点是，所述的电路结构包括USB Hub电路、USB转JTAG模块、USB Mux芯片、滑动开关、反相缓冲器芯片、电阻器和USB接口，所述的USB接口的输出端与滑动开关和USB Mux芯片相连，所述的USBMux芯片的输出端与USB Hub电路相连，所述的USB Hub电路的输出端与多个USB转JTAG模块相连，所述的滑动开关还与电阻器和外部的VBUS电压相连，所述的电阻器的一端与反相缓冲器芯片的输入端相连，另一端接地，所述的反相缓冲器芯片的输出端分别与USB Mux芯片和外部待调试目标FPGA电路系统相连；The circuit structure for realizing download debugging control for a multi-FPGA chip circuit system has the following main features: the circuit structure includes a USB Hub circuit, a USB to JTAG module, a USB Mux chip, a slide switch, an inverting buffer chip, a resistor and a USB interface; the output end of the USB interface is connected to the slide switch and the USB Mux chip; the output end of the USB Mux chip is connected to the USB Hub circuit; the output end of the USB Hub circuit is connected to multiple USB to JTAG modules; the slide switch is also connected to a resistor and an external VBUS voltage; one end of the resistor is connected to the input end of the inverting buffer chip and the other end is grounded; the output end of the inverting buffer chip is respectively connected to the USB Mux chip and an external target FPGA circuit system to be debugged;
所述的电路结构通过滑动开关来选择VBUS电压或USB信号，所述的USB HUB电路用于连接不同的USB转JTAG模块，所述的USB转JTAG模块用于配合上位机软件进行FPGA芯片的下载与调试；所述的USB MUX芯片用于切换USB信号，所述的滑动开关用于切换连接电路的连接通路，所述的电阻器用于分压至合适电压值，并驱动反相缓冲器芯片产生控制信号。The circuit structure selects VBUS voltage or USB signal through a sliding switch, the USB HUB circuit is used to connect different USB to JTAG modules, and the USB to JTAG module is used to cooperate with the host computer software to download and debug the FPGA chip; the USB MUX chip is used to switch the USB signal, the sliding switch is used to switch the connection path of the connection circuit, and the resistor is used to divide the voltage to a suitable voltage value and drive the inverting buffer chip to generate a control signal.
较佳地，所述的电阻器包括第一电阻和第二电阻，所述的第一电阻的一端与滑动开关相连，另一端与反相缓冲器芯片的输入端相连，所述的第二电阻的一端与反相缓冲器芯片的输入端相连，另一端接地。Preferably, the resistor includes a first resistor and a second resistor, one end of the first resistor is connected to the sliding switch, and the other end is connected to the input end of the inverting buffer chip, and one end of the second resistor is connected to the input end of the inverting buffer chip, and the other end is grounded.
较佳地，所述的USB Hub电路包括多个USB下行端口，每个USB下行端口均与USB转JTAG模块相连接。Preferably, the USB Hub circuit includes a plurality of USB downstream ports, and each USB downstream port is connected to a USB to JTAG module.
较佳地，所述的拨动滑动开关，使USB接口上的VBUS信号通过电阻器的两个分压电阻接地，所述的电路结构通过控制USB Mux芯片来联通USB接口与USB Hub电路。Preferably, the toggle slide switch allows the VBUS signal on the USB interface to be grounded through two voltage-dividing resistors of the resistor, and the circuit structure connects the USB interface with the USB Hub circuit by controlling the USB Mux chip.
采用了本发明的针对多FPGA芯片电路系统实现下载调试控制的电路结构，通过适当设置USB Hub电路下行端口数量，可在大规模数量FPGA芯片系统中，通过单一USB接口，实现整个系统JTAG调试电路的可靠连接，并保证连接速率最大化。同时电路应用于整机产品时，可使该调试USB接口与普通USB端口复用，不需要额外设计的调试接口。The circuit structure for realizing download debugging control for a multi-FPGA chip circuit system of the present invention is adopted. By appropriately setting the number of downstream ports of the USB Hub circuit, a reliable connection of the JTAG debugging circuit of the entire system can be realized through a single USB interface in a large number of FPGA chip systems, and the connection rate can be maximized. At the same time, when the circuit is applied to a complete product, the debugging USB interface can be reused with a common USB port, and no additional debugging interface needs to be designed.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为现有技术的串行链式JTAG电路示意图。FIG. 1 is a schematic diagram of a serial chain JTAG circuit in the prior art.
图2为现有技术的并联式JTAG电路示意图。FIG. 2 is a schematic diagram of a parallel JTAG circuit in the prior art.
图3为本发明的针对多FPGA芯片电路系统实现下载调试控制的电路结构的电路框图。FIG3 is a circuit block diagram of a circuit structure for implementing download and debug control for a multi-FPGA chip circuit system according to the present invention.
具体实施方式DETAILED DESCRIPTION
为了能够更清楚地描述本发明的技术内容，下面结合具体实施例来进行进一步的描述。In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.
本发明的该针对多FPGA芯片电路系统实现下载调试控制的电路结构，其中包括USB Hub电路、USB转JTAG模块、USB Mux芯片、滑动开关、反相缓冲器芯片、电阻器和USB接口，所述的USB接口的输出端与滑动开关和USB Mux芯片相连，所述的USB Mux芯片的输出端与USB Hub电路相连，所述的USB Hub电路的输出端与多个USB转JTAG模块相连，所述的滑动开关还与电阻器和外部的VBUS电压相连，所述的电阻器的一端与反相缓冲器芯片的输入端相连，另一端接地，所述的反相缓冲器芯片的输出端分别与USB Mux芯片和外部待调试目标FPGA电路系统相连；The circuit structure for realizing download debugging control for a multi-FPGA chip circuit system of the present invention includes a USB Hub circuit, a USB to JTAG module, a USB Mux chip, a slide switch, an inverting buffer chip, a resistor and a USB interface, wherein the output end of the USB interface is connected to the slide switch and the USB Mux chip, the output end of the USB Mux chip is connected to the USB Hub circuit, the output end of the USB Hub circuit is connected to multiple USB to JTAG modules, the slide switch is also connected to the resistor and an external VBUS voltage, one end of the resistor is connected to the input end of the inverting buffer chip, and the other end is grounded, and the output end of the inverting buffer chip is respectively connected to the USB Mux chip and an external target FPGA circuit system to be debugged;
所述的电路结构通过滑动开关来选择VBUS电压或USB信号，所述的USB HUB电路用于连接不同的USB转JTAG模块，所述的USB转JTAG模块用于配合上位机软件进行FPGA芯片的下载与调试；所述的USB MUX芯片用于切换USB信号，所述的滑动开关用于切换连接电路的连接通路，所述的电阻器用于分压至合适电压值，并驱动反相缓冲器芯片产生控制信号。The circuit structure selects VBUS voltage or USB signal through a sliding switch, the USB HUB circuit is used to connect different USB to JTAG modules, and the USB to JTAG module is used to cooperate with the host computer software to download and debug the FPGA chip; the USB MUX chip is used to switch the USB signal, the sliding switch is used to switch the connection path of the connection circuit, and the resistor is used to divide the voltage to a suitable voltage value and drive the inverting buffer chip to generate a control signal.
作为本发明的优选实施方式，所述的电阻器包括第一电阻和第二电阻，所述的第一电阻的一端与滑动开关相连，另一端与反相缓冲器芯片的输入端相连，所述的第二电阻的一端与反相缓冲器芯片的输入端相连，另一端接地。As a preferred embodiment of the present invention, the resistor includes a first resistor and a second resistor, one end of the first resistor is connected to the sliding switch, and the other end is connected to the input end of the inverting buffer chip, one end of the second resistor is connected to the input end of the inverting buffer chip, and the other end is grounded.
作为本发明的优选实施方式，所述的USB Hub电路包括多个USB下行端口，每个USB下行端口均与USB转JTAG模块相连接。As a preferred embodiment of the present invention, the USB Hub circuit includes a plurality of USB downstream ports, and each USB downstream port is connected to a USB to JTAG module.
作为本发明的优选实施方式，所述的拨动滑动开关，使USB接口上的VBUS信号通过电阻器的两个分压电阻接地，所述的电路结构通过控制USB Mux芯片来联通USB接口与USBHub电路。As a preferred embodiment of the present invention, the toggle slide switch allows the VBUS signal on the USB interface to be grounded through two voltage-dividing resistors of the resistor, and the circuit structure connects the USB interface with the USBHub circuit by controlling the USB Mux chip.
本发明的具体实施方式中，在多FPGA芯片系统中，保证JTAG接口可靠的工作，且速率不随着FPGA芯片数量增加而降低，节省宝贵的调试时间。In a specific implementation of the present invention, in a multi-FPGA chip system, the JTAG interface is guaranteed to work reliably, and the rate does not decrease as the number of FPGA chips increases, thereby saving valuable debugging time.
一种适用于多FPGA芯片系统的下载调试电路，其系统框图如附图3虚线框部分所示，包含USB Hub电路，USB转JTAG模块，USB Mux芯片，滑动开关，反相缓冲器芯片，电阻器以及USB接口。A download and debug circuit suitable for a multi-FPGA chip system, whose system block diagram is shown in the dotted box portion of Figure 3, includes a USB Hub circuit, a USB to JTAG module, a USB Mux chip, a slide switch, an inverting buffer chip, a resistor and a USB interface.
该电路通过滑动开关来决定USB接口是用于正常的USB host接口功能或者用于FPGA调试下载功能；电阻器分压至合适电压值，驱动反向缓冲芯片产生控制信号；USB MUX芯片用来切换USB信号；USB HUB电路连接位于不同FPGA目标系统上的USB转JTAG模块；USB转JTAG模块配合上位机软件完成FPGA芯片的下载与调试功能。The circuit uses a sliding switch to determine whether the USB interface is used for the normal USB host interface function or for the FPGA debugging and downloading function; the resistor divides the voltage to a suitable voltage value to drive the reverse buffer chip to generate a control signal; the USB MUX chip is used to switch USB signals; the USB HUB circuit connects the USB to JTAG modules located on different FPGA target systems; the USB to JTAG module cooperates with the host computer software to complete the download and debugging functions of the FPGA chip.
当产品开发调试完成后，可通过切换滑动开关，切换VBUS电压与USB信号通路至正常USB Host电路，使本电路的USB接口作为产品上正常的USB Host接口使用。When product development and debugging are completed, the VBUS voltage and USB signal path can be switched to the normal USB Host circuit by switching the slide switch, so that the USB interface of this circuit can be used as a normal USB Host interface on the product.
在本发明的具体实施例中，USB接口采用USB 2.0type A型连接器，USB Mux芯片采用TI公司的HD3SS3411TRWARQ1，USB Hub芯片采用Cypress公司的CY7C65630-56LTXC，反相缓冲器采用TI公司的SN74LVC1G04DBVR，滑动开关采用C&K公司的1201M2S3ABE2，USB转JTAG模块采用Digilent公司的410-308-B，电阻阻值采用10K欧姆。In a specific embodiment of the present invention, the USB interface adopts a USB 2.0 type A connector, the USB Mux chip adopts TI's HD3SS3411TRWARQ1, the USB Hub chip adopts Cypress's CY7C65630-56LTXC, the inverting buffer adopts TI's SN74LVC1G04DBVR, the slide switch adopts C&K's 1201M2S3ABE2, the USB to JTAG module adopts Digilent's 410-308-B, and the resistance value adopts 10K ohms.
该实例电路通过4片CY7C65630-56LTXC级联构成1分10的USB Hub电路，共产生10个USB下行端口，每个USB下行端口连接至1个位于独立的FPGA目标系统上的USB转JTAG模块。This example circuit forms a 1:10 USB Hub circuit by cascading four CY7C65630-56LTXCs, generating a total of 10 USB downstream ports. Each USB downstream port is connected to a USB to JTAG module located on an independent FPGA target system.
拨动滑动开关，使USB接口上的VBUS信号通过两颗分压电阻R1、R2接地，此时将上位机PC USB host端口通过USB公对公的线缆与本实例电路USB接口连接，则来自上位机USB端口的5V VBUS电压将在分压电阻之间产生一个2.5V的电压，该电压驱动反相缓冲器芯片产生低电平控制信号，该控制信号通过控制USB Mux芯片使本实例电路USB接口与USB Hub电路联通，从而PC上位机可以通过USB接口访问位于每一FPGA目标系统上的USB转JTAG模块，进而通过该模块完成FPGA芯片的配置与调试工作。Toggle the slide switch to connect the VBUS signal on the USB interface to the ground through the two voltage-dividing resistors R1 and R2. At this time, connect the USB host port of the PC to the USB interface of this example circuit through a USB male-to-male cable. The 5V VBUS voltage from the USB port of the PC will generate a 2.5V voltage between the voltage-dividing resistors. This voltage drives the inverting buffer chip to generate a low-level control signal. This control signal connects the USB interface of this example circuit to the USB Hub circuit by controlling the USB Mux chip. In this way, the PC can access the USB to JTAG module on each FPGA target system through the USB interface, and then complete the configuration and debugging of the FPGA chip through this module.
当产品开发调试完成后，可通过切换滑动开关，反相器输入信号变为低电平，控制信号变为高电平，从而本实例电路USB接口与系统中正常的USB Host端口联通，实现了该本实例电路USB接口与普通USB端口复用，同时切断了对外调试接口，增强了产品的技术保密性。When product development and debugging are completed, the sliding switch can be switched so that the inverter input signal becomes a low level and the control signal becomes a high level, thereby connecting the USB interface of this example circuit to the normal USB Host port in the system, realizing the multiplexing of the USB interface of this example circuit and the ordinary USB port, while cutting off the external debugging interface, thereby enhancing the technical confidentiality of the product.
采用了本发明的针对多FPGA芯片电路系统实现下载调试控制的电路结构，通过适当设置USB Hub电路下行端口数量，可在大规模数量FPGA芯片系统中，通过单一USB接口，实现整个系统JTAG调试电路的可靠连接，并保证连接速率最大化。同时电路应用于整机产品时，可使该调试USB接口与普通USB端口复用，不需要额外设计的调试接口。The circuit structure for realizing download debugging control for a multi-FPGA chip circuit system of the present invention is adopted. By appropriately setting the number of downstream ports of the USB Hub circuit, a reliable connection of the JTAG debugging circuit of the entire system can be realized through a single USB interface in a large number of FPGA chip systems, and the connection rate can be maximized. At the same time, when the circuit is applied to a complete product, the debugging USB interface can be reused with a common USB port, and no additional debugging interface needs to be designed.
在此说明书中，本发明已参照其特定的实施例作了描述。但是，很显然仍可以作出各种修改和变换而不背离本发明的精神和范围。因此，说明书和附图应被认为是说明性的而非限制性的。In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111388712.1A CN113934668B (en) | 2021-11-22 | 2021-11-22 | Circuit structure for download and debug control of multi-FPGA chip circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111388712.1A CN113934668B (en) | 2021-11-22 | 2021-11-22 | Circuit structure for download and debug control of multi-FPGA chip circuit system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113934668A CN113934668A (en) | 2022-01-14 |
| CN113934668B true CN113934668B (en) | 2024-11-08 |
Family
ID=79287239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111388712.1A Active CN113934668B (en) | 2021-11-22 | 2021-11-22 | Circuit structure for download and debug control of multi-FPGA chip circuit system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113934668B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN216772404U (en) * | 2021-11-22 | 2022-06-17 | 上海创远仪器技术股份有限公司 | Circuit structure for realizing download debugging control aiming at multi-FPGA chip circuit system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108475227B (en) * | 2016-03-31 | 2020-07-21 | 华为技术有限公司 | Test functional assembly and data debugging method |
| CN210129219U (en) * | 2019-08-09 | 2020-03-06 | 苏州浪潮智能科技有限公司 | Multi-functional USB Type-C interface circuit of FPGA accelerator card |
-
2021
- 2021-11-22 CN CN202111388712.1A patent/CN113934668B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN216772404U (en) * | 2021-11-22 | 2022-06-17 | 上海创远仪器技术股份有限公司 | Circuit structure for realizing download debugging control aiming at multi-FPGA chip circuit system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113934668A (en) | 2022-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10657088B2 (en) | Integrated circuit, bus system and control method thereof | |
| US8656220B2 (en) | System-on-chip and debugging method thereof | |
| US5210855A (en) | System for computer peripheral bus for allowing hot extraction on insertion without disrupting adjacent devices | |
| US7490176B2 (en) | Serial attached SCSI backplane and detection system thereof | |
| US20200132768A1 (en) | SAS Connector Conduction Detecting System And Method Thereof | |
| US6148398A (en) | Setting/driving circuit for use with an integrated circuit logic unit having multi-function pins | |
| CN107943640B (en) | Automatic daisy chain based single-ring JTAG backboard test bus circuit | |
| CN113934668B (en) | Circuit structure for download and debug control of multi-FPGA chip circuit system | |
| WO2016113530A1 (en) | Adapting the usage configuration of integrated circuit input-output pads | |
| CN216772404U (en) | Circuit structure for realizing download debugging control aiming at multi-FPGA chip circuit system | |
| CN111104279B (en) | SAS connector conduction detection system and method thereof | |
| TW201928386A (en) | Peripheral component interconnect express slot detection system and method thereof | |
| US7099966B2 (en) | Point-to-point electrical loading for a multi-drop bus | |
| CN109614683A (en) | Hard disk backboard and control panel | |
| CN108646172A (en) | A kind of apparatus for testing chip | |
| US20070220191A1 (en) | Apparatus and method for preventing configurable system-on-a-chip integrated circuits from becoming I/O limited | |
| CN114020669B (en) | A CPLD-based I2C link system and server | |
| CN115858426A (en) | Hard disk interface, hard disk and electronic equipment | |
| KR100265148B1 (en) | Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate | |
| US6177808B1 (en) | Integration of bidirectional switches with programmable logic | |
| CN111858226B (en) | Electronic device carrying non-volatile memory solid state disk | |
| CN106503369A (en) | A kind of device for realizing that multiple high-speed bus PCB links are shared and its method for designing | |
| TWI873470B (en) | Baseboard management controller and operation method thereof | |
| CN211856798U (en) | A system board card error detection device | |
| US9404968B1 (en) | System and methods for debug connectivity discovery |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |