CN113921603A - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- CN113921603A CN113921603A CN202010658683.5A CN202010658683A CN113921603A CN 113921603 A CN113921603 A CN 113921603A CN 202010658683 A CN202010658683 A CN 202010658683A CN 113921603 A CN113921603 A CN 113921603A
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- 230000007704 transition Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 66
- 238000002955 isolation Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- -1 hydrogen ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/641—Combinations of only vertical BJTs
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- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供一种功率半导体装置，包括有源区、围绕有源区的终端区以及位于有源区及终端区之间的过渡区，有源区设置有第一半导体器件，过渡区设置有第二半导体器件，其中，第一半导体器件的源极及第二槽部内的导电层与发射极电连接，第一槽部内的导电层及第三槽部内的导电层与栅极电连接，第二半导体器件的源极、第二槽部内的导电层及第二槽部与第三槽部之间的阱区与发射极电连接，第一槽部内的导电层及第三槽部内的导电层与栅极电连接。本发明在器件导通时能够有效提高器件正面存储的空穴浓度，降低导通压降及导通损耗，在器件关断时能够快速释放空穴，降低关断损耗，提高器件的抗闩锁能力，提升器件可靠性。
The present invention provides a power semiconductor device, comprising an active area, a terminal area surrounding the active area, and a transition area between the active area and the terminal area, the active area is provided with a first semiconductor device, and the transition area is provided with a second semiconductor device. Two semiconductor devices, wherein the source of the first semiconductor device and the conductive layer in the second groove are electrically connected to the emitter, the conductive layer in the first groove and the conductive layer in the third groove are electrically connected to the gate, the second The source electrode of the semiconductor device, the conductive layer in the second groove portion, and the well region between the second groove portion and the third groove portion are electrically connected to the emitter, and the conductive layer in the first groove portion and the conductive layer in the third groove portion are electrically connected to the emitter. The grid is electrically connected. The invention can effectively increase the concentration of holes stored on the front of the device when the device is turned on, reduce the conduction voltage drop and conduction loss, quickly release holes when the device is turned off, reduce the turn-off loss, and improve the anti-latch of the device capability to improve device reliability.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a power semiconductor device.
Background
The power device is used as a key switch device for controlling strong current by weak current, and is widely applied to the fields of industry, household appliances, electric locomotives, electric automobiles and the like. The development direction of power devices is to reduce the power loss of the power devices under the condition of ensuring the normal switching of the devices, which requires that the conduction voltage of the devices is reduced and the switching loss is small.
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device consisting of a Bipolar Junction Transistor (BJT) and an insulated Gate field effect transistor (MOS), and has the advantages of high input impedance of the MOSFET and low conduction voltage drop of the GTR. The GTR saturation voltage is reduced, the current density is high, but the driving current is high; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. Therefore, the application of the semiconductor is more and more extensive, and the semiconductor is an important power semiconductor device.
Fig. 1 shows a schematic structural diagram of an IGBT device, and as shown in fig. 1, the operating principle of the IGBT is as follows: a positive voltage is applied to a Collector (Collector)106, a positive voltage is applied to a Gate (Gate), a Trench is formed on a side wall of a Trench Gate (Trench)103, which is in contact with a P-type well region (Pbody)102, an electron current starts from an Emitter (Emitter), passes through a metal layer 104 and an N + -type source region 105, then passes through the Trench, reaches an N-type drift region 101, then, a part of electrons are recombined with holes injected by the Collector (Collector)106, and the other part of electrons reach the Collector (Collector)106 to form a current, so that the device is turned on. When negative pressure is applied to the Gate (Gate), the Trench Gate (Trench)103 side wall channel is closed, and the current has no passage, so that the device is turned off.
The existing IGBT device has high power loss and is prone to latch-up, so that both power consumption and reliability of the IGBT device need to be improved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a power semiconductor device, which solves the problems of the prior art that the power loss of the power semiconductor device is high and the latch-up is easy to occur.
In order to achieve the above and other related objects, the present invention provides a power semiconductor device, including an active region, a termination region surrounding the active region, and a transition region between the active region and the termination region, the active region being provided with a first semiconductor device, the transition region being provided with a second semiconductor device; the first semiconductor device includes: a substrate of a first conductivity type including opposing first and second major faces; a well region of a second conductivity type disposed on the first major surface of the substrate; the groove part is arranged on the first main surface of the substrate and penetrates through the well region to the substrate, the groove part comprises at least 3 groove parts which are arranged at intervals, the first groove part and the third groove part are configured to clamp the second groove part, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer; the source electrode of the first conduction type is arranged in the well region and is positioned on the side surface of the first groove part; a collector of a second conductivity type provided on a second main surface of the substrate; the source electrode and the conducting layer in the second groove part are electrically connected with an emitter electrode, and the conducting layer in the first groove part and the conducting layer in the third groove part are electrically connected with a grid electrode; the second semiconductor device includes: a substrate of a first conductivity type including opposing first and second major faces; a well region of a second conductivity type disposed on the first major surface of the substrate; the groove part is arranged on the first main surface of the substrate and penetrates through the well region to the substrate, the groove part comprises at least 3 groove parts which are arranged at intervals, the first groove part and the third groove part are configured to clamp the second groove part, the inner wall of each groove part is covered with an insulating layer, and the insulating layer is filled with a conductive layer; the source electrode of the first conduction type is arranged in the well region and is positioned on the side surface of the first groove part; a collector of a second conductivity type provided on a second main surface of the substrate; the source electrode, the conducting layer in the second groove part and the well region between the second groove part and the third groove part are electrically connected with the emitter, and the conducting layer in the first groove part and the conducting layer in the third groove part are electrically connected with the grid electrode.
Optionally, the power semiconductor device further includes a field stop layer of the first conductivity type disposed on the second main surface of the substrate and between the collector and the substrate.
Optionally, the source electrode of the first conductivity type is disposed only on two sides of the first trench portion, and the source electrode of the first conductivity type is not disposed between the second trench portion and the third trench portion.
Optionally, an isolation layer covers the substrate surface of the first semiconductor device, contact holes penetrating the source electrode and extending to the well region are formed in the isolation layer and the substrate, metal layers are formed on the surface of the isolation layer and in the contact holes, and the source electrode is electrically connected with the emitter electrode through the metal layers.
Optionally, an isolation layer covers the substrate surface of the second semiconductor device, a first contact hole penetrating through the source and extending to the well region and a second contact hole located between the second groove portion and the third groove portion and penetrating to the well region are formed in the isolation layer and the substrate, metal layers are formed in the isolation layer surface, the first contact hole and the second contact hole, and the source and the well region located between the second groove portion and the third groove portion are electrically connected to the emitter through the metal layers.
Optionally, the conductive layer in the first groove of the first semiconductor device is connected to the gate for implementing the conduction and switching functions of the device; the third groove inner conducting layer of the first semiconductor device is connected with the grid and used for adjusting grid-emitter capacitance and grid-collector capacitance, so that the switching speed of the device is improved; and the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, and is used for improving the hole concentration stored on the front surface of the power semiconductor device and reducing conduction loss when the power semiconductor device is conducted.
Optionally, the well region between the second trench portion and the third trench portion of the second semiconductor device is electrically connected to the emitter, and is configured to provide a hole release channel of the power semiconductor device when the power semiconductor device is turned off, so as to reduce turn-off loss and improve the latch-up resistance of the power semiconductor device.
Optionally, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type.
Optionally, the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type.
As described above, the power semiconductor device of the present invention has the following advantageous effects:
the invention optimizes the device of the power semiconductor device aiming at different areas of the semiconductor device (such as IGBT) through novel groove and connection design, can effectively reduce the power loss of the device and improve the reliability of the device.
According to the invention, the conducting layer in the first groove part of the first semiconductor device is connected with the grid, so that the conduction and switching functions of the device can be realized; the conducting layer in the third groove part of the first semiconductor device is connected with the grid, and the grid-emitter capacitance and the grid-collector capacitance can be adjusted, so that the switching speed of the device is improved; the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the hole concentration stored on the front side of the power semiconductor device can be improved, and the conduction loss is reduced.
According to the invention, aiming at the higher positive hole stored, the second semiconductor device is added in the transition region between the active region and the terminal region, the positive hole concentration of the second semiconductor device is lower, and the well region between the second groove part and the third groove part of the second semiconductor device is electrically connected with the emitter, so that more hole release channels can be provided, the holes can be quickly released when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
Drawings
Fig. 1 shows a schematic structure of an IGBT in the prior art.
Fig. 2 is a schematic plan view of a power semiconductor device according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a first semiconductor device of a power semiconductor apparatus according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a second semiconductor device of the power semiconductor device according to the embodiment of the present invention.
Fig. 5 is a graph showing the relationship between the device depth and the hole concentration of the first semiconductor device (curve a) and the second semiconductor device (curve B) according to the embodiment of the present invention.
Description of the element reference numerals
101 n-type drift region
102P type well region
103 trench gate
104 metal layer
105N + source region
106 collector electrode
20 active region
21 transition zone
22 terminal area
23 groove
201 substrate
202 well region
203 conductive layer
204 insulating layer
205 source electrode
206 field stop layer
207 collector electrode
208 metal layer
209 first contact hole
210 second contact hole
301 first groove part
302 second groove part
303 third groove part
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 2 to 4, the present embodiment provides a power semiconductor device, which is used to solve the problems of the prior art that the power semiconductor device has high power loss and is easy to generate latch-up effect.
As shown in fig. 2, the power semiconductor device includes an active region 20, a termination region 22 surrounding the active region 20, and a transition region 21 located between the active region 20 and the termination region 22, as shown in fig. 2, the power semiconductor device may be configured to be rectangular to improve the space utilization of the device, the central region of the power semiconductor device is the active region 20, the peripheral region is the termination region 22, the termination region 22 surrounds the active region 20 in a rectangular ring shape, the transition region 21 is located between the active region 20 and the termination region 22, and the transition region 21 may be located at two ends of the extending direction of the trench 23, as shown by a dashed box in fig. 2.
As shown in fig. 3, the active region 20 is provided with a first semiconductor device, which includes a substrate 201 of a first conductivity type, a well 202 of a second conductivity type, a trench, a source 205 of the first conductivity type, and a collector 207 of the second conductivity type. In order to improve the voltage endurance of the power semiconductor device, the power semiconductor device further includes a field stop layer 206 of the first conductivity type disposed on the second main surface of the substrate 201 and located between the collector electrode 207 and the substrate 201, and the doped ions of the field stop layer 206 may be hydrogen ions or the like.
The substrate 201 of the first conductivity type includes opposing first and second major faces. The substrate 201 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, and the like, and is not limited to the examples listed herein. The substrate 201 may be an N-type doped substrate or a P-type doped substrate, in this embodiment, the substrate 201 is an N-type doped silicon substrate, and the doped ions may be phosphorus, etc., of course, in other embodiments, the substrate 201 may also be a P-type doped substrate, for example, the doped ions may be boron, etc., which may be selected according to the actual requirements of the device.
The well region 202 of the second conductivity type is disposed on the first main surface of the substrate 201. In the present embodiment, the well region 202 of the second conductivity type is a P-type conductivity type, and the doped ions thereof may be boron and the like.
The trench portion is disposed on the first main surface of the substrate 201, and penetrates through the well region 202 into the substrate 201, the trench portion includes at least 3 trench portions arranged at intervals, the first trench portion 301 and the third trench portion 303 are configured to sandwich the second trench portion 302, and the first trench portion 301, the second trench portion 302, and the third trench portion 303 may be arranged in parallel, for example. The inner wall of each groove is covered with an insulating layer 204, and the insulating layer 204 is filled with a conductive layer 203. For example, the insulating layer 204 may be a silicon dioxide layer, a high-k dielectric layer, or the like, and the conductive layer 203 may be a conductive material such as polysilicon or metal. It should be noted that the present invention is limited only to the case where the first groove 301 and the third groove 303 are arranged so as to sandwich the second groove 302, but the number of the first groove 301, the second groove 302, and the third groove is not limited to this, and the arrangement thereof may be the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, the third groove 303, and the third groove 303, the second groove 302, the first groove 301, the second groove 302, and the third groove 303, and the like, and the examples are not limited to these.
The source 205 of the first conductivity type is disposed in the well 202 and is located at a side of the first trench 301. In the present embodiment, the source 205 is of N-type conductivity, and the dopant ions may be phosphorus. Further, the source electrode 205 of the first conductive type is disposed only at both sides of the first trench portion 301, and the source electrode 205 of the first conductive type is not disposed between the second trench portion 302 and the third trench portion 303.
The collector electrode 207 of the second conductivity type is disposed on the second main surface of the substrate 201. In the present embodiment, the collector 207 is of P-type conductivity, and the dopant ions thereof may be boron or the like.
As shown in fig. 3, the source 205 and the conductive layer 203 in the second groove portion 302 are electrically connected to an emitter, and the conductive layer 203 in the first groove portion 301 and the conductive layer 203 in the third groove portion 303 are electrically connected to a gate. As an example, the surface of the substrate 201 of the first semiconductor device is covered with an isolation layer, the isolation layer and the substrate 201 have a contact hole penetrating through the source 205 and extending to the well region 202, a metal layer 208 is formed on the surface of the isolation layer and in the contact hole 209, and the source 205 is electrically connected to the emitter through the metal layer 208. The conductive layer in the first groove part 301 of the first semiconductor device is connected with the gate, and is used for realizing the conduction and switching functions of the device; the conducting layer in the third groove part 303 of the first semiconductor device is connected with the grid and used for adjusting grid-emitter capacitance and grid-collector capacitance, so that the switching speed of the device is improved; the well region between the second trench portion 302 and the third trench portion 303 of the first semiconductor device is isolated from the emitter, and is used for increasing the hole concentration stored on the front surface of the power semiconductor device and reducing conduction loss when the power semiconductor device is conducted. For the first semiconductor device, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type. However, in other embodiments, the first conductive type may be a P-type conductive type, and the second conductive type may be an N-type conductive type.
As shown in fig. 4, the transition region 21 is provided with a second semiconductor device, which includes a substrate 201 of a first conductivity type, a well 202 of a second conductivity type, a trench, a source 205 of the first conductivity type, and a collector 207 of the second conductivity type. In order to improve the voltage endurance of the power semiconductor device, the power semiconductor device further includes a field stop layer 206 of the first conductivity type disposed on the second main surface of the substrate 201 and located between the collector electrode 207 and the substrate 201, and the doped ions of the field stop layer 206 may be hydrogen ions or the like.
The substrate 201 of the first conductivity type includes opposing first and second major faces. The well region 202 of the second conductivity type is disposed on the first major surface of the substrate. In the present embodiment, the well region 202 of the second conductivity type is a P-type conductivity type, and the doped ions thereof may be boron and the like. The second semiconductor device and the first semiconductor device are formed on the same wafer, and the substrate and the well region 202 of the second semiconductor device and the first semiconductor device are the same substrate and the well region 202.
The trench portion is disposed on the first main surface of the substrate, and penetrates through the well region 202 into the substrate, the trench portion includes at least 3 trench portions arranged at intervals, the first trench portion 301 and the third trench portion 303 are configured to sandwich the second trench portion 302, and the first trench portion 301, the second trench portion 302, and the third trench portion 303 may be arranged in parallel, for example. The inner wall of each groove is covered with an insulating layer 204, and the insulating layer 204 is filled with a conductive layer 203. For example, the insulating layer 204 may be a silicon dioxide layer, a high-k dielectric layer, or the like, and the conductive layer 203 may be a conductive material such as polysilicon or metal. It should be noted that the present invention is limited only to the case where the first groove 301 and the third groove 303 are arranged so as to sandwich the second groove 302, but the number of the first groove 301, the second groove 302, and the third groove is not limited to this, and the arrangement thereof may be the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, and the third groove 303, the first groove 301, the second groove 302, the third groove 303, and the third groove 303, the second groove 302, the first groove 301, the second groove 302, and the third groove 303, and the like, and the examples are not limited to these.
The source 205 of the first conductivity type is disposed in the well 202 and is located at a side of the first trench 301. In the present embodiment, the source 205 is of N-type conductivity, and the dopant ions may be phosphorus. Further, the source electrode 205 of the first conductive type is disposed only at both sides of the first trench portion 301, and the source electrode 205 of the first conductive type is not disposed between the second trench portion 302 and the third trench portion 303.
A collector electrode 207 of the second conductivity type is arranged on the second main surface of the substrate. In the present embodiment, the collector 207 is of P-type conductivity, and the dopant ions thereof may be boron or the like.
As shown in fig. 4, the source 205, the conductive layer 203 in the second trench portion 302, and the well 202 between the second trench portion 302 and the third trench portion 303 are electrically connected to an emitter, and the conductive layer 203 in the first trench portion 301 and the conductive layer 203 in the third trench portion 303 are electrically connected to a gate. As an example, the substrate surface of the second semiconductor device is covered with an isolation layer, the isolation layer and the substrate have a first contact hole 209 penetrating through the source 205 and extending to the well region 202 and a second contact hole 210 located between the second trench portion 302 and the third trench portion 303 and penetrating to the well region 202, a metal layer 208 is formed in the isolation layer surface, the first contact hole 209 and the second contact hole 210, and the source 205 and the well region 202 located between the second trench portion 302 and the third trench portion 303 are electrically connected to an emitter through the metal layer 208. The well region 202 between the second trench portion 302 and the third trench portion 303 of the second semiconductor device is electrically connected to the emitter, and is used for providing a hole release channel of the power semiconductor device when the power semiconductor device is turned off, reducing turn-off loss, and improving the latch-up resistance of the power semiconductor device.
For the second semiconductor device, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type. However, in other embodiments, the first conductive type may be a P-type conductive type, and the second conductive type may be an N-type conductive type.
Fig. 5 is a graph showing the relationship between the depth of the first semiconductor device (curve a) and the hole concentration of the second semiconductor device (curve B) according to the present invention, wherein the first semiconductor device in the active region 20 can effectively increase the hole concentration stored on the front surface of the device, thereby reducing the device turn-on voltage drop (Vcesat) and reducing the turn-on loss. The higher hole concentration stored in the front side needs to be released quickly when the device is turned off, so that the second semiconductor device is added at the transition part between the edge of the active region 20 and the terminal region 22, as shown in fig. 5, the front side hole concentration of the second semiconductor device is lower, and the second contact hole 210210 of the well region 202 between the second groove part 302 and the third groove part 303 of the second semiconductor device can provide more hole release channels, so that the holes can be released quickly when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
As described above, the power semiconductor device of the present invention has the following advantageous effects:
the invention optimizes the device of the power semiconductor device (such as IGBT) aiming at different areas of the semiconductor device through novel groove and connection design, can effectively reduce the power loss of the device and improve the reliability of the device.
According to the invention, the conducting layer in the first groove part of the first semiconductor device is connected with the grid, so that the conduction and switching functions of the device can be realized; the conducting layer in the third groove part of the first semiconductor device is connected with the grid, and the grid-emitter capacitance and the grid-collector capacitance can be adjusted, so that the switching speed of the device is improved; the well region between the second groove part and the third groove part of the first semiconductor device is isolated from the emitter, so that when the power semiconductor device is conducted, the hole concentration stored on the front side of the power semiconductor device can be improved, and the conduction loss is reduced. Aiming at the higher positive hole, the second semiconductor device is added in the transition region 21 between the active region 20 and the terminal region 22, the positive hole concentration of the second semiconductor device is lower, and the well region 202 between the second groove part 302 and the third groove part 303 of the second semiconductor device is electrically connected with the emitter, so that more hole release channels can be provided, the holes can be quickly released when the device is turned off, the turn-off loss of the device is reduced, the latch-up resistance of the device is improved, and the reliability of the device is improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179074A (en) * | 2006-11-10 | 2008-05-14 | 国际商业机器公司 | Integrated semiconductor device and method of forming the same |
| US20130113021A1 (en) * | 2011-11-08 | 2013-05-09 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Sige hbt having deep pseudo buried layer and manufacturing method thereof |
| JP2015162610A (en) * | 2014-02-27 | 2015-09-07 | 株式会社東芝 | semiconductor device |
| CN206976354U (en) * | 2017-07-25 | 2018-02-06 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure of deep trench |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179074A (en) * | 2006-11-10 | 2008-05-14 | 国际商业机器公司 | Integrated semiconductor device and method of forming the same |
| US20130113021A1 (en) * | 2011-11-08 | 2013-05-09 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Sige hbt having deep pseudo buried layer and manufacturing method thereof |
| JP2015162610A (en) * | 2014-02-27 | 2015-09-07 | 株式会社東芝 | semiconductor device |
| CN206976354U (en) * | 2017-07-25 | 2018-02-06 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure of deep trench |
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