CN113921461A - Copper conductor manufacturing process method - Google Patents
Copper conductor manufacturing process method Download PDFInfo
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- CN113921461A CN113921461A CN202010661435.6A CN202010661435A CN113921461A CN 113921461 A CN113921461 A CN 113921461A CN 202010661435 A CN202010661435 A CN 202010661435A CN 113921461 A CN113921461 A CN 113921461A
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- layer
- hole
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- seed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention provides a copper conductor processing method, which is characterized in that a restraining layer covering the surface of a seed crystal layer with preset depth at an opening of a hole to be processed is formed, so that copper is not easy to adhere to the surface of the restraining layer in the copper electroplating process, the growth rate of copper in the restraining layer area from the side wall to the center is reduced, and copper is further plated from the bottom of the hole to be processed to the opening. That is to say, after filling the bottom with copper, the preliminary depth zone of pending hole opening part just begins copper facing, the problem of sealing can not appear, after copper facing is accomplished, can fill up pending hole, and then the problem in space also can not appear.
Description
Technical Field
The invention relates to the technical field of copper wire manufacturing processes, in particular to a copper wire manufacturing process method.
Background
With the continuous development of science and technology, various electronic devices are widely applied to the life and work of people, and great convenience is brought to the daily life of people.
The circuit boards in most electronic devices are electrically connected by way of hole copper plating.
At present, the copper wire process is to form a seed layer in a hole and then copper plating is performed to fill the hole area, but the seed layer forming process is generally a PVD (physical vapor Deposition) process, and the growth method using the process will grow faster at the opening of the hole, resulting in a thicker seed layer at the opening of the hole.
Then, after the seed crystal layer is generated, copper plating is performed from the bottom to the opening in the copper plating process, and copper plating is performed simultaneously on the trend that the side wall faces the center.
Disclosure of Invention
In view of the above, in order to solve the above problems, the present invention provides a copper wire manufacturing method, which has the following technical scheme:
a copper wire manufacturing method comprises the following steps:
forming a barrier layer in the hole to be processed;
forming a seed layer on the surface of the barrier layer;
forming a restraining layer on the surface of the seed crystal layer, wherein the restraining layer covers the surface of the seed crystal layer with a preset depth at the opening of the hole to be processed;
electroplating copper in the hole to be processed until the hole to be processed is filled;
the inhibition layer is used for plating copper from the bottom of the hole to be processed to the opening in the copper electroplating process.
Preferably, in the above method for fabricating a copper wire, the forming of the inhibiting layer on the surface of the seed layer includes:
and introducing inert gas into the hole to be treated to adhere to the surface of the seed crystal layer to form the inhibition layer.
Preferably, in the above copper wire manufacturing method, the inhibiting layer is an Ar material inhibiting layer.
Preferably, in the above copper wire manufacturing method, the depth of the inhibition layer covering the seed crystal layer is a certain proportion of the depth of the hole to be processed from the opening of the hole to be processed.
Preferably, in the above copper wire manufacturing method, the barrier layer is a TaN barrier layer.
Preferably, in the above copper wire manufacturing method, the barrier layer covers the sidewall and the bottom of the hole to be processed.
Preferably, in the above method for manufacturing a copper wire, the forming a barrier layer in the hole to be processed includes:
and growing the barrier layer in the hole to be processed in a physical vapor deposition mode.
Preferably, in the above method for manufacturing a copper wire, the forming a seed layer on the surface of the barrier layer includes:
and growing the seed layer on the surface of the barrier layer by adopting a physical vapor deposition mode.
Preferably, in the above copper wire manufacturing method, the seed layer is a copper seed layer.
Preferably, in the above copper wire manufacturing method, the electroplating copper in the hole to be processed includes:
and plating copper in the hole to be treated by adopting an electrochemical copper plating mode.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a copper wire manufacturing process method, which comprises the following steps: forming a barrier layer in the hole to be processed; forming a seed layer on the surface of the barrier layer; forming a restraining layer on the surface of the seed crystal layer, wherein the restraining layer covers the surface of the seed crystal layer with a preset depth at the opening of the hole to be processed; electroplating copper in the hole to be processed until the hole to be processed is filled; the inhibition layer is used for plating copper from the bottom of the hole to be processed to the opening in the copper electroplating process.
According to the copper conductor processing method, the inhibiting layer covering the surface of the seed crystal layer with the preset depth at the opening of the hole to be processed is formed, so that copper is not easy to adhere to the surface of the inhibiting layer in the copper electroplating process, the growth rate of copper in the inhibiting layer area from the side wall to the center is reduced, and copper plating is carried out from the bottom of the hole to be processed to the opening. That is to say, after filling the bottom with copper, the preliminary depth zone of pending hole opening part just begins copper facing, the problem of sealing can not appear, after copper facing is accomplished, can fill up pending hole, and then the problem in space also can not appear.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic flow chart illustrating a copper wire manufacturing method according to an embodiment of the present invention;
fig. 2-6 are schematic diagrams illustrating a related method for manufacturing the copper wire shown in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a copper wire manufacturing method according to an embodiment of the present invention.
The copper wire manufacturing process method comprises the following steps:
s101: as shown in fig. 2, a barrier layer 12 is formed in the hole 11 to be processed.
S102: as shown in fig. 3, a seed layer 13 is formed on the surface of the barrier layer 12.
S103: as shown in fig. 4, a suppression layer 14 is formed on the surface of the seed layer 13, and the suppression layer 14 covers the surface of the seed layer 13 at a predetermined depth at the opening of the hole 11 to be processed.
S104: as shown in fig. 5 and 6, copper is electroplated in the hole 11 to be processed until the hole 11 to be processed is filled.
Wherein the inhibiting layer 14 is used for copper plating from the bottom of the hole 11 to be processed to the opening in the copper electroplating process.
In this embodiment, by forming the inhibiting layer 14 covering the surface of the seed layer 13 with the predetermined depth at the opening of the hole 11 to be processed, copper is not easily attached to the surface of the inhibiting layer 14 during the copper electroplating process, so that the growth rate of copper from the side wall to the center in the area of the inhibiting layer 14 is reduced, and copper is further plated from the bottom of the hole to be processed to the opening.
That is to say, as shown in fig. 5, after the bottom is filled with copper, the copper plating is started in the area with the preset depth at the opening of the hole to be processed, and the problem of sealing does not occur, as shown in fig. 6, after the copper plating is completed, the hole to be processed can be filled, and then the problem of gaps does not occur.
Further, according to the above embodiment of the present invention, the forming of the inhibition layer 14 on the surface of the seed layer 13 includes:
and introducing inert gas into the hole to be treated to adhere to the surface of the seed crystal layer to form the inhibition layer.
In this embodiment, the coverage area of the inhibition layer is controlled by controlling parameters such as the rate of inert gas introduction.
Further, according to the above embodiment of the present invention, the inhibiting layer 14 includes, but is not limited to, an Ar material inhibiting layer, and may also be a material layer of other inert gases.
Further, according to the above embodiment of the present invention, the depth of the inhibition layer 14 covering the seed layer 13 is a certain proportion of the depth of the hole to be processed from the opening of the hole to be processed.
For example, the inhibition layer 14 covers the seed layer 13 to a depth 1/4-1/3 of the depth of the holes to be processed from the openings of the holes to be processed.
Further, according to the above embodiment of the present invention, the barrier layer 12 includes, but is not limited to, a TaN barrier layer.
In this embodiment, the barrier layer 12 is used to prevent the copper material from reacting with other film structures, so as to improve the structural stability.
Further, according to the above embodiment of the present invention, the barrier layer 12 covers the sidewall and the bottom of the hole to be processed.
In this embodiment, the blocking effect can be greatly improved by covering the blocking layer on the side wall and the bottom of the hole to be processed in a large area.
Further, according to the above embodiments of the present invention, the forming a barrier layer in the hole to be processed includes:
and growing the barrier layer in the hole to be processed in a physical vapor deposition mode.
In this embodiment, the physical vapor deposition is merely exemplified, and the embodiment of the present invention is not limited thereto.
Further, according to the above embodiment of the present invention, the forming a seed layer 13 on the surface of the barrier layer 12 includes:
and growing the seed layer on the surface of the barrier layer by adopting a physical vapor deposition mode.
In this embodiment, the physical vapor deposition is merely exemplified, and the embodiment of the present invention is not limited thereto.
It should be noted that, the growth parameters of the seed layer need to be controlled during the growth of the seed layer, and the seed layer cannot seal the opening of the hole to be processed.
Optionally, the seed layer 13 is a copper seed layer.
Further, according to the above embodiment of the present invention, the electroplating of copper in the hole to be processed includes:
and plating copper in the hole to be treated by adopting an electrochemical copper plating mode.
The copper wire manufacturing method provided by the invention is described in detail, and the principle and the implementation mode of the invention are explained by applying specific examples, and the description of the examples is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A copper wire manufacturing method is characterized by comprising the following steps:
forming a barrier layer in the hole to be processed;
forming a seed layer on the surface of the barrier layer;
forming a restraining layer on the surface of the seed crystal layer, wherein the restraining layer covers the surface of the seed crystal layer with a preset depth at the opening of the hole to be processed;
electroplating copper in the hole to be processed until the hole to be processed is filled;
the inhibition layer is used for plating copper from the bottom of the hole to be processed to the opening in the copper electroplating process.
2. The method of claim 1, wherein forming a suppression layer on a surface of the seed layer comprises:
and introducing inert gas into the hole to be treated to adhere to the surface of the seed crystal layer to form the inhibition layer.
3. The method of claim 1, wherein the inhibiting layer is an Ar material inhibiting layer.
4. The method as claimed in claim 1, wherein the inhibiting layer covers the seed layer to a depth that is a proportion of the depth of the hole to be processed from the opening of the hole to be processed.
5. The method as claimed in claim 1, wherein the barrier layer is a TaN barrier layer.
6. The method as claimed in claim 1, wherein the barrier layer covers sidewalls and a bottom of the hole to be processed.
7. The method as claimed in claim 1, wherein the step of forming a barrier layer in the hole to be processed comprises:
and growing the barrier layer in the hole to be processed in a physical vapor deposition mode.
8. The method of claim 1, wherein the forming a seed layer on the surface of the barrier layer comprises:
and growing the seed layer on the surface of the barrier layer by adopting a physical vapor deposition mode.
9. The method of claim 1, wherein the seed layer is a copper seed layer.
10. The method as claimed in claim 1, wherein the step of electroplating copper into the hole to be processed comprises:
and plating copper in the hole to be treated by adopting an electrochemical copper plating mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010661435.6A CN113921461A (en) | 2020-07-10 | 2020-07-10 | Copper conductor manufacturing process method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010661435.6A CN113921461A (en) | 2020-07-10 | 2020-07-10 | Copper conductor manufacturing process method |
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| CN113921461A true CN113921461A (en) | 2022-01-11 |
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| CN202010661435.6A Pending CN113921461A (en) | 2020-07-10 | 2020-07-10 | Copper conductor manufacturing process method |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030194850A1 (en) * | 2002-04-16 | 2003-10-16 | Applied Materials, Inc. | Method and apparatus for improved electroplating fill of an aperture |
| TW200518266A (en) * | 2003-11-25 | 2005-06-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a multi-layer seed layer for improved Cu ECP |
| US20060234499A1 (en) * | 2005-03-29 | 2006-10-19 | Akira Kodera | Substrate processing method and substrate processing apparatus |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| CN104124196A (en) * | 2013-04-23 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107591358A (en) * | 2017-08-31 | 2018-01-16 | 长江存储科技有限责任公司 | A kind of preparation method of interconnection structure and preparation method thereof and semiconductor devices |
| US20180068889A1 (en) * | 2016-09-05 | 2018-03-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
2020
- 2020-07-10 CN CN202010661435.6A patent/CN113921461A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030194850A1 (en) * | 2002-04-16 | 2003-10-16 | Applied Materials, Inc. | Method and apparatus for improved electroplating fill of an aperture |
| TW200518266A (en) * | 2003-11-25 | 2005-06-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a multi-layer seed layer for improved Cu ECP |
| US20060234499A1 (en) * | 2005-03-29 | 2006-10-19 | Akira Kodera | Substrate processing method and substrate processing apparatus |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| CN104124196A (en) * | 2013-04-23 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| US20180068889A1 (en) * | 2016-09-05 | 2018-03-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN107591358A (en) * | 2017-08-31 | 2018-01-16 | 长江存储科技有限责任公司 | A kind of preparation method of interconnection structure and preparation method thereof and semiconductor devices |
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