CN113917321A

CN113917321A - Scan chain test method and device, computer equipment and storage medium

Info

Publication number: CN113917321A
Application number: CN202111514524.9A
Authority: CN
Inventors: 陈燕; 张帅; 邱进超
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2022-01-11
Anticipated expiration: 2041-12-13
Also published as: CN113917321B

Abstract

The invention discloses a scan chain testing method and device, computer equipment and a storage medium, and relates to the technical field of scan chain testing. The method comprises the following steps: acquiring initial clock delay and clock delay ranges of registers in a target physical region; adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register; and completing scan chain test on the target physical area according to the target clock delay corresponding to each register. By adopting the method, the target clock delay deviation of each register is larger, so that the register is turned over less in a short time, the instantaneous power consumption of a target physical area is further reduced, and the test safety of a chip is ensured.

Description

Scan chain test method and device, computer equipment and storage medium

Technical Field

The invention relates to the technical field of scan chain testing, in particular to a scan chain testing method, a scan chain testing device, computer equipment and a storage medium.

Background

The scan chain test is one of the important methods for testing the digital integrated circuit, so that a bad chip can be effectively screened out, and the product quality is improved. The basic principle of the scanning chain is that the Q end and the SI end of a scanning register on a chip are connected in sequence to form the scanning chain. The scan chain can serially input data (test vectors) into the SI end of each register in a scan chain shifting mode, and the purpose of controlling each register is achieved. And under the scan chain capturing mode, the feedback of the chip combinational logic is transmitted back to the register, so that the internal observation of the chip is realized.

When the chip works in a scan chain shifting mode in scan chain test, test vectors are loaded onto different scan chains in sequence, in the process, as the purpose of clock tree synthesis is to make the clock length of each register flat, that is, the delay of each register clock signal is basically similar (the maximum and minimum difference is called clock deviation), for example, in fig. 1, the clock signal delay of different register clock input ports is different and is different from 0.9ns to 1.2ns, and the clock deviation is 0.3 ns. That is, the clock edge will reach all registers within 0.3 ns. Causing a large number of inversions of the combinatorial logic of the register and its fan-out in a short time, resulting in large instantaneous dynamic power consumption. Excessive instantaneous power consumption may burn out the chip or cause the test items to fail.

In the prior art, it is common practice to divide a chip into a plurality of physical modules, each of which performs scan chain testing separately. This has the advantage that the various parts of the chip can be tested separately without the need for the clock signal of the module under test to be turned off, thereby reducing the instantaneous power consumption of the whole chip during testing.

However, when the chip is divided into a plurality of physical modules, some of the physical modules may be large, and the instantaneous power consumption may also be large during the test. If the physical module is further split, the design complexity is increased, and the test time and the test cost are also increased.

Disclosure of Invention

In view of this, embodiments of the present invention provide a scan chain testing method, apparatus, computer device, and storage medium, so as to solve the problems of large instantaneous power consumption and easy chip burning during chip testing.

According to a first aspect, an embodiment of the present invention provides a scan chain testing method, where the method includes: acquiring initial clock delay and clock delay ranges of registers in a target physical region; adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register; and completing scan chain test on the target physical area according to the target clock delay corresponding to each register.

In the embodiment of the application, the computer equipment acquires the initial clock delay and the clock delay range of each register in the target physical area; adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register; and completing scan chain test on the target physical area according to the target clock delay corresponding to each register. In the method, the computer device adjusts each initial clock delay corresponding to each register according to the clock delay range corresponding to each register to obtain the target clock delay corresponding to each register. Therefore, the target clock delay deviation of each register is large, the register is turned over less in a short time, the instantaneous power consumption of a target physical area is further reduced, and the chip test safety is guaranteed.

With reference to the first aspect, in the first embodiment of the first aspect, adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register includes: determining the maximum value and the minimum value of the clock delay from each clock delay range; calculating the corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value; and determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

In the embodiment of the application, the computer equipment determines the maximum value and the minimum value of the clock delay from each clock delay range; calculating the corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value; and determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range. Therefore, the final relatively even target clock delay distribution of all the registers can be ensured, and the target clock delay deviation of each register is relatively large, so that the registers are turned over less in a short time, the instantaneous power consumption of a target physical area is further reduced, and the chip test safety is ensured.

With reference to the first embodiment of the first aspect, in the second embodiment of the first aspect, determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each candidate clock delay, and each clock delay range includes: determining a first register corresponding to the maximum value, and determining that the maximum value is the target clock delay corresponding to the first register; determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register; and determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

In the embodiment of the application, the computer device determines the first register corresponding to the maximum value and determines that the maximum value is the target clock delay corresponding to the first register, so that the maximum target clock delay corresponding to the first register is ensured. And determining a second register corresponding to the minimum value, determining the minimum value as the target clock delay corresponding to the second register, thereby ensuring the target clock delay corresponding to the second register to be minimum, further ensuring the target clock delay deviation of the first register and the second register to be larger, and then determining the target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges. So that the target clock delay distribution of all registers is relatively even finally. Therefore, the method can ensure that the register is turned a little in a short time, further reduce the instantaneous power consumption of the target physical area and ensure the test safety of the chip.

With reference to the second implementation manner of the first aspect, in the third implementation manner of the first aspect, determining the target clock delays corresponding to the remaining registers according to the candidate clock delays and the clock delay ranges includes: sequencing the alternative clock delays from large to small, and determining alternative clock delay with the second sequence and alternative clock delay with the second to last sequence; determining a second large value and a second small value of the clock delay according to each clock delay range, and determining a third register and a fourth register according to the second large value and the second small value; comparing the second alternative clock delay with the second large value, and determining the target clock delay corresponding to the third register according to the comparison result; and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

In the embodiment of the application, the computer device sorts the alternative clock delays from big to small, and determines the alternative clock delay with the second sorting and the alternative clock delay with the second to last sorting; determining a second large value and a second small value of the clock delay according to each clock delay range, and determining a third register and a fourth register according to the second large value and the second small value; comparing the second alternative clock delay with the second large value, and determining the target clock delay corresponding to the third register according to the comparison result; and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result. Therefore, the target clock corresponding to the determined third register and the target clock corresponding to the determined fourth register can be delayed accurately, the front-stage time sequence and the rear-stage time sequence of each register cannot be influenced, and the time deviation between the target clock and the first register and the time deviation between the target clock and the second register are large.

With reference to the third implementation manner of the first aspect, in the fourth implementation manner of the first aspect, determining a target clock delay corresponding to the third register according to the comparison result includes: if the delay of the second alternative clock is greater than or equal to a second large value, determining the second large value as the target clock delay corresponding to the third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

In the embodiment of the present application, if the delay of the second alternative clock is greater than or equal to the second large value, the second large value is determined as the target clock delay corresponding to the third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register. Therefore, the influence of the time sequence of the front stage and the rear stage of the register can be avoided, the larger clock delay deviation between the third register and the first register can be ensured, and the overturning of each register in a short time can be reduced.

With reference to the third implementation manner of the first aspect, in the fifth implementation manner of the first aspect, the determining, according to the comparison result, a target clock delay corresponding to the fourth register includes: if the delay of the alternative clock with the second from last in the sequence is larger than or equal to a second small value, determining the delay of the alternative clock with the second from last in the sequence as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

In the embodiment of the application, if the delay of the alternative clock with the second from last in the sequence is greater than or equal to a second small value, determining the delay of the alternative clock with the second from last in the sequence as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than a second small value, determining the second small value as the target clock delay corresponding to the fourth register. Therefore, the influence of the time sequence of the front stage and the rear stage of the register can be avoided, the clock delay deviation between the fourth register and the second register can be ensured to be larger, and the overturning of the registers in a short time can be reduced.

With reference to the third implementation manner of the first aspect, in a sixth implementation manner of the first aspect, determining the third register and the fourth register according to the second large value and the second small value includes: judging whether the number corresponding to the second extreme value is greater than 1, wherein the second extreme value comprises a second large value and a second small value; when the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register.

In the embodiment of the present application, it is determined whether the number corresponding to the second extreme value is greater than 1, where the second extreme value includes a second large value and a second small value. When the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register. Therefore, the third register and the fourth register which are determined are accurate, the condition that a plurality of registers correspond to the same target clock delay is avoided, the number of registers which are inverted in a short time is small, and therefore the instantaneous power of the chip is reduced.

According to a second aspect, an embodiment of the present invention provides a scan chain test apparatus, including:

the acquisition module is used for acquiring the initial clock delay and the clock delay range of each register in the target physical area;

the adjusting module is used for adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register;

and the completion module is used for completing the scan chain test on the target physical area according to the target clock delay corresponding to each register.

With reference to the second aspect, in a first embodiment of the second aspect, the adjusting module includes:

a first determining unit for determining a maximum value and a minimum value of the clock delay from each clock delay range;

the computing unit is used for computing each alternative clock delay corresponding to each register under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value;

and the second determining unit is used for determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

With reference to the first embodiment of the second aspect, in the second embodiment of the second aspect, the second determining unit is specifically configured to determine the first register corresponding to the maximum value, and determine the maximum value as the target clock delay corresponding to the first register; determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register; and determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

With reference to the second embodiment of the second aspect, in a third embodiment of the second aspect, the second determining unit is specifically configured to sort the candidate clock delays from large to small, and determine a second candidate clock delay and a second last candidate clock delay from the sorted candidate clock delays; determining a second large value and a second small value of the clock delay according to each clock delay range, and determining a third register and a fourth register according to the second large value and the second small value; comparing the second alternative clock delay with the second large value, and determining the target clock delay corresponding to the third register according to the comparison result; and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

With reference to the third embodiment of the second aspect, in a fourth embodiment of the second aspect, the second determining unit is specifically configured to determine, if the second candidate clock delay of the sorting second is greater than or equal to a second large value, the second large value as a target clock delay corresponding to a third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

With reference to the third embodiment of the second aspect, in a fifth embodiment of the second aspect, the second determining unit is specifically configured to determine, if the clock delay candidate with the second from last rank is greater than or equal to a second small value, the clock delay candidate with the second from last rank as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

With reference to the third embodiment of the second aspect, in a sixth embodiment of the second aspect, the second determining unit is specifically configured to determine whether the number corresponding to the second extreme value is greater than 1, where the second extreme value includes a second large value and a second small value; when the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register.

According to a third aspect, an embodiment of the present invention provides a computer device, including: the scan chain testing method comprises a memory and a processor, wherein the memory and the processor are mutually connected in a communication mode, computer instructions are stored in the memory, and the processor executes the computer instructions so as to execute the scan chain testing method in the first aspect or any one of the implementation modes of the first aspect.

According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer instructions for causing a computer to execute the scan chain testing method in the first aspect or any one of the implementation manners of the first aspect.

According to a fifth aspect, an embodiment of the present invention provides a computer program product, where the computer program product includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions, which, when executed by a computer, cause the computer to execute the scan chain testing method in the first aspect or any one of the implementation manners of the first aspect.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:

FIG. 1 is a diagram illustrating different clock signal delays at different register clock input ports of a scan chain test method in one embodiment;

FIG. 2 is a flow chart illustrating the steps of a scan chain test method in another embodiment;

FIG. 3 is a diagram showing a chip divided into a plurality of physical regions in another scan chain test method in an embodiment;

FIG. 4 is a diagram showing the distribution of initial clock delays of registers in a scan chain test method in another embodiment;

FIG. 5 is a diagram showing the distribution of the clock delay ranges of registers in the scan chain test method in another embodiment;

FIG. 6 is a flow chart illustrating the steps of a scan chain test method in another embodiment;

FIG. 7 is a flowchart illustrating steps of a scan chain test method in another embodiment;

FIG. 8 is a flowchart showing the steps of a scan chain test method in another embodiment;

FIG. 9 is a diagram showing a target clock delay distribution of registers in a scan chain test method in another embodiment;

FIG. 10 is a diagram showing a comparison of clock delay distributions in a scan chain test method in another embodiment;

FIG. 11 is a table showing a comparison of clock delay distributions in a scan chain test method in another embodiment;

FIG. 12 is a flowchart showing the steps of a scan chain test method in another embodiment;

FIG. 13 is a block diagram showing a configuration of a scan chain test apparatus in one embodiment;

FIG. 14 is a block diagram showing a configuration of a scan chain test apparatus in one embodiment;

FIG. 15 is a diagram illustrating an internal structure of one embodiment of a computer device in the form of a server;

FIG. 16 is a diagram that illustrates an internal structure of a computer device that is a terminal according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that in the method for testing a scan chain provided in the embodiment of the present application, an execution main body of the method may be a device for testing a scan chain, and the device for testing a scan chain may be implemented as part or all of a computer device in a software, hardware, or a combination of software and hardware, where the computer device may be a server or a terminal, where the server in the embodiment of the present application may be one server or a server cluster composed of multiple servers, and the terminal in the embodiment of the present application may be another intelligent hardware device such as a smart phone, a personal computer, a tablet computer, a wearable device, and an intelligent robot. In the following method embodiments, the execution subject is a computer device as an example.

In an embodiment of the present application, a scan chain testing method is provided, as shown in fig. 2, which is described by taking the method as an example applied to a computer device, and includes the following steps:

and 201, acquiring initial clock delay and clock delay range of each register in the target physical area.

Specifically, the computer device may analyze the positions of the power source ground bumps of the chip, and divide the chip into a plurality of groups of rectangular physical regions RECTi with equal areas in the range of each group of VDD/VSS bumps, where the logic in the physical regions is mainly powered by the group of bumps, as shown in fig. 3.

Taking one of the physical areas as a target physical area, optionally, the computer device may test each register in the target physical area, so as to obtain an initial clock delay of each register; optionally, the computer device may further determine the initial clock delay of each register according to the attribute information of each register. The initial clock skew and the distribution of the initial clock delay of each register in this range are obtained, as shown in fig. 4, the initial clock delay skew of all registers is 0.9ns to 1.2ns (ordinate), the clock skew is 0.3ns, that is, all registers will complete the flip within 0.3 ns.

In an optional implementation manner, after the initial clock delay of each register in the target physical region is obtained, on the premise that no timing violation is generated, the computer device may calculate, according to the initial clock delay of each register, a clock delay range after the initial clock delay of each register is shifted forward and backward, in consideration of the influence of the front-stage timing and the rear-stage timing of each register.

In an alternative embodiment, the computer device may further receive clock delay ranges corresponding to registers sent by other devices.

In an alternative embodiment, if the timing path of the previous and subsequent stages of the selected register crosses the current target physical region, the corresponding clock delay range of the register is halved.

For example, please refer to fig. 4. For example, the initial clock delay of the FF0 register is 1.17ns in the FF0 register in fig. 4, and when the initial clock delay of the FF0 register is reduced, the initial clock delay will inevitably affect the timing of the front and rear stages of the FF0 register, for example, the next stage hold timing and the last stage setup timing are deteriorated, and a timing violation will be generated if the timing is deteriorated to a certain extent, which needs to be avoided. After performing maximum and minimum offset analysis on the initial clock delay of each register in the target physical region, the computer device may obtain the clock delay ranges of all registers, as shown in fig. 5, where a circle in fig. 5 represents the initial clock delay corresponding to each register, and a vertical line represents the clock delay range corresponding to each register. Taking the register FF0 as an example, the clock delay of the FF0 register extends from 1.17ns to 1.15ns to 1.25ns, and no timing violation of the preceding and following stage timing paths is caused in the clock delay range.

And 202, adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register.

In an optional implementation manner, the computer device may sequence the clock delay ranges, and adjust each initial clock delay corresponding to each register according to the result of the sequencing on the basis of ensuring that the corresponding clock delay range of each register is the largest, to obtain a target clock delay corresponding to each register.

In another alternative embodiment, the computer device may take a median value in each clock delay range as the target clock delay corresponding to each register. Therefore, the deviation between the target clock delays corresponding to the registers can be ensured to be large.

And 203, completing the scan chain test on the target physical area according to the target clock delay corresponding to each register.

Specifically, after the target clock delay corresponding to each register is obtained, the computer device completes the scan chain test on the target physical region according to the target clock delay corresponding to each register.

In an embodiment of the present application, as shown in fig. 6, the "adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register" in the above step 202 may include the following steps:

it should be noted that, in the embodiment of the present application, a method for adjusting each initial clock delay corresponding to each register includes: after the clock delay ranges (shown in fig. 5) corresponding to all registers in the target physical region are obtained, the target clock delay of each register can be calculated through several round-robin analyses. The purpose of each round of analysis and calculation is to select two registers from registers of each round of undetermined clock delay, so that the clock delay is selected to be a reasonable maximum value and a reasonable minimum value, the target clock delay of the registers of the number of the subsequent rounds is within the two clock delay ranges, and finally the clock delay distribution of all the registers is ensured to be the most even.

The maximum and minimum values of the clock delay are determined from the respective clock delay ranges 601.

Specifically, the computer device may select an undetermined target clock delay register set from all registers, and obtain a maximum value T (max, i) and a minimum value T (min, i) of a current round, where i is a round number (all variable symbols i below represent the round number), where the maximum value T (max, i) and the minimum value T (min, i) of the current round cover all register clock delay ranges in the undetermined target clock delay register set.

If the current cycle is the first cycle, the target clock delay register set is not determined to be all registers, and the computer equipment determines the maximum value and the minimum value from the clock delay ranges corresponding to all registers.

Exemplarily, as shown in fig. 5, wherein the maximum value T (max, 1) = 1.55ns, T (min, 1) = 0.63ns in the first round.

And 602, calculating the corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value.

Specifically, the computer sets the maximum value as the target clock delay corresponding to the register with the largest clock delay among all registers, and sets the minimum value as the target clock delay corresponding to the register with the smallest clock delay among all registers.

Assuming that the clock delay step of the current round is calculated, the clock delay step of the current round is obtained by dividing the difference between the maximum value and the minimum value selected in the current round by the number of steps needing to be evenly distributed, and the clock delay step = (maximum value-minimum value)/(number of FFs with undetermined clock delay + 1).

And then the computer subtracts the corresponding clock delay step length from the maximum value to obtain the alternative clock delay corresponding to each register. Or the computer sets the minimum value and the corresponding clock delay step length to obtain the alternative clock delay corresponding to each register.

603, determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

Specifically, the computer device may determine the target clock delays corresponding to the two registers from all the registers according to the maximum value and the minimum value.

And then comparing each alternative clock delay with each clock delay range corresponding to each alternative clock delay, and determining the target clock delay corresponding to each register according to the comparison result.

In an embodiment of the present application, as shown in fig. 7, the step 203 of determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each candidate clock delay, and each clock delay range may include the following steps:

701, determining a first register corresponding to the maximum value, and determining that the maximum value is a target clock delay corresponding to the first register.

Specifically, the computer device may determine, according to the maximum value, a clock delay range corresponding to the maximum value, then determine, according to the clock delay range, a first register corresponding to the maximum value, and determine that the maximum value is a target clock delay corresponding to the first register.

And 702, determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register.

Specifically, the computer device may determine, according to the minimum value, a clock delay range corresponding to the minimum value, then determine, according to the clock delay range, a second register corresponding to the minimum value, and determine that the minimum value is a target clock delay corresponding to the second register.

703, determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

Specifically, the computer device may compare each candidate clock delay with each clock delay range corresponding to each candidate clock delay, and determine the target clock delay corresponding to each register according to the comparison result.

Specifically, if the candidate clock delays are within the corresponding clock delay range, determining the candidate clock delays as the target clock delays of the registers corresponding to the candidate clock delays. And if the alternative clock delays are out of the corresponding clock delay ranges, determining the maximum clock delay or the minimum clock delay in the clock delay ranges as the target clock delay of each register.

In an embodiment of the present application, as shown in fig. 8, the "determining target clock delays corresponding to the remaining registers according to the alternative clock delays and the clock delay ranges" in step 703 may include the following steps:

and 810, sequencing the alternative clock delays from large to small, and determining the alternative clock delay with the second sequence and the alternative clock delay with the second last sequence.

Specifically, after the computer device calculates the candidate clock delays by using the maximum value and the minimum value, the candidate clock delays are sorted from large to small. Then, the second alternative clock delay and the second last alternative clock delay are determined.

Illustratively, assuming that the maximum value is 1.55ns, the minimum value is 0.63ns, and the number of registers is 20, the clock delay step calculated by the computer device according to the maximum value and the minimum value = (1.55ns-0.63ns)/(18+1) = 0.048ns, and then 1.55ns-0.048ns = 1.50 ns; 0.63ns + 0.048ns = 0.68 ns. It can be seen that the second-ranked candidate clock delay is 1.50ns, and the second-last candidate clock delay is 0.68 ns.

802, determining a second large value and a second small value of the clock delay according to each clock delay range,

and determining a third register and a fourth register according to the second large value and the second small value.

Specifically, the computer device determines a second large value and a second small value of the clock delay within the clock delay range corresponding to the other registers except the first register and the second register.

The computer device may determine a clock delay range corresponding to the second large value according to the second large value, and then determine a third register corresponding to the second large value according to the clock delay range.

The computer device may further determine a clock delay range corresponding to the second small value according to the second small value, and then determine a fourth register corresponding to the second small value according to the clock delay range.

And 803, comparing the second alternative clock delay with the second maximum value, and determining the target clock delay corresponding to the third register according to the comparison result.

Specifically, the computer device compares the second alternative clock delay with the second maximum value, and determines the target clock delay corresponding to the third register according to the comparison result.

And 804, comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

Specifically, the computer device compares the alternative clock delay with the second minimum value, and determines the target clock delay corresponding to the fourth register according to the comparison result.

In an embodiment of the present application, the "determining the target clock delay corresponding to the third register according to the comparison result" in the step 803 may include the following steps:

in one case, if the delay of the second candidate clock is greater than or equal to the second maximum value, the second maximum value is determined as the target clock delay corresponding to the third register.

Specifically, the computer device compares the second alternative clock delay with the second large value, and if the second alternative clock delay is greater than or equal to the second large value, the computer device determines that the second alternative clock is not within the clock delay range corresponding to the third register, and in order to avoid generating an influence on the front-rear stage timing of the register, the computer device determines the second large value as the target clock delay corresponding to the third register.

Exemplarily, as can be seen from fig. 5, the second maximum value is 1.43ns, the second candidate clock delay is 1.50ns, and the second candidate clock delay is greater than or equal to the second maximum value, then the computer device determines that the second candidate clock delay is not within the clock delay range corresponding to the second third register, and therefore, the second maximum value is determined as the target clock delay corresponding to the third register.

In another case, if the second alternative clock delay is smaller than the second maximum value, the second alternative clock delay is determined as the target clock delay corresponding to the third register.

Specifically, the computer device compares the candidate clock delay of the second rank with the second large value, and if the candidate clock delay of the second rank is smaller than the second large value, the computer device determines that the candidate clock of the second rank is within the clock delay range corresponding to the third register, and the clock delay deviation between the candidate clock delay of the second rank and the first register is larger, so that, in order to reduce the inversion of each register in a short time, the computer device may determine the candidate clock delay of the second rank as the target clock delay corresponding to the third register.

In an embodiment of the present application, the "determining the target clock delay corresponding to the fourth register according to the comparison result" in the step 804 may include the following steps:

in one case, if the delay of the candidate clock with the second from last is greater than or equal to the second small value, the delay of the candidate clock with the second from last is determined as the target clock delay corresponding to the fourth register.

Specifically, the computer device compares the candidate clock delay of the second from last to last in the sequence with the second small value, and if the candidate clock delay of the second from last in the sequence is greater than or equal to the second small value, the computer device determines that the candidate clock of the second from last in the sequence is within the clock delay range corresponding to the fourth register, and the clock delay deviation between the candidate clock delay of the second from last in the sequence and the second register is larger, so that, in order to reduce the inversion of each register in a short time, the computer device may determine the candidate clock delay of the second from last in the sequence as the target clock delay corresponding to the fourth register.

In another case, if the delay of the alternative clock with the second from last in the sequence is smaller than the second small value, the second small value is determined as the target clock delay corresponding to the fourth register.

Specifically, the computer device compares the candidate clock delay of the second from last to last with the second small value, and if the candidate clock delay of the second from last to last is smaller than the second small value, the computer device determines that the candidate clock of the second from last to last is not in the clock delay range corresponding to the fourth register, and in order to avoid generating the influence of the front and rear stage timings of the register, the computer device determines the second small value as the target clock delay corresponding to the fourth register.

In this embodiment of the present application, the above steps are cycled for multiple times until the target clock delay of each register is obtained after the initial clock delays corresponding to all registers are adjusted.

Taking 20 registers FF0-FF19 in the target physical region as an example, the initial clock delay before adjustment is compared to the target clock delay after recalculation for each register as shown in Table 1.

	Initial clock delay	Target clock delay
			FF0	1.17	1.19
FF1	1.20	1.39
			FF2	0.96	0.77
FF3	1.10	1.27
			FF4	1.02	1.06
FF5	1.00	1.01
			FF6	0.92	0.89
FF7	1.14	1.23
			FF8	1.10	1.43
FF9	0.91	0.72
			FF10	1.04	0.93
FF11	0.95	0.81
			FF12	0.91	0.85
FF13	0.90	0.63
			FF14	1.05	1.31
FF15	1.17	1.55
			FF16	1.11	1.15
FF17	1.16	1.35
			FF18	1.07	1.10
FF19	1.05	0.97

As shown in fig. 9, the dots in fig. 9 indicate the target clock delays corresponding to the registers after adjustment, and the vertical lines in fig. 9 indicate the clock delay ranges corresponding to the registers.

In fig. 10, the first row of dots represents the target clock delay distribution corresponding to each register after adjustment, and the second row of dots represents the initial clock delay distribution corresponding to each register before adjustment, and as can be seen from fig. 10, the target clock delay distribution deviation of the registers becomes large, and the number of registers that are inverted in a short time is reduced, so the instantaneous power of the chip is reduced.

In one embodiment of the present application, illustratively, wherein FF characterizes a register. Firstly, performing a first round of analysis and calculation, selecting all FFs as undetermined clock delay FF sets, and taking the maximum value and the minimum value of all FF clock delay offset ranges covering all the undetermined clock delay FF sets to obtain the maximum clock delay T (max, i) of the round and the minimum clock delay T (min, i) of the round, wherein i is the round number (all variable symbols i below represent the round number). Taking fig. 5 as an example, T (max, 1) = 1.55ns, and T (min, 1) = 0.63 ns. The FF (FF 15) with the maximum clock delay offset equal to T (max, 1) is taken and its clock delay is determined to be 1.55ns, denoted as the current round selected maximum clock delay T (max _ sel, 1), and the FF (FF 13) with the minimum clock delay offset equal to T (min, 1) is taken and its clock delay is determined to be 0.63ns, denoted as the current round selected minimum clock delay T (min _ sel, 1). The two FFs (FF 15 and FF 13) for the current round of determined clock delays are removed from the set of undetermined clock delay FFs. The calculated clock delay widest offset distribution of the undetermined clock delays FF is updated simultaneously (similar to fig. 5, the following example assumes that the widest offset distribution is unchanged).

The clock delay step T (step, 1) of the current round is calculated, the clock delay step of the current round is the maximum minimum clock delay difference selected in the current round divided by the number of steps needing to be evenly distributed, T (step, 1) = (T (max _ sel, 1) -T (min _ sel, 1))/(FF number of undetermined clock delay +1), and taking fig. 5 as an example, T (step, 1) = (1.55ns-0.63ns)/(18+1) = 0.048 ns).

The next round of analysis calculation is performed, and the maximum search clock delay T (max _ search, 2) and the minimum search clock delay T (min _ search, 2) of the present round are calculated, T (max _ search, 2) = T (max _ sel, 1) -T (step, 1), T (min _ search, 2) = T (min _ sel, 1) + T (step, 1), taking fig. 5 as an example, T (max _ search, 2) = 1.55ns-0.048ns = 1.50ns, and T (min _ search, 2) = 0.63ns + 0.048ns = 0.68 ns.

The maximum value and the minimum value of all FF clock delay offset ranges in all undetermined clock delay FF sets are selected to obtain the maximum clock delay T (max, 2) of the current round and the minimum clock delay T (min, 2) of the current round, which are 1.43ns and 0.72ns as an example in fig. 5.

The local maximum search clock delay T (max _ search, 2) is compared with the local maximum clock delay T (max, 2). When T (max _ search, 2) > = T (max, 2), directly selecting the FF with the maximum clock delay offset equal to T (max, 2) and determining the clock delay as T (max, 2), and simultaneously recording as the current round of selecting the maximum clock delay T (max _ sel, 2), when T (max _ search, 2) < T (max, 2), selecting the FF with the maximum value of the clock delay offset larger than T (max _ search, 2) and determining the clock delay of the FF as T (max _ search, 2), and recording the FF as the current round of the selected maximum clock delay T (max _ sel, 2), if a plurality of FFs meet the condition, the FF with the narrowest clock delay offset range is selected and removed out of the undetermined set of clock delay FFs, and taking FIG. 5 as an example, the FF is FF8, and the clock delay of the FF is determined to be 1.43 ns. The calculated clock delay widest offset distribution of the undetermined clock delays FF is updated simultaneously (similar to fig. 5, the following example assumes that the widest offset distribution is unchanged).

Comparing the minimum search clock delay T (min _ search, 2) of the current round with the minimum clock delay T (min, 2) of the current round, when T (min _ search, 2) < = T (min, 2), directly selecting the FF with the minimum clock delay offset equal to T (min, 2) and determining the clock delay as T (min, 2), and simultaneously recording the FF as the minimum clock delay T (min _ sel, 2) of the current round, if a plurality of FFs meet the condition, selecting the FF with the narrowest clock delay offset range, and removing the FF with the undetermined clock delay FF range. When T (min _ search, 2) > T (min, 2), selecting the FF with the minimum value of the self clock delay offset smaller than T (min _ search, 2) and determining the clock delay as T (min _ search, 2), and simultaneously recording the FF as the current round of selecting the minimum clock delay T (min _ sel, 2), if a plurality of FFs meet the condition, selecting the FF with the narrowest self clock delay offset range and removing the FF from the set of undetermined clock delays. Taking fig. 5 as an example, this FF is FF9, whose clock delay is determined to be 0.72 ns. The calculated clock delay widest offset distribution of the undetermined clock delays FF is updated simultaneously (similar to fig. 5, the following example assumes that the widest offset distribution is unchanged).

The clock delay step T (step, 2) of the current round is calculated, the clock delay step of the current round is the maximum minimum clock delay difference selected in the current round divided by the number of steps needing to be evenly distributed, T (step, 2) = (T (max _ sel, 2) -T (min _ sel, 2))/(FF number of undetermined clock delay +1), and taking fig. 5 as an example, T (step, 2) = (1.43 ns-0.72 ns)/(16 +1) =0.042 ns).

Repeating the loop of steps described above can analytically calculate the recalculated selected clock delay for all FFs. Fig. 11 lists the detailed calculation steps.

In an embodiment of the present application, the "determining the third register and the fourth register according to the second large value and the second small value" in 820 may include the following:

and judging whether the number corresponding to the second extreme value is greater than 1, wherein the second extreme value comprises a second large value and a second small value.

In one case, when the number of the second extreme values is 1, the third register or the fourth register is determined according to the clock delay range corresponding to the second extreme value.

In another case, when the number of the second extreme values is greater than 1, comparing the clock delay ranges corresponding to the second extreme values, and determining that the register with the smallest clock delay range is the third register or the fourth register.

Specifically, after the computer device determines the second extreme value, it may be determined whether the number of second extreme values is 1. And under the condition that the number of the second extreme values is 1, the computer equipment determines the corresponding clock delay range of the second extreme values, and determines the third register or the fourth register according to the corresponding clock delay range of the second extreme values.

And when the number of the second extreme values is larger than 1, the computer equipment acquires the clock delay ranges corresponding to the second extreme values, compares the clock delay ranges to determine a minimum clock delay range, and determines the register corresponding to the minimum clock delay range as a third register or a fourth register.

For example, the second extreme value is taken as the second maximum value for explanation. After the computer device determines the second largest value, it may be determined whether the number of second largest values is 1. And under the condition that the number of the second large values is 1, the computer equipment determines the corresponding clock delay range of the second large values, and determines the third register according to the corresponding clock delay range of the second large values. And when the number of the second large values is larger than 1, the computer equipment acquires the clock delay ranges corresponding to the second large values, compares the clock delay ranges to determine a minimum clock delay range, and determines the register corresponding to the minimum clock delay range as a third register.

In order to better explain the scan chain testing method provided in the embodiment of the present application, as shown in fig. 12, an overall flowchart of the scan chain testing method provided in the embodiment of the present application may include the following steps:

1201, the initial clock delay and the clock delay range of each register in the target physical area are obtained.

1202, maximum and minimum values of clock delays are determined from within each clock delay range.

1203, calculating corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value.

And 1204, determining a first register corresponding to the maximum value, and determining the maximum value as a target clock delay corresponding to the first register.

1205, determining a second register corresponding to the minimum value, and determining the minimum value as a target clock delay corresponding to the second register.

1206, sequencing the alternative clock delays from large to small, and determining the alternative clock delay with the second sequence and the alternative clock delay with the second last sequence.

1207, according to each clock delay range, determining a second large value and a second small value of the clock delay, and according to the second large value and the second small value, determining a third register and a fourth register.

1208, comparing the second ordered candidate clock delay to the second largest value.

1209, judging whether the delay of the alternative clock of the second sorting is larger than or equal to a second large value, if so, executing 1210; if not, 1211 is performed.

And 1210, determining the second largest value as the target clock delay corresponding to the third register.

1211 determines the second alternative clock delay as the target clock delay corresponding to the third register.

1212, the second last alternative clock delay of the sequence is compared to the second small value.

1213, judging whether the time delay of the alternative clock with the second from last is larger than or equal to the second small value, if yes, executing 1214; if not, 1215 is performed.

1214, determining the clock delay alternative with the second to last ordering as the target clock delay corresponding to the fourth register.

1215, determining the second small value as the target clock delay corresponding to the fourth register.

It should be understood that although the various steps in the flowcharts of fig. 2, 6-8 and 12 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2, 6-8, and 12 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or at least partially with other steps or with at least some of the other steps.

Accordingly, referring to fig. 13, an embodiment of the present invention provides a scan chain testing apparatus 1300, where the scan chain testing apparatus 1300 includes:

the obtaining module 1310 is configured to obtain an initial clock delay and a clock delay range of each register in the target physical area.

The adjusting module 1320 is configured to adjust each initial clock delay corresponding to each register according to each clock delay range, so as to obtain a target clock delay corresponding to each register.

A completing module 1320, configured to complete scan chain testing on the target physical area according to the target clock delay corresponding to each register.

In an embodiment of the present application, as shown in fig. 14, the adjusting module 1320 includes:

a first determining unit 1321, configured to determine a maximum value and a minimum value of the clock delay from each clock delay range.

The calculating unit 1322 is configured to calculate, according to the maximum value and the minimum value, each candidate clock delay corresponding to each register when the clock delay time intervals are equal.

And a second determining unit 1323, configured to determine the target clock delay corresponding to each register according to the maximum value, the minimum value, each candidate clock delay, and each clock delay range.

In an embodiment of the application, the second determining unit 1323 is specifically configured to determine the first register corresponding to the maximum value, and determine the maximum value as the target clock delay corresponding to the first register; determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register; and determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

In an embodiment of the present application, the second determining unit 1323 is specifically configured to sort the candidate clock delays from large to small, and determine a second candidate clock delay and a second last candidate clock delay from the second candidate clock delays; determining a second large value and a second small value of the clock delay according to each clock delay range, and determining a third register and a fourth register according to the second large value and the second small value; comparing the second alternative clock delay with the second large value, and determining the target clock delay corresponding to the third register according to the comparison result; and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

In an embodiment of the application, the second determining unit 1323 is specifically configured to determine, if the candidate clock delay of the second sorting candidate is greater than or equal to a second large value, the second large value as the target clock delay corresponding to the third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

In an embodiment of the application, the second determining unit 1323 is specifically configured to determine, if the delay of the candidate clock with the second from last rank is greater than or equal to a second small value, the delay of the candidate clock with the second from last rank is determined as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

In an embodiment of the application, the second determining unit 1323 is specifically configured to determine whether the number corresponding to the second extreme value is greater than 1, where the second extreme value includes a second large value and a second small value; when the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 15. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a scan chain testing method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 16. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing scan chain test data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a scan chain testing method.

It will be appreciated by those skilled in the art that the configurations shown in fig. 15 and 16 are block diagrams of only some of the configurations relevant to the present application, and do not constitute a limitation on the computing devices to which the present application may be applied, and that a particular computing device may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment of the present application, there is provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the following steps when executing the computer program: acquiring initial clock delay and clock delay ranges of registers in a target physical region; adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register; and completing scan chain test on the target physical area according to the target clock delay corresponding to each register.

In one embodiment of the application, the processor when executing the computer program further performs the following steps: determining the maximum value and the minimum value of the clock delay from each clock delay range; calculating the corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value; and determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

In one embodiment of the application, the processor when executing the computer program further performs the following steps: determining a first register corresponding to the maximum value, and determining that the maximum value is the target clock delay corresponding to the first register; determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register; and determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

In one embodiment of the application, the processor when executing the computer program further performs the following steps:

sequencing the alternative clock delays from large to small, and determining alternative clock delay with the second sequence and alternative clock delay with the second to last sequence; determining a second large value and a second small value of the clock delay according to each clock delay range, and determining a third register and a fourth register according to the second large value and the second small value; comparing the second alternative clock delay with the second large value, and determining the target clock delay corresponding to the third register according to the comparison result; and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

In one embodiment of the application, the processor when executing the computer program further performs the following steps: if the delay of the second alternative clock is greater than or equal to a second large value, determining the second large value as the target clock delay corresponding to the third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

In one embodiment of the application, the processor when executing the computer program further performs the following steps: if the delay of the alternative clock with the second from last in the sequence is larger than or equal to a second small value, determining the delay of the alternative clock with the second from last in the sequence as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

In one embodiment of the application, the processor when executing the computer program further performs the following steps: judging whether the number corresponding to the second extreme value is greater than 1, wherein the second extreme value comprises a second large value and a second small value; when the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register.

In one embodiment of the present application, there is provided a computer readable storage medium having a computer program stored thereon, the computer program when executed by a processor implementing the steps of: acquiring initial clock delay and clock delay ranges of registers in a target physical region; adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register; and completing scan chain test on the target physical area according to the target clock delay corresponding to each register.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: determining the maximum value and the minimum value of the clock delay from each clock delay range; calculating the corresponding alternative clock delays of the registers under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value; and determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: determining a first register corresponding to the maximum value, and determining that the maximum value is the target clock delay corresponding to the first register; determining a second register corresponding to the minimum value, and determining the minimum value as the target clock delay corresponding to the second register; and determining target clock delays corresponding to the other registers according to the alternative clock delays and the clock delay ranges.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of:

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: if the delay of the second alternative clock is greater than or equal to a second large value, determining the second large value as the target clock delay corresponding to the third register; and if the alternative clock delay of the second sequencing is smaller than a second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: if the delay of the alternative clock with the second from last in the sequence is larger than or equal to a second small value, determining the delay of the alternative clock with the second from last in the sequence as the target clock delay corresponding to the fourth register; and if the delay of the alternative clock with the second last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: judging whether the number corresponding to the second extreme value is greater than 1, wherein the second extreme value comprises a second large value and a second small value; when the number of the second extreme values is 1, determining a third register or a fourth register according to the clock delay range corresponding to the second extreme values; and when the number of the second extreme values is larger than 1, comparing each clock delay range corresponding to each second extreme value, and determining the register with the minimum clock delay range as a third register or a fourth register.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, and the program can be stored in a computer readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the kind described above.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A scan chain testing method, the method comprising:

acquiring initial clock delay and clock delay ranges of registers in a target physical region;

adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register;

and completing scan chain test on the target physical area according to the target clock delay corresponding to each register.

2. The method of claim 1, wherein the adjusting each initial clock delay corresponding to each register according to each clock delay range to obtain a target clock delay corresponding to each register comprises:

determining the maximum value and the minimum value of the clock delay from each clock delay range;

calculating the corresponding alternative clock delay of each register under the condition that the clock delay time intervals are equal according to the maximum value and the minimum value;

and determining the target clock delay corresponding to each register according to the maximum value, the minimum value, each alternative clock delay and each clock delay range.

3. The method of claim 2, wherein determining a target clock delay for each register based on the maximum value, the minimum value, each candidate clock delay, and each clock delay range comprises:

determining a first register corresponding to the maximum value, and determining the maximum value as a target clock delay corresponding to the first register;

determining a second register corresponding to the minimum value, and determining the minimum value as a target clock delay corresponding to the second register;

and determining target clock delays corresponding to the rest of registers according to the alternative clock delays and the clock delay ranges.

4. The method of claim 3, wherein determining the target clock delays for the remaining registers based on the alternative clock delays and the clock delay ranges comprises:

sequencing the alternative clock delays from large to small, and determining alternative clock delay with the second sequencing and alternative clock delay with the second to last sequencing;

determining a second large value and a second small value of the clock delay according to each of the clock delay ranges,

determining a third register and a fourth register according to the second large value and the second small value;

comparing the second alternative clock delay with the second maximum value, and determining the target clock delay corresponding to the third register according to the comparison result;

and comparing the alternative clock delay with the second minimum value, and determining the target clock delay corresponding to the fourth register according to the comparison result.

5. The method of claim 4, wherein determining the target clock delay corresponding to the third register according to the comparison result comprises:

if the alternative clock delay of the second sequencing is greater than or equal to the second large value, determining the second large value as the target clock delay corresponding to the third register;

and if the alternative clock delay of the second sequencing is smaller than the second large value, determining the alternative clock delay of the second sequencing as the target clock delay corresponding to the third register.

6. The method of claim 4, wherein determining the target clock delay corresponding to the fourth register according to the comparison result comprises:

if the alternative clock delay of the second from last in the sequence is greater than or equal to the second small value, determining the alternative clock delay of the second from last in the sequence as the target clock delay corresponding to the fourth register;

and if the alternative clock delay of the last to last order is smaller than the second large value, determining the second small value as the target clock delay corresponding to the fourth register.

7. The method of claim 4, wherein determining a third register and a fourth register based on the second large value and the second small value comprises:

judging whether the number corresponding to a second extreme value is greater than 1, wherein the second extreme value comprises a second large value and a second small value;

when the number of the second extreme values is 1, determining the third register or the fourth register according to the clock delay range corresponding to the second extreme values;

when the number of the second extreme values is greater than 1, comparing the clock delay ranges corresponding to the second extreme values, and determining that the register with the smallest clock delay range is the third register or the fourth register.

8. A scan chain test apparatus, the apparatus comprising:

9. A computer device, comprising: a memory and a processor, the memory and the processor being communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the scan chain testing method of any of claims 1-7.

10. A computer-readable storage medium storing computer instructions for causing a computer to perform the scan chain testing method of any of claims 1-7.