CN113904938B - A system and method for dynamically configuring PCIe terminal equipment - Google Patents

Abstract

The present invention provides a system and method for dynamically configuring PCIe terminal equipment. The system includes: a PCIe virtualization module, an external debugger and an embedded processor. By simulating a PCIe switch device, it further simulates multiple downstream ports connected to it. terminal equipment, and provide external debuggable and internal programmable development support, realize the dynamic configuration and unified management of PCIe terminal equipment through the simulation of PCIe switch; external debugging interface, internal embedded processor and programmable state machine, The method of joint control by stages and tasks effectively meets the needs of comprehensive, flexible, real-time response and processing of PCIe transaction layer messages under debugging, application, update, and abnormal conditions; IO processing in the PCIe virtualization module The corresponding function design in the module supports two IO operation modes of device IO and host IO, which improves the efficiency of IO operation.

Description

A system and method for dynamically configuring PCIe terminal equipment

technical field

The invention relates to the field of cloud computing, in particular to a system and method for dynamically configuring PCIe terminal equipment.

Background technique

In the current data center application scenarios, elastic bare metal servers gradually occupy a larger proportion, and users rent physical servers in an elastic manner similar to cloud services. Different from the traditional server leasing model, elastic bare metal servers not only provide complete IO resources, but also have the flexibility and configurability of cloud services. The user's dynamic configuration of IO resources such as network devices, storage devices, and computing acceleration devices will take effect immediately on the leased elastic bare metal server.

The multiplexing of PCIe terminal devices mostly adopts the SR-IOV (Single Root I/O Virtualization) method, and uses a PF (Physical Functions, physical function) as a template to virtualize multiple VFs (Virtual Functions, virtual functions), from the terminal device. Angular provides virtualization support with the efficiency of hardware implementation. Since it starts from the hardware point of view, it lacks the requirements for dynamic and flexible configuration of terminal device attributes and quantity in virtualization management. The number and attributes of its devices are set statically and cannot be modified online. If a VF is modified, it will affect all VFs under the same PF, and cannot meet the requirement that the dynamic configuration of PCIe devices of the elastic bare metal server takes effect immediately. In addition, when supporting the dynamic configuration of PCIe devices in data center application scenarios based on elastic bare metal servers, how to improve the efficiency of IO processing is also an urgent problem to be solved.

SUMMARY OF THE INVENTION

In view of this, the purpose of the embodiments of the present invention is to provide a medical text entity labeling method and system, specifically including:

In a first aspect, an embodiment of the present invention provides a system for dynamically configuring PCIe terminal devices, where the system includes:

The PCIe virtualization module is configured to receive a PCIe configuration request message sent by the host when the host scans PCIe terminal devices downstream of the system, and reply a configuration response message to the configuration request message; and is used to receive the PCIe configuration request message. PCIe IO request message sent by the host, and reply IO response message to the configuration request message; wherein, the PCIe IO request message includes the BAR address space memory read and write request corresponding to the downstream PCIe terminal device;

An external debugger, connected to the PCIe virtualization module through the debug interface provided by the PCIe virtualization module, and used to replace the PCIe virtualization module with the debug interface provided by the PCIe virtualization module during startup to perform PCIe Debugging of configuration and IO call; and for modifying the program for supporting the PCIe terminal device of the target type in the PCIe virtualization module after the debugging of the PCIe terminal device of the target type is completed;

The embedded processor is configured to negotiate with an external configuration management server to generate the configuration response message, and determine the generation sequence of a plurality of the configuration response messages.

Optionally, the PCIe virtualization module includes:

The PCIe transaction layer message distributor is used to parse the PCIe transaction layer message received from the PCIe link layer, and configure the transaction request message according to the PCIe configuration transaction request message or according to the message header information of the PCIe transaction layer message. PCIe IO transaction request message, send the PCIe configuration transaction request message or PCIe IO transaction request message to the corresponding configuration processing module or IO processing module respectively; PCIe transaction layer messages are distributed to the PCIe link layer;

a debugging interface, connected with the external debugger, for sending and receiving PCIe transaction layer messages instead of the PCIe transaction layer message distributor when the external debugger is started;

a configuration processing module, configured to receive a configuration message, and complete the update of the PCIe terminal device according to the configuration message;

An IO processing module, configured to receive a PCIe IO request message, and control the PCIe virtualization module and/or at least one PCIe terminal device to perform control status register access and direct memory access according to the PCIe IO request message.

Optionally, the configuration processing module includes:

The configuration packet sending and receiving interface is used to receive the PCIe configuration transaction request packet distributed by the PCIe transaction layer packet distributor, and send the configuration transaction response packet received from the programmable hardware state machine or the CPU configuration processing interface;

The CPU configuration processing interface is used to receive the PCIe configuration transaction request message forwarded by the configuration message transceiver interface, and send the configuration transaction response message received from the embedded processor;

The programmable hardware state machine is used to receive and parse the PCIe configuration transaction request message forwarded by the configuration message transceiver interface, and send a pre-programmed configuration transaction response message according to the parsed content;

The state machine micro-sequence program storage unit is used to store the instructions and data of the programmable hardware state machine, and the instructions and data are written in or read out from the CPU configuration processing interface.

Optionally, the IO processing module includes:

The target IO message sending and receiving interface is used to receive the PCIe IO transaction request message forwarded by the PCIe transaction layer message distributor, and parse it into a BAR address space memory read and write request; and used to encapsulate the memory read and write response returned by the CSR module into The IO transaction response message is sent to the PCIe transaction layer message distributor;

The CSR module is configured to receive the read and write request of the BAR address space memory sent by the target IO message sending and receiving interface, obtain the corresponding read and write request content according to the BAR address space memory read and write request, and send it to the target IO message sending and receiving interface.

Optionally, the CSR module includes:

The BAR address space mapping management interface is used to provide the BAR address corresponding to the target function of the corresponding PCIe terminal device after receiving the read and write request of the BAR address space memory;

The BAR address space memory is used to save and provide the contents of the BAR address space.

Optionally, the CSR module also includes a BAR specific address access trigger, for when the target BAR address is accessed, triggering the programmable state machine of the IO processing module to run the BAR address space memory update program and the DMA request program;

Correspondingly, the IO processing module further includes:

The programmable state machine is used to respond to the BAR specific address access trigger signal sent by the BAR specific address access trigger, and send the BAR address space memory update information to the CSR module; it is also used to send a DMA request to the DMA module and receive the DMA module's complete response;

The initial IO message sending and receiving interface is used to receive the host memory address space memory read and write requests sent by the DMA module, and encapsulate the host memory address space memory read and write requests into IO transaction request messages, and send them to the PCIe transaction layer to report It is used to parse the IO transaction response message returned by the PCIe transaction layer message distributor into the host memory address space memory read and write response and send it to the DMA module;

The DMA module is used to respond to the DMA request of the programmable state machine, initiate command acquisition DMA or data transfer DMA operations, and send host memory address space memory read and write requests to the initial IO message transceiver interface; The host memory address space memory read and write response content received by the interface is written to the command buffer or data buffer.

In a second aspect, an embodiment of the present invention provides a method for dynamically configuring a PCIe terminal device, which is applied to the system described in the first aspect, wherein the method includes:

The PCIe virtualization module of the system receives the PCIe configuration request message sent by the host when the host scans the PCIe terminal equipment downstream of the system;

The configuration processing module of the PCIe virtualization module replies with a PCIe configuration response message to the PCIe configuration request message, wherein the configuration response message is generated by negotiation between the embedded processor of the system and an external configuration management server, The generation sequence of a plurality of the configuration response messages is determined by the embedded processor;

The PCIe virtualization module of the system receives a PCIe IO request message sent by the host, wherein the PCIe IO request message includes a BAR address space memory read and write request corresponding to a downstream PCIe terminal device;

The IO processing module of the PCIe virtualization module replies with an IO response message to the PCIe IO request message, where the IO response message includes the content stored in the BAR address space memory.

Optionally, the method further includes:

When the target BAR address is accessed, the programmable state machine of the IO processing module is triggered to run the BAR address space memory update procedure and the DMA request procedure.

Optionally, the method further includes:

start an external debugger for the system;

The external debugger performs the debugging of PCIe configuration and IO call in place of the PCIe virtualization module through the debugging interface provided by the PCIe virtualization module;

After the debugging of the PCIe terminal device of the target type is completed, modify the program in the PCIe virtualization module for supporting the PCIe terminal device of the target type.

Optionally, the method further includes:

The configuration response message is generated by the programmable state machine of the configuration processing module of the PCIe virtualization module, instead of the negotiation process between the embedded processor and the external configuration management server;

If the PCIe configuration request message is of an undefined type, the configuration response message is generated instead of the programmable state machine according to the negotiation between the embedded processor and the external configuration management server.

The system and method for dynamically configuring PCIe terminal devices provided by the embodiments of the present invention further simulate multiple terminal devices connected to downstream ports by simulating PCIe switch devices, and provide externally debuggable and internally programmable development support. The simulation of the switch realizes the dynamic configuration and unified management of the PCIe terminal equipment; the external debugging interface, the internal embedded processor and the programmable state machine adopt the method of joint control by stages and tasks, which effectively meets the requirements of debugging, application, Update, comprehensive, flexible, real-time response and processing requirements of PCIe transaction layer messages under abnormal conditions; corresponding functional design is carried out in the IO processing module in the PCIe virtualization module to support two IO operation modes of device IO and host IO, Improves the efficiency of IO operations.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some of the present application. In the embodiment, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without paying creative services. The above and other objects, features and advantages of the present application will be more apparent from the accompanying drawings. The same reference numerals refer to the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the emphasis is on illustrating the subject matter of the present application.

FIG. 1 shows a schematic structural diagram of a system for dynamically configuring a PCIe terminal device according to an embodiment of the present invention.

FIG. 2 shows a schematic structural diagram of a PCIe virtualization module provided by an embodiment of the present invention.

FIG. 3 shows a schematic structural diagram of a configuration processing module provided by an embodiment of the present invention.

FIG. 4 shows a schematic structural diagram of an IO processing module provided by an embodiment of the present invention.

FIG. 5 shows a schematic diagram of a complete structure of a system for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention.

FIG. 6 shows a schematic flowchart of a method for dynamically configuring a PCIe terminal device according to an embodiment of the present invention.

FIG. 7 shows a schematic diagram of a complete flow of a method for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention.

FIG. 8 shows a schematic flowchart of a debugging method for a PCIe terminal device provided by an embodiment of the present invention.

FIG. 9 shows a schematic flowchart of an exception processing method for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the words "a," "an," and "the" and the like shall also include the meanings of "plurality," "plurality," unless the context clearly dictates otherwise. Furthermore, the terms "comprising", "comprising" and the like used herein indicate the presence of stated features, steps, operations and/or components, but do not preclude the presence or addition of one or more other features, steps, operations or components .

All terms (including technical and scientific terms) used herein have the meaning as commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly rigid manner.

In the current data center application scenarios, elastic bare metal servers gradually occupy a larger proportion, and users rent physical servers in an elastic manner similar to cloud services. Different from the traditional server leasing model, elastic bare metal servers not only provide complete IO resources, but also have the flexibility and configurability of cloud services. The user's dynamic configuration of IO resources such as network devices, storage devices, and computing acceleration devices will take effect immediately on the leased elastic bare metal server.

The multiplexing of PCIe terminal devices mostly adopts the SR-IOV (Single Root I/O Virtualization) method, and uses a PF (Physical Functions, physical function) as a template to virtualize multiple VFs (Virtual Functions, virtual functions), from the terminal device. Angular provides virtualization support with the efficiency of hardware implementation. Since it starts from the hardware point of view, it lacks the requirements for dynamic and flexible configuration of terminal device attributes and quantity in virtualization management. The number and attributes of its devices are set statically and cannot be modified online. If a VF is modified, it will affect all VFs under the same PF, and cannot meet the requirement that the dynamic configuration of PCIe devices of the elastic bare metal server takes effect immediately. In addition, when supporting the dynamic configuration of PCIe devices in data center application scenarios based on elastic bare metal servers, how to improve the efficiency of IO processing is also an urgent problem to be solved.

In view of this, the purpose of the embodiments of the present invention is to provide a system and method for dynamically configuring a PCIe terminal device, and the contents disclosed in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic structural diagram of a system for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention, and the specific content is as follows.

The PCIe virtualization module 110 is configured to receive a PCIe configuration request message sent by the host when the host scans the PCIe terminal devices downstream of the system, and reply a configuration response message to the configuration request message; The PCIe IO request message sent by the host is sent, and an IO response message is replied to the configuration request message; wherein, the PCIe IO request message includes a read and write request of the BAR address space memory corresponding to the downstream PCIe terminal device.

Due to the existing technology based on the elastic bare metal server data center application scenario, the technology that provides virtualization support for the multiplexing of PCIe terminal devices from the perspective of hardware, the existing virtualization management cannot dynamically and flexibly configure the attributes and number of terminal devices. As for the problem of support, the system for dynamically configuring PCIe terminal devices in this embodiment of the present invention is a software function system set on the device.

The system for dynamically configuring PCIe terminal equipment is composed of three main modules, a PCIe virtualization module 110 , an external debugger 120 and an embedded processor 130 . The PCIe virtualization module 110 can not only simulate the function of the PCIe switch device in software, but also can further simulate multiple terminal devices connected to its downstream ports.

When the host boots up, the topology of downstream PCIe devices is scanned during the PCIe enumeration phase. When the device where the system is located, the PCIe virtualization module will respond as a PCIe switch; the host further scans the PCIe devices downstream of the device, and the PCIe virtualization module will respond instead of the virtual downstream PCIe device, which appears as a logical PCIe switch and downstream multiple and multiple logical PCIe terminal devices. After the host completes power-on and PCIe device scanning, the host enters the running phase, and the device where the system is located can initiate a PCIe hot-plug request to dynamically delete or add multiple or multiple logical PCIe terminal devices. The number and attributes of logical PCIe terminal devices downstream of the device where the system is located can be flexibly configured, and the configuration content is determined by the configuration management server and the embedded processor of the device through negotiation when the device starts or runs. In the data center application scenario based on elastic bare metal server, the downstream logical PCIe terminal device can be any device type deployed on the PCI slot, such as sound card, network card, built-in modem, etc.

Specifically, in the host configuration stage, the host scans the downstream PCIe terminal devices in the system and performs corresponding configuration work. In this embodiment of the present invention, the PCIe virtualization module 110 replaces the PCIe terminal device, and receives the PCIe configuration request report sent by the host. message, and reply a configuration response message to the configuration request message. That is to say, when the host scans and configures PCIe terminal devices, it is implemented through the PCIe virtualization module 110 . The PCIe configuration request message and the configuration response message are both message types used in the PCIe protocol for device information exchange when configuring a PCIe terminal device.

In addition, in the device IO operation stage, the host will request to access the IO resources corresponding to the configured PCIe terminal device. At this time, in this embodiment of the present invention, the PCIe virtualization module 110 is still responsible for receiving the PCIe IO request message sent by the host, and replying an IO response message to the configuration request message. Both PCIe IO request packets and IO response packets are packet types used for device information exchange when accessing PCIe terminal device resources in the PCIe protocol. The PCIe IO request packet includes a read and write request of the BAR address space memory corresponding to the downstream PCIe terminal device. The BAR address space is composed of multiple BAR addresses representing multiple functions of multiple PCIE terminal devices, and the data stored in the BAR address space memory is the base address representing the PCIE terminal device in the PCIE address space. Therefore, through the PCIe IO request message including the read and write request of the BAR address space memory, the host can request to access the IO resource corresponding to the address and the corresponding function.

According to the above description of the functions of the PCIe virtualization module 110, it can be seen that the PCIe virtualization module 110 in the embodiment of the present invention performs configuration/IO message interaction with the host regardless of the host configuration stage or the device IO operation stage. , which implements the function of simulating a PCIe switch device and further simulating multiple terminal devices connected to its downstream ports.

The external debugger 120 is connected to the PCIe virtualization module through the debug interface provided by the PCIe virtualization module, and is used to replace the PCIe virtualization module with the debug interface provided by the PCIe virtualization module during startup. Debugging of PCIe configuration and IO calls; and used to modify the program in the PCIe virtualization module for supporting the PCIe terminal device of the target type after the debugging of the PCIe terminal device of the target type is completed.

The system for dynamically configuring PCIe terminal devices provided by the embodiments of the present invention also has programmable and dynamic online update capabilities through the settings of the external debugger 120 and the PCIe virtualization module 110, and can support the virtual realization of existing types of PCIe devices and future possibilities. The emergence of new types of PCIe devices. The support for different types of PCIe devices is achieved by adding or modifying the program storage content of the device where the system is located. The system can support multiple different types of PCIe devices at the same time, and the types of supported devices are limited by the program storage capacity. For new types of PCIe devices that have not been implemented in the system, the system provides an external debugger 120, and sets a corresponding debug interface in the PCIe virtualization module 110 to connect to the external debugger 120. When running the debugging function, the external debugger can be debugged. The debugger 120 takes over the function of the PCIe virtualization module 110 for processing configuration/IO packets, thereby realizing that the external debugger host replaces the PCIe virtualization module 110 to complete the function simulation of the PCIe switch and downstream PCIe terminal devices. After the new type of PCIe terminal device completes all functions in the external host debug mode, the corresponding program storage content in the PCIe virtualization module 110 can be modified to update support for the new type of PCIe terminal device.

In this system, since the external debugger 120 has the highest priority, when the device where the system is located is powered on, it can be determined whether the external debugger is connected. If connected, the system enters the debugging state. When the external debugger is in the debugging state when it is started, the external debugger can use the debugging interface provided by the PCIe virtualization module to replace the PCIe virtualization module to debug the PCIe configuration and IO calls, so as to realize the modification of the existing type of PCIe device. And new types of PCIe device updates. After the debugging is completed, the corresponding program storage content in the PCIe virtualization module 110 is modified in a programmable manner, thereby realizing the support for the new type of PCIe terminal device.

Through the above process, the system realizes the dynamic update of the quantity or attributes of PCIe terminal devices. When the PCIe terminal device needs to be updated, the external debugger can be started to intervene, and the PCIe terminal device can be dynamically configured. At the same time, it also avoids the traditional SR-IOV method, which is more flexible in configuration when multiplexing PCIe terminal devices. Bad question.

The embedded processor 130 is configured to negotiate with an external configuration management server to generate the configuration response message, and determine the generation sequence of a plurality of the configuration response message.

The embedded processor 130 provided in this embodiment of the present invention is responsible for interacting with an external configuration management server (not shown in the figure), responding to a configuration update request and updating the configuration content, so as to flexibly simulate multiple or multiple PCIe terminal devices, And the function of deleting multiple or multiple PCIe terminal devices can be dynamically added and deleted during the running of the host. The embedded processor can be connected to the configuration management server through the Ethernet interface. The embedded processor can realize the simulation of the PCIe terminal device alone, or can work together with the configuration processing module and the IO processing module to realize the simulation of the PCIe terminal device.

Specifically, the PCIe virtualization module 110 in the normal process and the external debugger 120 in the debugging process described above have the functions of distributing PCIe configuration request packets and configuration response packets, respectively. However, the generation of the configuration response message is generated by the embedded processor 130 negotiating with the external configuration management server. In addition, the embedded processor 130 also stores an internal program for determining the generation sequence of a plurality of the configuration response messages, which is suitable for a PCIe configuration request queue formed for a plurality of PCIe configuration requests. The processing logic preset in the internal program of the device determines the generation sequence of multiple corresponding configuration response packets. The processing logic preset in the internal program stored in the embedded processor 130 may determine the generation sequence of the configuration response message according to the time sequence of the arrival of the PCIe configuration request message, or may be determined according to the importance of the requested PCIe terminal device. The generation sequence of the configuration response message is determined, which is not specifically limited in this embodiment of the present invention. The external configuration management server may be an external server device storing PCIe configuration information, and may obtain the latest PCIe configuration information by communicating with the server, and the configuration management server may be provided by a third-party hardware manufacturer.

It can be seen that the embedded processor 130 provides functions similar to CPU in this system, and realizes the generation of the message content itself and the determination of the message generation sequence in the configuration response process through communication with the external configuration management server. When the configuration information is updated by the external configuration management server, the embedded processor 130 obtains the latest configuration information by negotiating with the external configuration management server, and realizes the generation of the message content itself and the determination of the message generation sequence based on the latest configuration information.

The relationship between the PCIe virtualization module 110 , the external debugger 120 and the embedded processor 130 is as follows: the PCIe virtualization module 110 starts immediately after being powered on, and acts as a simulated switch in the conventional process to control the operation of the PCIe terminal device. Configuration and IO handling work. The function corresponding to the external debugger 120 has the highest priority, can monitor and close the other two interfaces, and is only enabled in the debugging state, instead of the PCIe virtualization module 110 to perform the configuration of the PCIe terminal device and the debugging of the IO processing. After the embedded processor 130 works, it can generate the configuration response message according to the latest configuration of the external configuration management server, for example, by switching the jump address of the programmable hardware state machine, etc., and determine a plurality of configuration response messages. The order in which the text is generated. The external debugger can be a processor on the same circuit board as the device where the system is located, or a processor outside the circuit board (such as a PC for debugging). An embedded processor is a dedicated processor on the same circuit board as the device where the system is located.

The system for dynamically configuring PCIe terminal devices provided by the embodiments of the present invention simulates a PCIe switch device through a PCIe virtualization module, further simulates multiple terminal devices connected to its downstream ports, and is responsible for the actual generation of configuration packets through an embedded processor. It also realizes external debuggable and internal programmable development support through the settings of the external debugger, and then effectively meets the flexible configuration and application of PCIe terminal equipment in the case of application, debugging, and updating through the overall design of the system. demand.

Based on the foregoing embodiment, FIG. 2 shows a schematic structural diagram of a PCIe virtualization module provided by an embodiment of the present invention, and the specific content is as follows.

The PCIe transaction layer packet distributor 101 is configured to parse the PCIe transaction layer packet received from the PCIe link layer, and configure the transaction request packet according to the PCIe configuration indicated by the packet header information of the PCIe transaction layer packet Or PCIe IO transaction request message, the PCIe configuration transaction request message or PCIe IO transaction request message is respectively sent to the corresponding configuration processing module or IO processing module; and used to receive from the configuration processing module or IO processing module The PCIe transaction layer packets are distributed to the PCIe link layer.

The PCIe virtualization module provided by the embodiment of the present invention is composed of main modules such as a PCIe transaction layer packet distributor 101, a debugging interface 102, a configuration processing module 103, and an IO processing module 104 in FIG. 2. In addition, the PCIe virtualization module also includes a conventional PCIe physical layer (not shown in the figure), which is responsible for processing physical signals and exchanging data with the PCIe link layer; the PCIe link layer (not shown in the figure), responsible for the data link Road layer packet creation, decoding and verification. Both the PCIe physical layer and the PCIe link layer conform to the PCIe protocol specification, and details are not described in this embodiment of the present invention.

The PCIe transaction layer packet processed by the PCIe link layer will be sent to the PCIe transaction layer packet distributor 101 for reception. After the PCIe transaction layer packet distributor receives the PCIe transaction layer packet of the PCIe link layer, it only parses the packet header, and distinguishes the packet as a PCIe configuration transaction request packet or a PCIe IO transaction request according to the information in the packet header. message. If it is a PCIe configuration transaction request message, it is forwarded to the configuration processing module 103 for processing; if it is a PCIe IO transaction request message, it is forwarded to the IO processing module 104 for processing. Correspondingly, the response packets sent by the configuration processing module 103 and the IO processing module 104 are also sent to the PCIe link layer through the PCIe transaction layer packet distributor. Since the PCIe virtualization module in the embodiment of the present invention functions as a PCIe switch, a PCIe transaction layer packet distributor needs to be set in the PCIe virtualization module to distinguish different types of packets according to the header format of the PCIe protocol. Whether the received message is a PCIe configuration transaction request message or a PCIe IO transaction request message, so as to realize unified management of downstream PCIe terminal devices.

The debug interface 102 is connected to the external debugger, and is used for sending and receiving PCIe transaction layer packets instead of the PCIe transaction layer packet distributor when the external debugger is started.

The foregoing embodiments involve an external debugger taking over the function of the PCIe virtualization module to process configuration/IO packets, thereby realizing that the external debugger host replaces the PCIe virtualization module 110 to complete the functional simulation of the PCIe switch and downstream PCIe terminal devices. Specifically, in the debug state, the external debugger actually communicates with the debug interface 102 in the PCIe virtualization module. Capture and forward all transaction layer packets that the PCIe transaction layer packet distributor interacts with the configuration processing module and the IO processing module.

The above-mentioned active takeover or passive capture method is determined by the debugging process defined by the system. The debugging interface can directly transmit packets with the PCIe link layer, or can automatically capture the packets passing through the PCIe transaction layer packet distributor. The work of the debug interface dealing with the sending and receiving of messages from the PCIe transaction layer message dispatcher is controlled by an external debugger.

The configuration processing module 103 is configured to receive a configuration message, and complete the update of the PCIe terminal device according to the configuration message.

The configuration processing module in the embodiment of the present invention is used for the PCIe device dynamic configuration function in charge of the PCIe switch simulated by the PCIe virtualization module, and specifically includes: receiving and sending a PCIe configuration transaction request message defined in the PCIe protocol, responding to the host's upper During the electrical PCIe enumeration process, a hot-plug operation is initiated and the number and attributes of PCIe terminal devices are updated. By responding to the PCIe configuration transaction request message, the PCIe virtualization module provided by the embodiment of the present invention can simulate a PCIe terminal device, a PCIe switch device, or a PCIe switch device and multiple PCIe terminals connected downstream through software functions. equipment.

The more detailed structure and function of the configuration processing module 103 will be further described in subsequent embodiments.

The IO processing module 104 is configured to receive a PCIe IO request message, and control the PCIe virtualization module and/or at least one PCIe terminal device to perform control status register access and direct memory access according to the PCIe IO request message.

The IO processing module 104 provided in the embodiment of the present invention is used for completing the function of accessing the IO terminal device in the IO processing stage after the configuration processing module completes the dynamic configuration function of the PCIe device, and specifically includes: receiving and sending the PCIe device defined in the PCIe protocol. The IO request message responds to the control status register access of the host driver, and initiates a device-side direct memory access (Direct Memory Access, DMA). The system can implement a PCIe virtualization module and/or independent control status registers of multiple PCIe terminal devices according to the host configuration negotiation result; in addition, for a specific access object, the system can also obtain a PCIe virtualization module from a PCIe virtualization module and/or multiple PCIe terminal devices. /or multiple PCIe end devices independently initiate direct memory access operations.

The more detailed structure and function of the IO processing module 104 will be further described in subsequent embodiments.

Based on any of the foregoing embodiments, FIG. 3 shows a schematic structural diagram of a configuration processing module provided by an embodiment of the present invention, and the specific content is as follows.

The configuration packet sending and receiving interface is used to receive the PCIe configuration transaction request packet distributed by the PCIe transaction layer packet distributor, and send the configuration transaction response packet received from the programmable hardware state machine or the CPU configuration processing interface.

When the packet type distributed by the PCIe transaction layer packet distributor in the embodiment of the present invention is a PCIe configuration transaction request packet, the packet is sent to the configuration processing module, and the configuration processing module receives the packet through the configuration packet sending and receiving interface. of the message. Similarly, when the solution in the embodiment of the present invention is in the debugging state, the configuration processing module receives the PCIe configuration transaction request message distributed by the debugging interface through the configuration message sending and receiving interface.

In addition to receiving PCIe configuration transaction request packets, the configuration packet transceiver interface also needs to send corresponding configuration transaction response packets. The configuration response message in the embodiment of the present invention may be generated by a programmable hardware state machine and sent to the configuration message sending and receiving interface, or may be generated by an embedded processor and sent to the configuration message sending and receiving interface through the CPU configuration processing interface. .

The CPU configuration processing interface is configured to receive the PCIe configuration transaction request message forwarded by the configuration message transceiver interface, and send the configuration transaction response message received from the embedded processor.

The main function of the CPU configuration processing interface in the embodiment of the present invention is an interface for enabling the PCIe virtualization module to communicate with the embedded processor. According to the embedded processor is mainly responsible for generating the configuration response message in this system, the CPU configuration processing interface is mainly used to forward the PCIe configuration transaction request message to the embedded processor for processing. After the transaction response message is configured, the response message is received from the embedded processor.

The programmable hardware state machine is used to receive and parse the PCIe configuration transaction request message forwarded by the configuration message transceiver interface, and send a pre-programmed configuration transaction response message according to the parsed content;

The programmable hardware state machine of the configuration processing module in the embodiment of the present invention also has the function of processing a PCIe configuration transaction request message. The programmable hardware state machine can start to work after power-on. It will parse the PCIe configuration transaction request message according to the pre-programmed configuration transaction response message, and respond to the most basic PCIe protocol and control the response of the PCIe protocol. , Pause PCIe protocol interaction and other work. At the same time, the programmable hardware state machine can work in cooperation with the CPU configuration processing interface after the CPU configuration processing interface is powered on and starts to work.

Specifically, in the embodiment of the present invention, the configuration message may be sent and received independently by the CPU configuration processing interface or the programmable hardware state machine, or may be completed by the cooperation of the two. A possible cooperation method is: the programmable hardware state machine starts immediately after power-on. After receiving the configuration read and write request from the upstream port, it sends a pre-programmed message until the CPU completes power-on initialization, and the CPU takes over the programmable state. The machine completes the subsequent configuration read and write request response. Another possible cooperation method is: the programmable state machine completes all pre-set configuration read and write request responses, and when it encounters an abnormal situation other than the pre-set situation, the embedded processor is triggered to take over the processing, and after the processing is completed , the request response is still completed by the programmable state machine.

The state machine micro-sequence program storage unit is used to store the instructions and data of the programmable hardware state machine, and the instructions and data are written in or read out from the CPU configuration processing interface. This module can be understood as the data storage unit of the programmable hardware state machine. When writing the data in the CPU configuration processing interface, it can switch the jump address in the pre-programmed response message in the programmable hardware state machine. .

The configuration processing module provided by the embodiment of the present invention cooperates with an external embedded processor through the set programmable state machine, and adopts the method of joint control by stages and tasks, so as to provide the dynamic configuration of the PCIe device with immediate effect. Support, effectively meet the needs of flexible processing of PCIe configuration transactions, and realize the unified management of the local and downstream PCIe terminal devices by the PCIe virtualization module where the configuration processing module is located by simulating the PCIe switch device.

Based on any of the foregoing embodiments, FIG. 4 shows a schematic structural diagram of an IO processing module provided by an embodiment of the present invention, and the specific content is as follows.

The target IO message sending and receiving interface is used to receive the PCIe IO transaction request message forwarded by the PCIe transaction layer message distributor, and parse it into a BAR address space memory read and write request; and used to encapsulate the memory read and write response returned by the CSR module into The IO transaction response message is sent to the PCIe transaction layer message distributor.

The CSR module is configured to receive the read and write request of the BAR address space memory sent by the target IO message sending and receiving interface, obtain the corresponding read and write request content according to the BAR address space memory read and write request, and send it to the target IO message sending and receiving interface.

In the IO processing module provided by the embodiment of the present invention, two modules, the target IO message sending and receiving interface and the CSR module, are used for the operation of PCIe IO transaction request under normal circumstances, that is, the host IO stage transaction. The target IO message sending and receiving interface is mainly used for sending and receiving IO messages, and the CSR module is used for processing IO read and write transactions.

When the PCIe transaction layer message distributor in the embodiment of the present invention distributes a PCIe IO transaction request message, the message is sent to the IO processing module, which is specifically the target IO message sending and receiving interface in the IO processing module, which is composed of The target IO message sending and receiving interface further parses the message into a BAR address space memory read and write request, and distributes it to the CSR module to process specific IO read and write transactions.

After the CSR module returns a memory read/write response, the target IO message transceiver interface will encapsulate the response content into an IO transaction response message, and then send it to the PCIe transaction layer message distributor to complete the IO request response process.

The specific structure of the CSR module includes:

The BAR address space mapping management interface is used to provide the BAR address corresponding to the target function of the corresponding PCIe terminal device after receiving the read and write request of the BAR address space memory.

The BAR address space memory is used to save and provide the contents of the BAR address space.

The BAR specific address access trigger is used to trigger the programmable state machine of the IO processing module to run the BAR address space memory update program and the DMA request program when the target BAR address is accessed.

In the embodiment of the present invention, the CSR module is used for specific operations of IO transactions under normal circumstances. First, the BAR address space mapping management interface provides the BAR address corresponding to the target function of the corresponding PCIe terminal device according to the BAR address space memory read/write request parsed by the target IO message sending and receiving interface. Those skilled in the art can understand that PCIe When managing the terminal device, the specific function of the PCIe terminal device can be specifically called in the form of BAR address and through address mapping. Once the value of the BAR address is determined, the internal storage space in the PCIe terminal device within the specified range can be used. Accessed, when the PCIe terminal device confirms that the address in an IO request is within the range of its own BAR, it can accept the request to implement the IO operation. The mapping relationship between the addresses represented by the BAR address space memory and the specific functions of the PCIe terminal device can be stored in the BAR address space memory in advance and provided to the BAR address space mapping management interface for use during IO operations.

The BAR specific address access trigger is used to trigger the programmable state machine of the IO processing module to run the BAR address space memory update program and the DMA request program when the target BAR address is accessed, that is, to switch from the host IO stage under normal conditions to The IO stage of the device related to the special BAR address, and then realize the efficient IO operation corresponding to the specific BAR address through the DMA operation. Next, the relevant modules involved in the specific implementation process of the device IO stage and their specific functions will be described.

The programmable state machine is used to respond to the BAR specific address access trigger signal sent by the BAR specific address access trigger, and send the BAR address space memory update information to the CSR module; it is also used to send a DMA request to the DMA module and receive the DMA module's complete response;

The initial IO message sending and receiving interface is used to receive the host memory address space memory read and write requests sent by the DMA module, and encapsulate the host memory address space memory read and write requests into IO transaction request messages, and send them to the PCIe transaction layer to report It is used to parse the IO transaction response message returned by the PCIe transaction layer message distributor into the host memory address space memory read and write response and send it to the DMA module;

The DMA module is used to respond to the DMA request of the programmable state machine, initiate command acquisition DMA or data transfer DMA operations, and send host memory address space memory read and write requests to the initial IO message transceiver interface; The host memory address space memory read and write response content received by the interface is written to the command buffer or data buffer.

The programmable state machine, the initial IO message sending and receiving interface, and the DMA module in the IO processing module provided by the embodiment of the present invention are used to process the device IO stage transaction that needs to perform DMA operation when the BAR specific address access trigger signal is triggered . In the system provided by the embodiment of the present invention, in addition to realizing flexible configuration of PCIe terminal devices, the PCIe virtualization module also needs to consider the efficiency of IO processing when simulating PCIe switches and implementing unified management of PCIe terminal devices. Therefore, when designing the IO processing module for IO processing, in addition to the target IO message transceiver interface and the CSR module, which are used for the operation of PCIe IO transaction requests under normal circumstances, a programmable state machine, an initial IO module are also designed. The three modules of the message sending and receiving interface and the DMA module are used for the IO processing of the device triggered under special circumstances. The two IO processing mechanisms cooperate with each other to realize the efficient processing of IO.

In the embodiment of the present invention, the programmable state machine is used for triggering the IO processing of the device, and is specifically used to respond to the BAR specific address access trigger signal sent by the BAR specific address access trigger in the CSR module, and send the address space memory of the BAR to the CSR module Update information. Then, the programmable state machine sends a DMA request to the DMA module, completes the triggering process of the DMA operation, and receives a completion response from the DMA module after the DMA module completes the DMA operation.

Specifically, according to the pre-written micro-sequence program stored in the micro-sequence program storage unit of the state machine, the programmable state machine works in the query waiting state, and sequentially queries the BAR specific address access according to a certain order and priority. Trigger signal and completion response signal of DMA module. After receiving the BAR specific address access trigger signal, trigger the execution of the corresponding micro-sequence program; after receiving the completion response signal of the DMA module, trigger and execute the corresponding micro-sequence program.

The function of the starting IO packet sending and receiving interface is similar to that of the target IO packet sending and receiving interface, but it is mainly used for sending and receiving packets of device IO transactions. Specifically, after receiving the host memory address space memory read and write request sent by the DMA module, encapsulate the host memory address space memory read and write request into an IO transaction request message, and send it to the PCIe transaction layer message distributor; in addition; After the IO transaction response packet returned by the PCIe transaction layer packet distributor is sent to the initial IO packet transceiver interface, the initial IO packet transceiver interface parses the response packet into the host memory address space memory read and write response and sends it to DMA module, so as to realize DMA read and write operations.

The DMA module is used to respond to the request of the programmable state machine, initiate command acquisition DMA or data transfer DMA operations, and send host memory address space memory read and write requests to the initial IO message transceiver interface; To the host memory address space memory read and write response content is written to the command cache or data cache. Among them, the DMA module also includes a command acquisition DMA module and a data transmission DMA module, which are controlled by the programmable state machine and are respectively used to acquire corresponding commands or data from the programmable state machine, and in the DMA module are command acquisitions respectively. The DMA module and the data transmission DMA module are respectively provided with a command buffer and a data buffer for buffering the DMA commands and DMA data acquired in the DMA operation.

In the IO processing module provided by the embodiment of the present invention, when the PCIe virtualization module performs unified management on the downstream PCIe devices, the functions of the host IO and the device IO are respectively realized through the design of the related functions of the CSR module and the DMA module. Specifically, according to the corresponding BAR address Different PCIe terminal devices and their functions choose to perform host IO operations or device IO operations, ensuring the efficiency of IO operations under different user needs.

Based on any of the foregoing embodiments, FIG. 5 shows a schematic diagram of a complete structure of a system for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention, and the specific content is as follows.

The system for dynamically configuring PCIe end devices includes PCIe virtualization modules, external debuggers, and embedded processors.

The PCIe virtualization module further includes a PCIe physical layer, a PCIe link layer, a PCIe transaction layer packet distributor, a debugging interface, a configuration processing module, and an IO processing module.

The configuration processing module further includes a configuration message sending and receiving interface, a CPU configuration processing interface, a programmable hardware state machine and a state machine micro-sequence program storage unit.

The IO processing module also includes a target IO message sending and receiving interface, a CSR module, a programmable state machine, a state machine micro-sequence program storage unit, a DMA module and an initial IO message sending and receiving interface.

The CSR module further includes a BAR address space mapping management interface, a BAR address space memory and a BAR specific address access trigger.

The DMA module also includes command acquisition DMA, data transmission DMA, command cache, and data cache; the data cache is also connected to an external data interface for writing DMA data.

Each functional module in the system for dynamically configuring PCIe terminal devices is described in the foregoing embodiments, and details are not described here. The main functions implemented by the system for dynamically configuring PCIe terminal equipment provided by the embodiments of the present invention include: realizing dynamic configuration and unified management of PCIe terminal equipment by simulating PCIe switches; The state machine adopts the method of joint control by stages and tasks, which effectively meets the needs of comprehensive, flexible, real-time response and processing of PCIe transaction layer messages under debugging, application, update, and abnormal conditions; in the PCIe virtualization module Corresponding functional design is carried out in the IO processing module of the device to support two IO operation modes of device IO and host IO, which improves the efficiency of IO operation.

Based on any of the foregoing embodiments, FIG. 6 shows a schematic flowchart of a method for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention, and the specific content is as follows.

Step S610, the PCIe virtualization module of the system receives the PCIe configuration request message sent by the host when the host scans the PCIe terminal devices downstream of the system.

When the host boots up, the topology of downstream PCIe devices is scanned during the PCIe enumeration phase. When scanning the device where the system is located, the PCIe virtualization module will respond as a PCIe switch; the host further scans the PCIe devices downstream of the device, and the PCIe virtualization module will respond instead of the virtual downstream PCIe device, which behaves as a logical PCIe switch and downstream multiple and multiple logical PCIe terminal devices. After the host completes power-on and PCIe device scanning, the host enters the running phase, and the device where the system is located can initiate a PCIe hot-plug request to dynamically delete or add multiple or multiple logical PCIe terminal devices. The number and attributes of logical PCIe terminal devices downstream of the device where the system is located can be flexibly configured, and the configuration content is determined by the configuration management server and the embedded processor of the device through negotiation when the device starts or runs. In the data center application scenario based on elastic bare metal server, the downstream logical PCIe terminal device can be any device type deployed on the PCI slot, such as sound card, network card, built-in modem, etc.

Step S620, the configuration processing module of the PCIe virtualization module replies a PCIe configuration response message to the PCIe configuration request message, wherein the configuration response message is sent by the embedded processor of the system and an external configuration management server. After negotiation and generation, the generation sequence of the plurality of configuration response messages is determined by the embedded processor.

Specifically, in the host configuration stage, the host scans the downstream PCIe terminal devices in the system and performs corresponding configuration work. In this embodiment of the present invention, a PCIe virtualization module replaces the PCIe terminal device, and receives a PCIe configuration request message sent by the host. , and reply a configuration response message to the configuration request message. That is to say, when the host scans and configures PCIe terminal devices, it does so through the PCIe virtualization module. The PCIe configuration request message and the configuration response message are both message types used in the PCIe protocol for device information exchange when configuring a PCIe terminal device.

Step S630, the PCIe virtualization module of the system receives a PCIe IO request message sent by the host, wherein the PCIe IO request message includes a read and write request of a BAR address space memory corresponding to a downstream PCIe terminal device.

Step S640, the IO processing module of the PCIe virtualization module replies with an IO response message to the PCIe IO request message, wherein the IO response message includes the content stored in the BAR address space memory.

In the device IO operation stage, the host will request to access the IO resources corresponding to the configured PCIe terminal device. At this time, in this embodiment of the present invention, the PCIe virtualization module is still responsible for receiving the PCIe IO request message sent by the host, and replies with an IO response message to the configuration request message. Both PCIe IO request packets and IO response packets are packet types used for device information exchange when accessing PCIe terminal device resources in the PCIe protocol. The PCIe IO request packet includes a read and write request of the BAR address space memory corresponding to the downstream PCIe terminal device. The BAR address space is composed of multiple BAR addresses representing multiple functions of multiple PCIE terminal devices, and the data stored in the BAR address space memory is the base address representing the PCIE terminal device in the PCIE address space. Therefore, through the PCIe IO request message including the read and write request of the BAR address space memory, the host can request to access the IO resource corresponding to the address and the corresponding function.

S650, when the target BAR address is accessed, the programmable state machine of the IO processing module is triggered to run the BAR address space memory update program and the DMA request program.

The embodiment of the present invention embodies the application process of the system executing the method for dynamically configuring PCIe terminal equipment. A possible specific implementation is as follows:

Host configuration stage: The host configuration stage starts to scan for PCIe terminal devices after the host is powered on; the terminal device waits for the embedded processor to power on after receiving the READY query command; after the embedded processor is ready for power on, it waits for the programmable state machine Returns the READY signal; when the device where the system is located receives the configuration read request, the embedded processor returns the type of the device as PCIe switch, and then the device receives the read request from the downstream PCIe terminal device, the device where the system is located and the embedded processor After the processor communicates, it returns the configuration information of one of the multiple downstream devices to complete the task of the host scanning phase.

Host IO stage: the embedded processor configures the CSR module in the PCIe virtualization to set the BAR address information of each downstream device. Then the IO operation phase can be performed. The device where the system is located receives the IO read request, and the CSR module can return the CSR content of the specific downstream device. When the host accesses a specific BAR address, the BAR specific address access flip-flop sends a trigger signal to the programmable state machine.

Device IO stage: After triggering the process of the device IO stage, the programmable state machine starts the command to obtain DMA, the command to obtain DMA sends the host memory read command, the host returns the response content to the command cache, and the programmable state machine reads the command cache and parses Command, start the data transfer DMA, the data transfer DMA sends the host memory read and write instructions, the host returns the memory content in the data cache, and completes the main operations in the IO stage of the device. For a complete implementation manner provided above, reference may be made to the complete schematic flowchart of the method for dynamically configuring a PCIe terminal device provided in FIG. 7 .

Based on any of the foregoing embodiments, FIG. 8 shows a schematic flowchart of a debugging method for a PCIe terminal device provided by an embodiment of the present invention, and the specific content is as follows.

Step S810, start the external debugger of the system;

Step S820, the external debugger performs the debugging of PCIe configuration and IO call instead of the PCIe virtualization module through the debugging interface provided by the PCIe virtualization module;

Step S830, after the debugging of the PCIe terminal device of the target type is completed, modify the program in the PCIe virtualization module for supporting the PCIe terminal device of the target type.

The embodiment of the present invention embodies the debugging process of the system executing the method for dynamically configuring PCIe terminal equipment. The system for dynamically configuring a PCIe terminal device provided by the embodiment of the present invention is connected to the PCIe virtualization module through a debugging interface provided by the PCIe virtualization module, and is used for using the debugging interface provided by the PCIe virtualization module during startup, Debugging of PCIe configuration and IO call in place of the PCIe virtualization module; and for modifying the program for supporting the PCIe terminal device of the target type in the PCIe virtualization module after the debugging of the PCIe terminal device of the target type is completed .

The system for dynamically configuring PCIe terminal devices provided by the embodiments of the present invention also has programmable and dynamic online update capabilities through the settings of an external debugger and a PCIe virtualization module, and can support the virtual realization of existing types of PCIe devices and possible future ones. New type of PCIe device. The support for different types of PCIe devices is achieved by adding or modifying the program storage content of the device where the system is located. The system can support multiple different types of PCIe devices at the same time, and the types of supported devices are limited by the program storage capacity. For new types of PCIe devices that have not been implemented in the system, the system provides an external debugger, and sets a corresponding debug interface in the PCIe virtualization module to connect with the external debugger 120, which can be taken over by the external debugger when running the debugging function The PCIe virtualization module processes the configuration/IO message function, and then realizes that the external debugger host replaces the PCIe virtualization module to complete the functional simulation of the PCIe switch and downstream PCIe terminal devices. After the new type of PCIe terminal device completes all functions in the external host debug mode, the corresponding program storage content in the PCIe virtualization module can be modified to update support for the new type of PCIe terminal device.

Since the external debugger has the highest priority in this system, it can be judged whether the external debugger is connected when the device where the system is located is powered on. If connected, the system enters the debugging state. When the external debugger is in the debug state when it is started, the external debugger can use the debug interface provided by the PCIe virtualization module to replace the PCIe virtualization module to debug PCIe configuration and IO calls, so as to realize the modification of existing types of PCIe devices. And new types of PCIe device updates. After the debugging is completed, the corresponding program storage content in the PCIe virtualization module is modified in a programmable manner, thereby realizing support for new types of PCIe terminal devices.

Through the above process, the system realizes the dynamic update of the quantity or attributes of PCIe terminal devices. When the PCIe terminal device needs to be updated, the external debugger can be started to intervene, and the PCIe terminal device can be dynamically configured. At the same time, it also avoids the traditional SR-IOV method, which is more flexible in configuration when multiplexing PCIe terminal devices. Bad question.

Based on any of the foregoing embodiments, FIG. 9 shows a schematic flowchart of an exception processing method for dynamically configuring a PCIe terminal device provided by an embodiment of the present invention, and the specific content is as follows.

Step S910, the configuration response message is generated by the programmable state machine of the configuration processing module of the PCIe virtualization module, instead of the negotiation process between the embedded processor and the external configuration management server;

Step S920, if the PCIe configuration request message is of an undefined type, the configuration response message is generated instead of the programmable state machine according to the negotiation between the embedded processor and the external configuration management server.

The embodiment of the present invention embodies the abnormal processing flow of the system executing the method for dynamically configuring PCIe terminal equipment. The programmable hardware state machine of the configuration processing module in the embodiment of the present invention also has the function of processing a PCIe configuration transaction request message. The programmable hardware state machine can start to work after power-on. It will parse the PCIe configuration transaction request message according to the pre-programmed configuration transaction response message, and respond to the most basic PCIe protocol and control the response of the PCIe protocol. , Pause PCIe protocol interaction and other work. At the same time, the programmable hardware state machine can work in cooperation with the CPU configuration processing interface after the CPU configuration processing interface is powered on and starts to work.

Specifically, in the embodiment of the present invention, the configuration message may be sent and received independently by the CPU configuration processing interface or the programmable hardware state machine, or may be completed by the cooperation of the two. A possible cooperation method is: the programmable hardware state machine starts immediately after power-on. After receiving the configuration read and write request from the upstream port, it sends a pre-programmed message until the CPU completes power-on initialization, and the CPU takes over the programmable state. The machine completes the subsequent configuration read and write request response. Another possible cooperation method is: the programmable state machine completes all pre-set configuration read and write request responses, and when it encounters an abnormal situation other than the pre-set situation, the embedded processor is triggered to take over the processing, and after the processing is completed , the request response is still completed by the programmable state machine.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. a system of dynamically configuring PCIe terminal equipment, is characterized in that, described system comprises: The PCIe virtualization module is configured to receive a PCIe configuration request message sent by the host when the host scans the PCIe terminal devices downstream of the system, and reply a configuration response message to the PCIe configuration request message; and is used to receive all the PCIe configuration request messages. Describe the PCIe IO request message sent by the host, and reply the IO response message to the PCIe IO request message; wherein, the PCIe IO request message includes the base address register BAR address space memory read and write request corresponding to the downstream PCIe terminal device ; An external debugger, connected to the PCIe virtualization module through the debug interface provided by the PCIe virtualization module, and used to replace the PCIe virtualization module with the debug interface provided by the PCIe virtualization module during startup to perform PCIe Debugging of configuration and IO call; and for modifying the program for supporting the PCIe terminal device of the target type in the PCIe virtualization module after the debugging of the PCIe terminal device of the target type is completed; The embedded processor is configured to negotiate with an external configuration management server to generate the configuration response message, and determine the generation sequence of a plurality of the configuration response messages. 2. The system for dynamically configuring PCIe terminal equipment according to claim 1, wherein the PCIe virtualization module comprises: The PCIe transaction layer message distributor is used to parse the PCIe transaction layer message received from the PCIe link layer, and according to the PCIe configuration request message or PCIe configuration request message indicated by the message header information of the PCIe transaction layer message IO request message, sending the PCIe configuration request message or PCIe IO request message to the corresponding configuration processing module or IO processing module respectively; and used to report the PCIe transaction layer received from the configuration processing module or the IO processing module document, distributed to the PCIe link layer; a debugging interface, connected with the external debugger, for sending and receiving PCIe transaction layer messages instead of the PCIe transaction layer message distributor when the external debugger is started; a configuration processing module, configured to receive the PCIe configuration request message, and complete the update of the PCIe terminal device according to the PCIe configuration request message; An IO processing module, configured to receive a PCIe IO request message, and control the PCIe virtualization module and/or at least one PCIe terminal device to perform control status register access and direct memory access according to the PCIe IO request message. 3. The system for dynamically configuring PCIe terminal equipment according to claim 2, wherein the configuration processing module comprises: The configuration packet sending and receiving interface is used to receive the PCIe configuration request packet distributed by the PCIe transaction layer packet distributor, and send the configuration response packet received from the programmable hardware state machine or the CPU configuration processing interface; The CPU configuration processing interface is used to receive the PCIe configuration request message forwarded by the configuration message transceiver interface, and send the configuration response message received from the embedded processor; The programmable hardware state machine is used to receive and parse the PCIe configuration request message forwarded by the configuration message transceiver interface, and send a pre-programmed configuration response message according to the parsed content; The state machine micro-sequence program storage unit is used to store the instructions and data of the programmable hardware state machine, and the instructions and data are written in or read out from the CPU configuration processing interface. 4. The system for dynamically configuring PCIe terminal equipment according to claim 2, wherein the IO processing module comprises: The target IO message transceiver interface is used to receive the PCIe IO request message forwarded by the PCIe transaction layer message distributor, and parse it into a BAR address space memory read and write request; and used to read and write the memory returned by the control and status register CSR module. The response is encapsulated into an IO response message and sent to the PCIe transaction layer message distributor; The CSR module is configured to receive the read and write request of the BAR address space memory sent by the target IO message sending and receiving interface, obtain the corresponding read and write request content according to the BAR address space memory read and write request, and send it to the target IO message sending and receiving interface. 5. The system for dynamically configuring PCIe terminal equipment according to claim 4, wherein the CSR module comprises: The BAR address space mapping management interface is used to provide the BAR address corresponding to the target function of the corresponding PCIe terminal device after receiving the read and write request of the BAR address space memory; The BAR address space memory is used to save and provide the contents of the BAR address space. 6. the system of dynamically configuring PCIe terminal equipment according to claim 5, is characterized in that, described CSR module also comprises BAR specific address access trigger, is used for when target BAR address is visited, triggers the possibility of IO processing module. The programming state machine runs the BAR address space memory update routine and the direct register access DMA request routine; Correspondingly, the IO processing module further includes: The programmable state machine is used to respond to the BAR specific address access trigger signal sent by the BAR specific address access trigger, and send the BAR address space memory update information to the CSR module; it is also used to send a DMA request to the DMA module and receive the DMA module's complete response; The initial IO message sending and receiving interface is used to receive the host memory address space memory read and write request sent by the DMA module, and encapsulate the host memory address space memory read and write request into a PCIe IO request message, and send it to the PCIe transaction layer to report It is used to parse the IO response message returned by the PCIe transaction layer message distributor into the host memory address space memory read and write response and send it to the DMA module; The DMA module is used to respond to the DMA request of the programmable state machine, initiate command acquisition DMA or data transfer DMA operations, and send host memory address space memory read and write requests to the initial IO message transceiver interface; The host memory address space memory read and write response content received by the interface is written to the command buffer or data buffer. 7. A method for dynamically configuring PCIe terminal equipment, applied to the system according to any one of claims 1-6, wherein the method comprises: The PCIe virtualization module of the system receives the PCIe configuration request message sent by the host when the host scans the PCIe terminal equipment downstream of the system; The configuration processing module of the PCIe virtualization module replies with a PCIe configuration response message to the PCIe configuration request message, wherein the configuration response message is generated by negotiation between the embedded processor of the system and an external configuration management server, The generation sequence of a plurality of the configuration response messages is determined by the embedded processor; The PCIe virtualization module of the system receives a PCIe IO request message sent by the host, wherein the PCIe IO request message includes a BAR address space memory read and write request corresponding to a downstream PCIe terminal device; The IO processing module of the PCIe virtualization module replies with an IO response message to the PCIe IO request message, where the IO response message includes the content stored in the BAR address space memory. 8. The method for dynamically configuring a PCIe terminal device according to claim 7, wherein the method further comprises: When the target BAR address is accessed, the programmable state machine of the IO processing module is triggered to run the BAR address space memory update procedure and the DMA request procedure. 9. The method for dynamically configuring a PCIe terminal device according to claim 7, wherein the method further comprises: start an external debugger for the system; The external debugger performs the debugging of PCIe configuration and IO call in place of the PCIe virtualization module through the debugging interface provided by the PCIe virtualization module; After the debugging of the PCIe terminal device of the target type is completed, modify the program in the PCIe virtualization module for supporting the PCIe terminal device of the target type. 10. The method for dynamically configuring a PCIe terminal device according to claim 7, wherein the method further comprises: The configuration response message is generated by the programmable hardware state machine of the configuration processing module of the PCIe virtualization module, instead of the negotiation process between the embedded processor and the external configuration management server; If the PCIe configuration request message is of an undefined type, the configuration response message is generated instead of the programmable state machine according to the negotiation between the embedded processor and the external configuration management server.

Images