CN113904729A - Multi-rate 10km QSFP28 optical module - Google Patents
Multi-rate 10km QSFP28 optical module Download PDFInfo
- Publication number
- CN113904729A CN113904729A CN202111153801.8A CN202111153801A CN113904729A CN 113904729 A CN113904729 A CN 113904729A CN 202111153801 A CN202111153801 A CN 202111153801A CN 113904729 A CN113904729 A CN 113904729A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- pin
- circuit
- optical
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 120
- 238000003745 diagnosis Methods 0.000 claims abstract description 23
- 238000004891 communication Methods 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 153
- 238000011084 recovery Methods 0.000 claims description 57
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 230000003321 amplification Effects 0.000 claims description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 10
- 238000005070 sampling Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100406674 Arabidopsis thaliana OTU4 gene Proteins 0.000 description 1
- 235000011449 Rosa Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/501—Structural aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/501—Structural aspects
- H04B10/503—Laser transmitters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J14/00—Optical multiplex systems
- H04J14/02—Wavelength-division multiplex systems
- H04J14/0201—Add-and-drop multiplexing
- H04J14/0202—Arrangements therefor
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Optical Communication System (AREA)
Abstract
The invention relates to a multi-rate 10km QSFP28 optical module, which comprises a light receiving unit, a digital diagnostic unit, an interface unit and a light emitting unit, wherein the light receiving unit and the light emitting unit are respectively connected with the digital diagnostic unit and provide light detection signals for the digital diagnostic unit; the light receiving unit is connected with the interface unit and converts a received light signal into an electric signal to be output; the light emitting unit is connected with the interface unit and converts the electric signal input by the interface unit into an optical signal to be output, the digital diagnosis unit is connected with the interface unit and processes the optical detection signal to obtain a digital diagnosis signal, and the digital diagnosis signal is sent to external communication equipment through the interface unit. The invention supports 112G multi-rate 10km QSFP28 optical module, so that the optical module can be suitable for a plurality of fixed rates, thus enhancing the universality of the 112G 10km QSFP28 optical module.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a multi-rate 10km QSFP28 optical module.
Background
Metropolitan Area networks (metropolian Area networks) are computer communication networks established in a city domain, MAN for short, and belong to broadband local Area networks. With the continuous development of internet services and various value-added services, the bandwidth required by the metropolitan area network is also wider and wider, and the current metropolitan area network becomes a bottleneck of service development. In addition, various types of services also put higher demands on the comprehensive access and processing of the metropolitan area network.
QSFP is a form of packaging specified in the multi-source agreement (MSA) of 40G and 100G pluggable optical modules initiated and established by internationally known communication equipment manufacturers.
Currently, a 112G multi-rate 10km QSFP28 optical module is mainly used for meeting the Ethernet transmission requirement of 103.12Gb/s, however, individual customers also require to meet the requirements of 111.809Gb/s of OTU4 and 112.2Gb/s of 32G FC as well as 8.5Gb/s of downward compatible 8G FC and 14.025Gb/s of 16G FC, and the current optical module cannot meet the requirement of multiple rates at the same time.
Disclosure of Invention
In view of the above, the present invention provides a multi-rate 10km QSFP28 optical module capable of supporting multiple different rates simultaneously.
In order to achieve the above object, a technical solution to the technical problem of the present invention is to provide a multi-rate 10km QSFP28 optical module, including: a base;
the system comprises a light receiving unit, a digital diagnosis unit, an interface unit and a light emitting unit, wherein the light receiving unit and the light emitting unit are respectively connected with the digital diagnosis unit and provide light detection signals for the digital diagnosis unit; the light receiving unit is connected with the interface unit and converts a received light signal into an electric signal to be output; the light emitting unit is connected with the interface unit and converts an electric signal input by the interface unit into an optical signal to be output, the digital diagnosis unit is connected with the interface unit and processes the optical detection signal to obtain a digital diagnosis signal, and the digital diagnosis signal is sent to external communication equipment through the interface unit;
the optical receiving unit comprises a wavelength division demultiplexing optical circuit and an optical receiving circuit which are connected according to the transmission sequence of an optical circuit, wherein the wavelength division demultiplexing optical circuit receives a transmitted optical input signal and demultiplexes the received optical input signal to form a decomposed signal received by the optical receiving circuit, and the optical receiving circuit receives the transmitted decomposed signal and converts the decomposed signal into an electric signal;
the optical transmitting unit comprises a wavelength division multiplexing optical circuit, an optical transmitting circuit and a laser driver, wherein the laser driver transmits signals sent by the interface unit into the optical transmitting circuit, the optical transmitting circuit converts the input signals into optical signals and outputs the optical signals to the wavelength division multiplexing optical circuit, and the optical signals are generated and transmitted to the outside after the multiplexing function of the wavelength division multiplexing optical circuit.
Further, the optical receiving unit further comprises a transimpedance amplifier circuit and a clock data recovery circuit, the transimpedance amplifier circuit is electrically connected with the optical receiving circuit and the clock data recovery circuit, the clock data recovery circuit is electrically connected with the interface unit, an electric signal generated by the optical receiving circuit is amplified by the transimpedance amplifier circuit and transmitted to the clock data recovery circuit for clock data sampling and cache processing, and the converted signal is transmitted to the interface unit.
Furthermore, the light emitting unit further comprises a pre-emphasis clock data recovery circuit, the pre-emphasis clock data recovery circuit is electrically connected with the interface unit and the laser driver, the pre-emphasis clock data recovery circuit receives the input signal of the interface unit, performs modulation pre-emphasis processing, performs clock data sampling and cache processing simultaneously, and transmits the signal into the light emitting circuit through the laser driver.
Further, the digital diagnostic unit includes a logic control circuit and a signal conversion circuit, the logic control circuit is electrically connected to the clock data recovery circuit and the pre-emphasis data recovery circuit respectively to collect, process and monitor data of the clock data recovery circuit and the pre-emphasis data recovery circuit 44, an internal memory of the logic control circuit stores module information and user information, and the signal conversion circuit is connected to the light receiving circuit and the laser driving circuit to complete conversion between analog signals and digital signals.
Further, the signal conversion circuit has a D/a converter and an a/D converter, the D/a converter is electrically connected to the laser drive circuit and the logic control circuit, and can convert a digital signal of the logic control circuit into an analog signal that can be received by the laser drive circuit; the A/D converter is electrically connected with the logic control circuit and the light receiving circuit and can convert an analog signal sent by the light receiving circuit into a digital signal which can be received by the logic control circuit.
Further, the light receiving circuit comprises a light receiving chip U62, a capacitor C29 and a capacitor C28, wherein the OUT0N pin, the OUT0P pin, the OUT1N pin, the OUT1P pin, the OUT2N pin, the OUT3P pin, the OUT3N pin and the OUT3P pin of the light receiving chip U62 are electrically connected with the transimpedance amplifier circuit, the RSSI3 pin of the light receiving chip U62 is electrically connected with the signal conversion circuit, and one end of the capacitor C29 and one end of the capacitor C28 are electrically connected with the VCC4 pin of the light receiving chip U62; the other end of the capacitor C29 and the other end of the capacitor C28 are grounded.
Further, the clock data recovery circuit includes an amplification chip U, a capacitor C, and a capacitor C, wherein one end of the capacitor C, one end of an upper capacitor C, one end of the capacitor C, and one end of the capacitor C are electrically connected to an R1N + pin, an R1N-pin, an R1N + pin, an R1N-pin, and an R1N + pin of the amplification chip U, respectively, and the other end of the capacitor C, the other end of the upper capacitor C, and the other end of the capacitor C are electrically connected to the light receiving chip U; the CS pin and the INTRPT pin of the amplification chip U3 are electrically connected with the digital diagnosis unit, and the ROUT 1-pin, the ROUT1+ pin, the ROUT 1-pin, the ROUT 2-pin, the ROUT2+ pin, the ROUT 3-pin, the ROUT3+ pin, the ROUT 4-pin and the ROUT4+ pin of the amplification chip U3 are electrically connected with the interface unit.
Further, the light emitting circuit comprises a light emitting chip U15, a resistor R6 and a capacitor C34, wherein one end of the resistor R6 and one end of the capacitor C34 are electrically connected with an RTH pin of the light emitting chip U15, and the other end of the capacitor C34 is grounded; the pin SI3P, the pin SI3N, the pin SI2P, the pin SI2N, the pin SI1P, the pin SI1N, the pin SI0P and the pin SI0N of the light emitting chip U15 are electrically connected with the laser driving circuit.
Further, the pre-emphasis clock data recovery circuit comprises a recovery chip U14, a resistor R101, a resistor R102, a capacitor C49, a capacitor C253, a capacitor C254, an inductor L18, an inductor L20, an inductor L22, an inductor L23, an inductor L24, and an inductor L28, wherein one end of the resistor R101 and one end of the resistor R102 are electrically connected to a CONFIG pin of the recovery chip U14, the other end of the resistor R101 is grounded, the other end of the resistor R102 is electrically connected to one end of the capacitor C49, and the other end of the capacitor C49 is grounded; one end of the capacitor C253 and one end of the capacitor C254 are electrically connected with a VCC _ CAP pin of the recovery chip U14, and the other end of the capacitor C253 and the other end of the capacitor C254 are grounded; the VCCL1 pin, the VCCL2 pin, the VCCL3 pin, the VCCL4 pin, the VCCL5 pin and the VCCL6 pin of the recovery chip U14 are electrically connected to the inductor L28, the inductor L22, the inductor L24, the inductor L23, the inductor L18 and the inductor L20, respectively.
Further, the logic control circuit comprises a logic control chip U8, a capacitor C54, a capacitor C61, a capacitor C63, a capacitor C276, a capacitor C277, a resistor R8 and a resistor R89, wherein one end of the capacitor C54 is electrically connected with a P1.0 pin of the logic control chip U8, and the other end of the capacitor C54 is grounded; one end of the capacitor C61 and one end of the capacitor C63 are electrically connected with a VDD pin of the logic control chip U8, and the other end of the capacitor C61 and the other end of the capacitor C63 are grounded; one end of the capacitor C276, one end of the capacitor C277 and one end of the resistor R89 are electrically connected, the other end of the resistor R89 is electrically connected with the RSTb pin of the logic control chip U8, the other end of the capacitor C276 and the other end of the capacitor C277 are grounded, one end of the resistor R8 is electrically connected with the P1.0 pin of the logic control chip U8, and the other end of the resistor R8 is grounded.
Compared with the prior art, the multi-rate 10km QSFP28 optical module provided by the invention has the following beneficial effects:
the invention supports 112G multi-speed 10km QSFP28 optical module, which adopts a wavelength division multiplexing optical circuit and a wavelength division demultiplexing optical circuit to synthesize a plurality of wavelength optical signals into a beam, so that the optical module can be suitable for a plurality of fixed speeds, thus enhancing the universality of the 112G 10km QSFP28 optical module; the optical receiving unit and the optical transmitting unit are integrated with a clock data recovery circuit, so that the optical receiving unit and the optical transmitting unit have good high-frequency jitter removal characteristics and are beneficial to the recovery of clock data in the transmission process of synchronous data in network communication.
Drawings
FIG. 1 is a block diagram of a multi-rate 10km QSFP28 optical module according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram of the light receiving circuit of FIG. 1;
FIG. 3 is a circuit diagram of the clock data recovery circuit of FIG. 1;
FIG. 4 is a circuit diagram of the light emitting circuit of FIG. 1;
FIG. 5 is a circuit diagram of the pre-emphasis clock data recovery circuit of FIG. 1;
fig. 6 is a circuit diagram of the logic control circuit of fig. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, a multi-rate 10km QSFP28 optical module according to a first embodiment of the present invention includes: the system comprises a light receiving unit 1, a digital diagnosis unit 2, an interface unit 3 and a light emitting unit 4; the light receiving unit 1 and the light emitting unit 4 are respectively connected with the digital diagnostic unit 2, and the light receiving unit 1 and the light emitting unit 4 provide light detection signals for the digital diagnostic unit 2; the light receiving unit 1 is connected with the interface unit 3, and converts a received light signal into an electric signal to be output; the light emitting unit 4 is connected with the interface unit 3, converts the electrical signal input by the interface unit 3 into an optical signal and outputs the optical signal, the digital diagnosis unit 2 is connected with the interface unit 3, and the digital diagnosis unit 2 processes the optical detection signal to obtain a digital diagnosis signal and sends the digital diagnosis signal to external communication equipment through the interface unit 3.
Specifically, with reference to fig. 2 and 3, the optical receiving unit 1 includes a wavelength division demultiplexing optical circuit 11, an optical receiving circuit 12, a transimpedance amplifier circuit 13, and a clock data recovery circuit 14, which are connected in an optical circuit propagation order, where the wavelength division demultiplexing optical circuit 11 receives a transmitted optical input signal and demultiplexes the received optical input signal to form a decomposed signal received by the optical receiving circuit 12, the optical receiving circuit 12 receives the transmitted decomposed signal and converts the decomposed signal into an electrical signal, the electrical signal is amplified by the transimpedance amplifier circuit 13 and transmitted to the clock data recovery circuit 14, clock data sampling and buffering processing is performed, and the converted signal is transmitted to the interface unit 3.
Specifically, the light receiving unit 1 includes four light receiving circuits 12, the wavelength division demultiplexing optical circuit 11 receives the transmitted light input signal, demultiplexes the received light input signal, divides the demultiplexed light input signal into four paths of decomposed signals, and receives the decomposed signals by the four light receiving circuits 12, and each light receiving circuit 12 receives the decomposed signals and converts the decomposed signals into electric signals.
Specifically, the optical transmitter unit 4 includes a wavelength division multiplexing optical circuit 41, an optical transmitter circuit 42, a laser driver 43, and a pre-emphasis clock data recovery circuit 44, where the pre-emphasis clock data recovery circuit 44 is connected to the interface unit 3 to receive the input signal of the interface unit 3, perform modulation pre-emphasis processing, perform clock data sampling and buffer processing, transmit the signal to the optical transmitter circuit 42 through the laser driver 43, the optical transmitter circuit 42 converts the input signal into an optical signal, outputs the optical signal to the wavelength division multiplexing optical circuit 41, and transmits the optical signal to the outside after the multiplexing function of the wavelength division multiplexing optical circuit 41.
Specifically, the light emitting unit 4 includes four light emitting circuits 42 and four laser drivers 43, the four light emitting circuits 52 are electrically connected to the wavelength division multiplexing optical circuit 41 and are electrically connected to the four laser drivers 43 in a one-to-one correspondence manner, and the four laser drivers 43 are electrically connected to the pre-emphasis clock data recovery circuit 44.
Specifically, the digital diagnostic unit 2 includes a logic control circuit 21 and a signal conversion circuit 22, the logic control circuit 21 is electrically connected to the clock data recovery circuit 13 and the pre-emphasis data recovery circuit 44 respectively to collect, process and monitor data of the clock data recovery circuit 13 and the pre-emphasis data recovery circuit 44, an internal memory of the logic control circuit 21 stores module information and user information, and the signal conversion circuit 22 is connected to the light receiving circuit 12 and the laser driving circuit 43 to complete conversion between analog signals and digital signals.
It is understood that the signal conversion circuit 22 has a D/a converter and an a/D converter, the D/a converter is electrically connected to the laser driving circuit 43 and the logic control circuit 21, and can convert the digital signal of the logic control circuit 21 into an analog signal that can be received by the laser driving circuit 43; the a/D converter is electrically connected to the logic control circuit 21 and the light receiving circuit 12, and can convert an analog signal sent from the light receiving circuit 12 into a digital signal that can be received by the logic control circuit 21.
Specifically, as shown in fig. 2, the light receiving circuit 12 includes a light receiving chip U62, a capacitor C29, and a capacitor C28, where the pin OUT0N, the pin OUT0P, the pin OUT1N, the pin OUT1P, the pin OUT2N, the pin OUT3P, the pin OUT3N, and the pin OUT3P of the light receiving chip U62 are electrically connected to the transimpedance amplifier circuit 13, the RSSI3 pin of the light receiving chip U62 is electrically connected to the signal conversion circuit 22, and one end of the capacitor C29 and one end of the capacitor C28 are electrically connected to the pin VCC4 of the light receiving chip U62; the other end of the capacitor C29 and the other end of the capacitor C28 are grounded.
In this embodiment, the specific model of the light receiving chip U62 is LAN _ WDM _ ROSA.
Specifically, the transimpedance amplifier circuit 13 is a GN2110S 28Gbps type transimpedance amplifier, and is electrically connected to the light receiving circuit 12 and the clock data recovery circuit 14.
Specifically, as shown in fig. 3, the clock data recovery circuit 14 includes an amplifying chip U3, a capacitor C13, a capacitor C14, a capacitor C21, a capacitor C24, a capacitor C30, a capacitor C31, a capacitor C36, a capacitor C38, one end of the capacitor C13, one end of the capacitor C14, one end of the capacitor C21, one end of the capacitor C24, one end of the capacitor C30, one end of the upper capacitor C31, one end of the capacitor C36 and one end of the capacitor C38 are respectively and electrically connected with a pin R1N1+, a pin R1N1-, a pin R1N2-, a pin R1N2+, a pin R1N3-, a pin R1N3+, a pin R1N 4-and a pin R1N4+ of the amplification chip U3, the other end of the capacitor C13, the other end of the capacitor C14, the other end of the capacitor C21, the other end of the capacitor C24, the other end of the capacitor C30, the other end of the upper capacitor C31 and the other end of the capacitor C36 are electrically connected with the light receiving chip U62; the CS pin and INTRPT pin of the amplification chip U3 are electrically connected with the digital diagnostic unit 2, and the ROUT 1-pin, ROUT1+ pin, ROUT 1-pin, ROUT 2-pin, ROUT2+ pin, ROUT 3-pin, ROUT3+ pin, ROUT 4-pin and ROUT4+ pin of the amplification chip U3 are electrically connected with the interface unit 3.
In this embodiment, the specific model of the amplification chip U3 is MAX 24026.
Specifically, as shown in fig. 4, the light emitting circuit 42 includes a light emitting chip U15, a resistor R6, and a capacitor C34, one end of the resistor R6 and one end of the capacitor C34 are electrically connected to an RTH pin of the light emitting chip U15, and the other end of the capacitor C34 is grounded; the SI3P pin, the SI3N pin, the SI2P pin, the SI2N pin, the SI1P pin, the SI1N pin, the SI0P pin, and the SI0N pin of the light emitting chip U15 are electrically connected to the laser driving circuit 43.
In the embodiment, the specific model of the light emitting chip U15 is CL 100G LAN-WDM TOSA.
Specifically, the laser driver 43 is preferably a MALD-37059B 25Gb/s to 28Gb/s four-channel direct modulation driver.
Specifically, as shown in fig. 5, the pre-emphasis clock data recovery circuit 44 includes a recovery chip U14, a resistor R101, a resistor R102, a capacitor C49, a capacitor C253, a capacitor C254, an inductor L18, an inductor L20, an inductor L22, an inductor L23, an inductor L24, and an inductor L28, where one end of the resistor R101 and one end of the resistor R102 are electrically connected to a CONFIG pin of the recovery chip U14, the other end of the resistor R101 is grounded, the other end of the resistor R102 is electrically connected to one end of the capacitor C49, and the other end of the capacitor C49 is grounded; one end of the capacitor C253 and one end of the capacitor C254 are electrically connected with a VCC _ CAP pin of the recovery chip U14, and the other end of the capacitor C253 and the other end of the capacitor C254 are grounded; the VCCL1 pin, the VCCL2 pin, the VCCL3 pin, the VCCL4 pin, the VCCL5 pin and the VCCL6 pin of the recovery chip U14 are electrically connected to the inductor L28, the inductor L22, the inductor L24, the inductor L23, the inductor L18 and the inductor L20, respectively.
In this embodiment, the specific model of the recovery chip U14 is GN 2104S.
Specifically, as shown in fig. 6, the logic control circuit 21 includes a logic control chip U8, a capacitor C54, a capacitor C61, a capacitor C63, a capacitor C276, a capacitor C277, a resistor R8, and a resistor R89, one end of the capacitor C54 is electrically connected to the P1.0 pin of the logic control chip U8, and the other end of the capacitor C54 is grounded; one end of the capacitor C61 and one end of the capacitor C63 are electrically connected with a VDD pin of the logic control chip U8, and the other end of the capacitor C61 and the other end of the capacitor C63 are grounded; one end of the capacitor C276, one end of the capacitor C277 and one end of the resistor R89 are electrically connected, the other end of the resistor R89 is electrically connected with the RSTb pin of the logic control chip U8, the other end of the capacitor C276 and the other end of the capacitor C277 are grounded, one end of the resistor R8 is electrically connected with the P1.0 pin of the logic control chip U8, and the other end of the resistor R8 is grounded.
In the embodiment, the specific model of the logic control chip U8 is EFM8LB11F32E-A-QFN 32.
The invention supports 112G multi-speed 10km QSFP28 optical module, which adopts a wavelength division multiplexing optical circuit and a wavelength division demultiplexing optical circuit to synthesize a plurality of wavelength optical signals into a beam, so that the optical module can be suitable for a plurality of fixed speeds, thus enhancing the universality of the 112G 10km QSFP28 optical module; the optical receiving unit and the optical transmitting unit are integrated with a clock data recovery circuit, so that the optical receiving unit and the optical transmitting unit have good high-frequency jitter removal characteristics and are beneficial to the recovery of clock data in the transmission process of synchronous data in network communication.
The above-described embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A multi-rate 10km QSFP28 optical module comprising:
the system comprises a light receiving unit, a digital diagnosis unit, an interface unit and a light emitting unit, wherein the light receiving unit and the light emitting unit are respectively connected with the digital diagnosis unit and provide light detection signals for the digital diagnosis unit; the light receiving unit is connected with the interface unit and converts a received light signal into an electric signal to be output; the light emitting unit is connected with the interface unit and converts an electric signal input by the interface unit into an optical signal to be output, the digital diagnosis unit is connected with the interface unit and processes the optical detection signal to obtain a digital diagnosis signal, and the digital diagnosis signal is sent to external communication equipment through the interface unit;
the optical receiving unit comprises a wavelength division demultiplexing optical circuit and an optical receiving circuit which are connected according to the transmission sequence of an optical circuit, wherein the wavelength division demultiplexing optical circuit receives a transmitted optical input signal and demultiplexes the received optical input signal to form a decomposed signal received by the optical receiving circuit, and the optical receiving circuit receives the transmitted decomposed signal and converts the decomposed signal into an electric signal;
the optical transmitting unit comprises a wavelength division multiplexing optical circuit, an optical transmitting circuit and a laser driver, wherein the laser driver transmits signals sent by the interface unit into the optical transmitting circuit, the optical transmitting circuit converts the input signals into optical signals and outputs the optical signals to the wavelength division multiplexing optical circuit, and the optical signals are generated and transmitted to the outside after the multiplexing function of the wavelength division multiplexing optical circuit.
2. A multi-rate 10km QSFP28 optical module according to claim 1, wherein:
the optical receiving unit further comprises a transimpedance amplification circuit and a clock data recovery circuit, the transimpedance amplification circuit is electrically connected with the optical receiving circuit and the clock data recovery circuit, the clock data recovery circuit is electrically connected with the interface unit, an electric signal generated by the optical receiving circuit is amplified by the transimpedance amplification circuit and transmitted to the clock data recovery circuit to be subjected to clock data sampling and cache processing, and the converted signal is transmitted to the interface unit.
3. A multi-rate 10km QSFP28 optical module according to claim 2, wherein:
the light emitting unit further comprises a pre-emphasis clock data recovery circuit, the pre-emphasis clock data recovery circuit is electrically connected with the interface unit and the laser driver, the pre-emphasis clock data recovery circuit receives input signals of the interface unit, performs modulation pre-emphasis processing, performs clock data sampling and buffering processing at the same time, and transmits the signals to the light emitting circuit through the laser driver.
4. A multi-rate 10km QSFP28 optical module according to claim 3, wherein:
the digital diagnosis unit comprises a logic control circuit and a signal conversion circuit, the logic control circuit is respectively electrically connected with the clock data recovery circuit and the pre-emphasis data recovery circuit to collect, process and monitor the data of the clock data recovery circuit and the pre-emphasis data recovery circuit 44, an internal memory of the logic control circuit stores module information and user information, and the signal conversion circuit is connected with the light receiving circuit and the laser driving circuit to complete conversion between analog signals and digital signals.
5. A multi-rate 10km QSFP28 optical module according to claim 4, wherein:
the signal conversion circuit is provided with a D/A converter and an A/D converter, the D/A converter is electrically connected with the laser driving circuit and the logic control circuit and can convert a digital signal of the logic control circuit into an analog signal which can be received by the laser driving circuit; the A/D converter is electrically connected with the logic control circuit and the light receiving circuit and can convert an analog signal sent by the light receiving circuit into a digital signal which can be received by the logic control circuit.
6. A multi-rate 10km QSFP28 optical module according to claim 5, wherein:
the light receiving circuit comprises a light receiving chip U62, a capacitor C29 and a capacitor C28, wherein an OUT0N pin, an OUT0P pin, an OUT1N pin, an OUT1P pin, an OUT2N pin, an OUT3P pin, an OUT3N pin and an OUT3P pin of the light receiving chip U62 are electrically connected with the transimpedance amplification circuit, an RSSI3 pin of the light receiving chip U62 is electrically connected with the signal conversion circuit, and one end of the capacitor C29 and one end of the capacitor C28 are electrically connected with a VCC4 pin of the light receiving chip U62; the other end of the capacitor C29 and the other end of the capacitor C28 are grounded.
7. A multi-rate 10km QSFP28 optical module according to claim 6, wherein:
the clock data recovery circuit comprises an amplifying chip U3, a capacitor C13, a capacitor C14, a capacitor C21, a capacitor C24, a capacitor C30, a capacitor C31, a capacitor C36 and a capacitor C38, wherein one end of the capacitor C13, one end of the capacitor C14, one end of the capacitor C21, one end of the capacitor C24, one end of the capacitor C30, one end of an upper capacitor C31, one end of the capacitor C36 and one end of the capacitor C38 are respectively electrically connected with an R1N1+ pin, an R1N 1-pin, an R1N 2-pin, an R1N2+ pin, an R1N 3-pin, an R1N3+ pin, an R1N 4-pin and an R1N4+ pin of the amplifying chip U3, and the other end of the capacitor C13, the other end of the capacitor C14, the other end of the capacitor C21, the other end of the capacitor C36 24, the other end of the capacitor C30 and the other end of the capacitor C31 are electrically connected with the optical receiving chip U31; the CS pin and the INTRPT pin of the amplification chip U3 are electrically connected with the digital diagnosis unit, and the ROUT 1-pin, the ROUT1+ pin, the ROUT 1-pin, the ROUT 2-pin, the ROUT2+ pin, the ROUT 3-pin, the ROUT3+ pin, the ROUT 4-pin and the ROUT4+ pin of the amplification chip U3 are electrically connected with the interface unit.
8. A multi-rate 10km QSFP28 optical module according to claim 7, wherein:
the light emitting circuit comprises a light emitting chip U15, a resistor R6 and a capacitor C34, wherein one end of the resistor R6 and one end of the capacitor C34 are electrically connected with an RTH pin of the light emitting chip U15, and the other end of the capacitor C34 is grounded; the pin SI3P, the pin SI3N, the pin SI2P, the pin SI2N, the pin SI1P, the pin SI1N, the pin SI0P and the pin SI0N of the light emitting chip U15 are electrically connected with the laser driving circuit.
9. A multi-rate 10km QSFP28 optical module according to claim 7, wherein:
the pre-emphasis clock data recovery circuit comprises a recovery chip U14, a resistor R101, a resistor R102, a capacitor C49, a capacitor C253, a capacitor C254, an inductor L18, an inductor L20, an inductor L22, an inductor L23, an inductor L24 and an inductor L28, wherein one end of the resistor R101 and one end of the resistor R102 are electrically connected with a CONFIG pin of the recovery chip U14, the other end of the resistor R101 is grounded, the other end of the resistor R102 is electrically connected with one end of the capacitor C49, and the other end of the capacitor C49 is grounded; one end of the capacitor C253 and one end of the capacitor C254 are electrically connected with a VCC _ CAP pin of the recovery chip U14, and the other end of the capacitor C253 and the other end of the capacitor C254 are grounded; the VCCL1 pin, the VCCL2 pin, the VCCL3 pin, the VCCL4 pin, the VCCL5 pin and the VCCL6 pin of the recovery chip U14 are electrically connected to the inductor L28, the inductor L22, the inductor L24, the inductor L23, the inductor L18 and the inductor L20, respectively.
10. A multi-rate 10km QSFP28 optical module according to claim 5, wherein:
the logic control circuit comprises a logic control chip U8, a capacitor C54, a capacitor C61, a capacitor C63, a capacitor C276, a capacitor C277, a resistor R8 and a resistor R89, wherein one end of the capacitor C54 is electrically connected with a P1.0 pin of the logic control chip U8, and the other end of the capacitor C54 is grounded; one end of the capacitor C61 and one end of the capacitor C63 are electrically connected with a VDD pin of the logic control chip U8, and the other end of the capacitor C61 and the other end of the capacitor C63 are grounded; one end of the capacitor C276, one end of the capacitor C277 and one end of the resistor R89 are electrically connected, the other end of the resistor R89 is electrically connected with the RSTb pin of the logic control chip U8, the other end of the capacitor C276 and the other end of the capacitor C277 are grounded, one end of the resistor R8 is electrically connected with the P1.0 pin of the logic control chip U8, and the other end of the resistor R8 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111153801.8A CN113904729A (en) | 2021-09-29 | 2021-09-29 | Multi-rate 10km QSFP28 optical module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111153801.8A CN113904729A (en) | 2021-09-29 | 2021-09-29 | Multi-rate 10km QSFP28 optical module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113904729A true CN113904729A (en) | 2022-01-07 |
Family
ID=79189392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111153801.8A Pending CN113904729A (en) | 2021-09-29 | 2021-09-29 | Multi-rate 10km QSFP28 optical module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113904729A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347802A (en) * | 2011-10-13 | 2012-02-08 | 苏州旭创科技有限公司 | 40G 40km CFP optical module |
| CN203151516U (en) * | 2013-01-18 | 2013-08-21 | 天津七所信息技术有限公司 | Multi-channel multi-rate wavelength converter |
| US20140056594A1 (en) * | 2006-10-13 | 2014-02-27 | Menara Networks, Inc. | Extended reach xfp transceiver with integrated forward error correction |
| CN208299802U (en) * | 2018-06-21 | 2018-12-28 | 武汉意谷光电科技有限公司 | A kind of 100G 10km QSFP28 optical module |
-
2021
- 2021-09-29 CN CN202111153801.8A patent/CN113904729A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140056594A1 (en) * | 2006-10-13 | 2014-02-27 | Menara Networks, Inc. | Extended reach xfp transceiver with integrated forward error correction |
| CN102347802A (en) * | 2011-10-13 | 2012-02-08 | 苏州旭创科技有限公司 | 40G 40km CFP optical module |
| CN203151516U (en) * | 2013-01-18 | 2013-08-21 | 天津七所信息技术有限公司 | Multi-channel multi-rate wavelength converter |
| CN208299802U (en) * | 2018-06-21 | 2018-12-28 | 武汉意谷光电科技有限公司 | A kind of 100G 10km QSFP28 optical module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11483089B2 (en) | Optical module | |
| CN110176960B (en) | Novel single-fiber bidirectional multichannel input optical module | |
| EP2976845B1 (en) | Pluggable optical host and network i/o optoelectronic module | |
| CN101902280B (en) | Self-contained MAC Ethernet passive optical network terminal SFP | |
| CN104348553A (en) | Cfp optical transceiver module | |
| CN105763245A (en) | Optical transceiving module | |
| CN210518344U (en) | 100G-QSFP28 optical transmission module based on PAM4 | |
| CN101669305B (en) | Multi-mode integrated circuit for use in optoelectronic devices | |
| CN102833004A (en) | 100G form-factor pluggable (CFP) optical module with transmission distance larger than 40 kilometers | |
| WO2023284540A1 (en) | Single-fiber bidirectional optical module, high-baud-rate signal transmission method, and 5g fronthaul network | |
| CN112615674A (en) | OLT optical transceiver integrated module, method and system for processing multiple PONs | |
| CN104467972A (en) | 100G QSFP28 SR4 parallel optical transceiver module and packaging method thereof | |
| CN214626994U (en) | 25G CWDM optical module | |
| CN208433971U (en) | A kind of 56G BIDI 40km SFP-DD optical module | |
| CN113904729A (en) | Multi-rate 10km QSFP28 optical module | |
| US9014552B2 (en) | Method and system for testing jitter compatibility | |
| CN208299802U (en) | A kind of 100G 10km QSFP28 optical module | |
| CN116192267A (en) | Data transmission device based on optical fiber | |
| CN115664527A (en) | Optical module and optical communication system | |
| CN106899352A (en) | A kind of photoelectric conversion device based on QSFP28 optical modules | |
| CN210927635U (en) | 10G SFP +1310nm60KM optical module | |
| CN217546059U (en) | Optical module | |
| CN207099076U (en) | A kind of signal processing apparatus and signal receiving device | |
| CN221929876U (en) | Communication device | |
| CN106209243B (en) | relay optical module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220107 |
|
| RJ01 | Rejection of invention patent application after publication |