CN113903309B - Shifting register unit, control method thereof and grid drive circuit - Google Patents

Abstract

Provide a shift register unit and its control method, gate drive circuit, the shift register unit includes: a first input circuit, used to provide the potential of the power signal terminal to the pull-up node under the control of the first control signal terminal; A reset circuit, used to provide the potential of the power supply signal terminal to the pull-down node and provide the potential of the reference signal terminal to the pull-up node under the control of the second control signal terminal; the second input circuit is used for the third control signal terminal and the clock signal The potential of the input signal terminal is provided to the pull-up node under the control of the terminal; the second reset circuit is used to control the potential of the pull-down node under the control of the clock signal terminal and the input signal terminal; an output circuit; and a control circuit.

Description

Shift register unit, control method thereof, and gate drive circuit

technical field

The present disclosure relates to the technical field of digital circuits, and in particular to a shift register unit, a control method thereof, and a gate drive circuit.

Background technique

In the current field of OLED display, the display is driven by GOA (Gate on Array) circuit and timing design. In the related art, two driving modes are mainly used for internal compensation, namely PE (Progressive emission) progressive sequential driving mode and SE (Simultaneous emission) full-screen simultaneous driving mode. The PE drive mode is line by line reset + compensation + lighting, the SE mode is full screen reset + compensation, and then writes data line by line, and finally the full screen is lighted at the same time. Under these two drive modes, multiple GOAs are often required to generate gate drive signals for reset, compensation, and data writing respectively. These GOAs have a large number of transistors and signal lines, and there are many cross-wire connections, which occupy a large space. .

Contents of the invention

In one aspect, a shift register unit is provided, including but not limited to: a first input circuit, connected to a first control signal terminal, a power signal terminal and a pull-up node of the shift register unit, configured to The potential of the power signal terminal is provided to the pull-up node under the control of the signal of the first control signal terminal; the first reset circuit is connected to the second control signal terminal, the power signal terminal, the reference signal terminal, and the pull-up node. and the pull-down node of the shift register unit, configured to provide the potential of the power signal terminal to the pull-down node and provide the potential of the reference signal terminal to the pull-down node under the control of the signal of the second control signal terminal. The pull-up node; the second input circuit, connected to the input signal terminal, the third control signal terminal, the clock signal terminal and the pull-up node, configured to be under the control of the third control signal terminal and the clock signal terminal providing the potential of the input signal terminal to the pull-up node; a second reset circuit, connected to the clock signal terminal, the input signal terminal, the power signal terminal and the pull-down node, configured to The potential of the pull-down node is controlled under the control of the clock signal terminal and the input signal terminal; the output circuit is connected to the pull-up node, the pull-down node, the power signal terminal, the reference signal terminal and the output a signal terminal configured to provide the signal of the power signal terminal to the output signal terminal under the control of the potential of the pull-up node, and to provide the signal of the reference signal terminal under the control of the potential of the pull-down node provided to the output signal terminal; and a control circuit, connected to the pull-up node and the pull-down node, configured to pull down the potential of the pull-down node according to the potential of the pull-up node, and to pull down the potential of the pull-down node according to the potential of the pull-down node to pull down the potential of the pull-up node.

In an exemplary embodiment of the present disclosure, the second reset circuit is further configured to electrically isolate the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal.

In an exemplary embodiment of the present disclosure, the second input circuit includes: a first transistor, the gate of the first transistor is connected to the clock signal terminal, and the first electrode of the first transistor is connected to the input signal terminal; a second transistor, the gate of the second transistor is connected to the third control signal terminal, the first pole of the second transistor is connected to the second pole of the first transistor, and the gate of the second transistor is connected to the second pole of the first transistor. The second pole is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, the gate of the first transistor is connected to the first clock signal terminal, and the second input The circuit further includes: a third transistor, the gate of the third transistor is connected to the pull-up node, and the first pole of the third transistor is connected to the second clock signal terminal; a fourth transistor, the fourth transistor The gate of the first capacitor is connected to the third control signal terminal, the first pole of the fourth transistor is connected to the second pole of the third transistor; the first capacitor, the first terminal of the first capacitor is connected to the pull-up node, the second end of the first capacitor is connected to the second pole of the fourth transistor.

In an exemplary embodiment of the present disclosure, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the second reset circuit includes: a fifth transistor, the gate of which is connected to the The second clock signal terminal, the first pole of the fifth transistor is connected to the power signal terminal; the sixth transistor, the gate of the sixth transistor is connected to the input signal terminal, and the first pole of the sixth transistor is connected to the input signal terminal. The pole is connected to the second clock signal terminal, the second pole of the sixth transistor is connected to the second pole of the fifth transistor; the seventh transistor, the gate of the seventh transistor is connected to the first pole of the fifth transistor Diode, the first pole of the seventh transistor is connected to the first clock signal end; the eighth transistor, the gate of the eighth transistor is connected to the first clock signal end, the first of the eighth transistor The pole is connected to the second pole of the seventh transistor, the second pole of the eighth transistor is connected to the pull-down node; the second capacitor, the first end of the second capacitor is connected to the gate of the seventh transistor, The second end of the second capacitor is connected to the second pole of the seventh transistor.

In an exemplary embodiment of the present disclosure, the second reset circuit further includes: a ninth transistor, the gate of the ninth transistor is connected to the second control signal terminal, and the first electrode of the ninth transistor is connected to The power signal end, the second pole of the ninth transistor is connected to the second pole of the fifth transistor.

In an exemplary embodiment of the present disclosure, the output circuit includes: a tenth transistor, the gate of the tenth transistor is connected to the pull-up node, and the first pole of the tenth transistor is connected to the power signal terminal , the second pole of the tenth transistor is connected to the output signal terminal; the eleventh transistor, the gate of the eleventh transistor is connected to the pull-down node, and the first pole of the eleventh transistor is connected to the Referring to the signal terminal, the second pole of the eleventh transistor is connected to the output signal terminal; the third capacitor, the first terminal of the third capacitor is connected to the pull-up node, and the second terminal of the third capacitor connected to the output signal terminal; a fourth capacitor, the first terminal of the fourth capacitor is connected to the pull-down node, and the second terminal of the fourth capacitor is connected to the reference signal terminal.

In an exemplary embodiment of the present disclosure, the first reset circuit includes: a first reset subcircuit connected to the second control signal terminal, the reference signal terminal and the pull-up node, configured to The potential of the reference signal terminal is provided to the pull-up node under the control of the signal of the second control signal terminal; the second reset subcircuit is connected to the second control signal terminal, the power signal terminal and the pull-down node , configured to provide the potential of the power signal terminal to the pull-down node under the control of the signal of the second control signal terminal.

In an exemplary embodiment of the present disclosure, the first reset subcircuit includes: a twelfth transistor, the gate of the twelfth transistor is connected to the second control signal terminal, and the gate of the twelfth transistor One pole is connected to the reference signal terminal, and the second pole of the twelfth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the first reset subcircuit includes: a thirteenth transistor, the gate of the thirteenth transistor is connected to the second control signal terminal, and the gate of the thirteenth transistor One pole is connected to the reference signal terminal; and a fourteenth transistor, the gate of the fourteenth transistor is connected to the second control signal terminal, and the first pole of the fourteenth transistor is connected to the thirteenth transistor The second pole of the fourteenth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the second reset subcircuit includes: a fifteenth transistor, the gate of the fifteenth transistor is connected to the second control signal terminal, and the gate of the fifteenth transistor is One pole is connected to the power signal terminal, and the second pole of the fifteenth transistor is connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the first input circuit includes: a sixteenth transistor, the gate of the sixteenth transistor is connected to the first control signal terminal, and the first The pole is connected to the power signal terminal, and the second pole of the sixteenth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the control circuit includes: a first control subcircuit connected to the pull-up node, the pull-down node and the reference signal terminal, configured to be at the potential of the pull-down node Under the control of the reference signal terminal, the potential of the reference signal terminal is provided to the pull-up node; the second control subcircuit, connected to the pull-up node, the pull-down node and the reference signal terminal, is configured to The potential of the reference signal terminal is provided to the pull-down node under the control of the potential of the node.

In an exemplary embodiment of the present disclosure, the first control subcircuit includes: a seventeenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, and the first electrode of the seventeenth transistor is connected to The reference signal end, the second pole of the seventeenth transistor is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the first control subcircuit includes: an eighteenth transistor, the gate of the eighteenth transistor is connected to the pull-down node, and the first electrode of the eighteenth transistor is connected to The reference signal terminal: a nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first pole of the nineteenth transistor is connected to the second pole of the eighteenth transistor, and the tenth transistor is connected to the second pole of the eighteenth transistor. The second pole of the nine transistors is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the second control subcircuit includes a twentieth transistor, the gate of the twentieth transistor is connected to the pull-up node, and the first electrode of the twentieth transistor is connected to The reference signal terminal and the second pole of the twentieth transistor are connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the second control subcircuit includes: a twenty-first transistor, the gate of the twenty-first transistor is connected to the pull-up node, and the gate of the twenty-first transistor The first pole is connected to the reference signal terminal; the gate of the twenty-second transistor is connected to the pull-up node, and the first pole of the twenty-second transistor is connected to the twenty-second A second pole of a transistor, the second pole of the twenty-second transistor is connected to the pull-down node.

In an exemplary embodiment of the present disclosure, the first reset subcircuit of the first reset circuit includes a thirteenth transistor and a fourteenth transistor, and the first control subcircuit of the control circuit includes an eighteenth transistor and a fourth transistor. Nineteen transistors, the shift register unit further includes: a twenty-third transistor, the gate of the twenty-third transistor is connected to the pull-up node, and the first pole of the twenty-third transistor is connected to the A power supply reference signal terminal, the second pole of the twenty-third transistor is connected to the second pole of the thirteenth transistor, the first pole of the fourteenth transistor, the second pole of the eighteenth transistor and The first pole of the nineteenth transistor.

In an exemplary embodiment of the present disclosure, the shift register unit further includes: a load circuit through which the output circuit is connected to an output signal terminal of the shift register unit.

A second aspect of the present disclosure provides a gate driving circuit, comprising multi-stage cascaded shift register units as described above.

In an exemplary embodiment of the present disclosure, the first control signal terminal of each shift register unit is connected to receive the first control signal, the second control signal terminal is connected to receive the second control signal, and the third control signal terminal is connected to Receive the third control signal; the input signal end of the shift register unit of the nth stage is connected to the output signal end of the shift register unit of the n-xth stage, wherein n is an integer greater than 1, and x is an integer greater than or equal to 1; the n-xth stage The first clock signal end of the shift register unit is connected to receive the first clock signal, and the second clock signal end of the n-x stage shift register unit is connected to receive the second clock signal; the first clock of the n stage shift register unit The signal end is connected to receive the second clock signal, and the second clock signal end of the shift register unit of the nth stage is connected to receive the first clock signal.

A third aspect of the present disclosure provides a method for controlling the shift register unit as described above, including: in the first stage, the first input circuit provides the potential of the power signal terminal to the upper level under the control of the signal of the first control signal terminal Pulling up the node, the potential of the pull-up node makes the output circuit provide the signal of the power signal terminal to the output signal terminal and makes the control circuit pull down the potential of the pull-down node, and the first reset circuit controls the signal of the second control signal terminal. The potential of the power signal terminal is provided to the pull-down node and the potential of the reference signal terminal is provided to the pull-up node, and the potential of the pull-down node makes the output circuit provide the signal of the reference signal terminal to the output signal terminal and the control circuit pulls down the the potential of the pull-up node; in the second stage, the second input circuit provides the potential of the input signal terminal to the pull-up node under the control of the third control signal terminal and the clock signal terminal, and the potential of the pull-up node causes the output circuit to The signal of the power signal terminal is provided to the output signal terminal and the control circuit pulls down the potential of the pull-down node, and the second reset circuit pulls up under the control of the signals of the clock signal terminal, the input signal terminal and the power signal terminal The potential of the pull-down node, the potential of the pull-down node makes the output circuit provide the signal of the reference signal terminal to the output signal terminal and makes the control circuit pull down the potential of the pull-up node.

In an exemplary embodiment of the present disclosure, the method further includes: in the first stage, the second reset circuit connects the power signal terminal and the pull-down signal terminal under the control of the clock signal terminal and the input signal terminal Nodes are electrically isolated.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be known that the drawings described below only relate to some embodiments of the present disclosure, rather than to restrictions, where:

Fig. 1 schematically shows a schematic block diagram of a shift register unit of an exemplary embodiment of the present disclosure;

Fig. 2 schematically shows a circuit diagram of a shift register unit according to another exemplary embodiment of the present disclosure;

Fig. 3 schematically shows a circuit diagram of a shift register unit according to yet another exemplary embodiment of the present disclosure;

Fig. 4 schematically shows a schematic block diagram of a gate drive circuit of an exemplary embodiment of the present disclosure;

FIG. 5 schematically shows a signal timing diagram of a shift register unit according to an exemplary embodiment of the present disclosure;

FIG. 6 schematically shows a simulation diagram of signal timing of a shift register unit according to an exemplary embodiment of the present disclosure;

FIG. 7 schematically shows a simulation diagram of signal timing of a gate drive circuit according to an exemplary embodiment of the present disclosure;

FIG. 8 schematically shows a driving effect diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure.

Detailed ways

Although the present disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments of the present disclosure, it should be understood before proceeding that those skilled in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the above description is a broad disclosure for those of ordinary skill in the art, and its content is not intended to limit the exemplary embodiments described in the present disclosure.

In addition, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in diagrammatic form to simplify the drawings.

The shift register unit, the control method thereof, and the gate driving circuit of the embodiments of the present disclosure will be described in detail below with reference to FIG. 1 to FIG. 8 .

Fig. 1 schematically shows a schematic block diagram of a shift register unit according to an exemplary embodiment of the present disclosure. As shown in FIG. 1 , the shift register unit of the embodiment of the present disclosure includes a first input circuit 100 , a second input circuit 200 , a first reset circuit 300 , a second reset circuit 400 , an output circuit 500 and a control circuit 600 .

The first input circuit 100 is connected to the first control signal terminal SC1, the power signal terminal VGH and the pull-up node Q of the shift register unit. The first input circuit 100 can provide the potential of the power signal terminal VGH to the pull-up node Q under the control of the signal of the first control signal terminal SC1.

The first reset circuit 300 is connected to the second control signal terminal SC2, the power signal terminal VGH, the reference signal terminal VGL, the pull-up node Q and the pull-down node QB of the shift register unit. The first reset circuit 300 can provide the potential of the power signal terminal VGH to the pull-down node QB and the potential of the reference signal terminal VGL to the pull-up node Q under the control of the signal of the second control signal terminal SC2.

The second input circuit 200 is connected to the input signal terminal STU, the third control signal terminal SC3 , the clock signal terminal CLK and the pull-up node Q. The second input circuit 200 can provide the potential of the input signal terminal STU to the pull-up node Q under the control of the third control signal terminal SC3 and the clock signal terminal CLK.

The second reset circuit 400 is connected to the clock signal terminal CLK, the input signal terminal STU, the power signal terminal VGH and the pull-down node QB. The second reset circuit 400 can pull up the potential of the pull-down node QB under the control of the clock signal terminal and the input signal terminal STU.

The output circuit 500 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal VGH, the reference signal terminal VGL and the output signal terminal OUT. The output circuit 500 can provide the signal of the power signal terminal VGH to the output signal terminal OUT under the control of the potential of the pull-up node QB, and provide the potential of the reference signal terminal VGL to the output signal terminal under the control of the potential of the pull-down node QB OUT.

The control circuit 600 connects the pull-up node Q and the pull-down node QB. The control circuit 600 can pull down the potential of the pull-down node QB according to the potential of the pull-up node Q, and pull down the potential of the pull-up node Q according to the potential of the pull-down node QB.

In some embodiments, the second reset circuit 400 can also electrically isolate the power signal terminal VGH from the pull-down node QB under the control of the clock signal terminal CLK and the input signal terminal STU.

Embodiments of the present disclosure can respectively generate a gate drive signal for compensation and reset and a gate drive signal for data writing by arranging two sets of input circuits and reset circuits in the shift register unit, and make both There is no mutual influence, so that multiple shift register units can be replaced to realize SE scanning.

FIG. 2 schematically shows a circuit diagram of a shift register unit according to another exemplary embodiment of the present disclosure.

As shown in FIG. 2 , the shift register unit includes a first input circuit 100 , a second input circuit 200 , a first reset circuit, a second reset circuit 400 , an output circuit 500 and a control circuit 600 . The above descriptions for the first input circuit 100 , the second input circuit 200 , the first reset circuit 300 , the second reset circuit 400 , the output circuit 500 and the control circuit 600 are also applicable to this embodiment.

In some embodiments, as shown in FIG. 2 , the clock signal terminals may include a first clock signal terminal CK and a second clock signal terminal XCK.

The second input circuit 200 may include a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the clock signal terminal (connected to the first clock signal terminal XCK in this embodiment), and the first pole of the first transistor T1 is connected to the input signal terminal STU. The gate of the second transistor T2 is connected to the third control signal terminal SC3, the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is connected to the pull-up node Q.

The second reset circuit 400 may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2. The gate of the fifth transistor T5 is connected to the second clock signal terminal CK, and the first electrode of the fifth transistor T5 is connected to the power signal terminal VGH. The gate of the sixth transistor T6 is connected to the input signal terminal STU, the first pole of the sixth transistor T6 is connected to the second clock signal terminal CK, and the second pole of the sixth transistor T6 is connected to the second pole of the fifth transistor T5. The gate of the seventh transistor T7 is connected to the second pole of the fifth transistor T5, and the first pole of the seventh transistor T7 is connected to the first clock signal terminal XCK. The gate of the eighth transistor T8 is connected to the first clock signal terminal XCK, the first pole of the eighth transistor T8 is connected to the second pole of the seventh transistor T7, and the second pole of the eighth transistor T8 is connected to the pull-down node QB. A first end of the second capacitor C2 is connected to the gate of the seventh transistor T7, and a second end of the second capacitor C2 is connected to the second electrode of the seventh transistor T7.

In some embodiments, the second reset circuit 400 may further include a ninth transistor T9. The gate of the ninth transistor T9 is connected to the second control signal terminal SC2, the first terminal of the ninth transistor T9 is connected to the power signal terminal VGH, and the second terminal of the ninth transistor is connected to the second terminal of the fifth transistor T5.

In some embodiments, the output circuit 500 may include: a tenth transistor T10, an eleventh transistor T11, a third capacitor C3 and a fourth capacitor C4. The gate of the tenth transistor T10 is connected to the pull-up node Q, the first pole of the tenth transistor T10 is connected to the power signal terminal VGH, and the second pole of the tenth transistor is connected to the output signal terminal OUT. The gate of the eleventh transistor T11 is connected to the pull-down node QB, the first pole of the eleventh transistor T11 is connected to the reference signal terminal VGL, and the second pole of the eleventh transistor T11 is connected to the output signal terminal OUT. A first terminal of the third capacitor C3 is connected to the pull-up node Q, and a second terminal of the third capacitor C3 is connected to the output signal terminal OUT. A first terminal of the fourth capacitor C4 is connected to the pull-down node QB, and a second terminal of the fourth capacitor C4 is connected to the reference signal terminal VGL.

In some embodiments, as shown in FIG. 2 , the first reset circuit may include a first reset subcircuit 310 and a second reset subcircuit 320 .

The first reset subcircuit 310 is connected to the second control signal terminal SC2 , the reference signal terminal VGL and the pull-up node Q. The first reset subcircuit 310 can provide the potential of the reference signal terminal VGL to the pull-up node Q under the control of the signal of the second control signal terminal SC2. In some embodiments, the first reset sub-circuit 310 may include a twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the second control signal terminal SC2, the first pole of the twelfth transistor T12 is connected to the reference signal terminal VGL, and the second pole of the twelfth transistor is connected to the pull-up node Q.

The second reset sub-circuit 320 is connected to the second control signal terminal SC2, the power signal terminal VGH and the pull-down node QB. The second reset sub-circuit 320 can provide the potential of the power signal terminal VGH to the pull-down node QB under the control of the signal of the second control signal terminal SC2. In some embodiments, the second reset sub-circuit 320 includes a fifteenth transistor T15. The gate of the fifteenth transistor T15 is connected to the second control signal terminal SC2, the first pole of the fifteenth transistor T15 is connected to the power signal terminal VGH, and the second pole of the fifteenth transistor T15 is connected to the pull-down node QB.

In some embodiments, the first input circuit 100 may include a sixteenth transistor T16. The gate of the sixteenth transistor T16 is connected to the first control signal terminal SC1 , the first pole of the sixteenth transistor T16 is connected to the power signal terminal VGH, and the second pole of the sixteenth transistor T16 is connected to the pull-up node Q.

In some embodiments, the control circuit 600 may include a first control subcircuit 610 and a second control subcircuit 620 .

The first control subcircuit 610 is connected to the pull-up node Q, the pull-down node QB and the reference signal terminal VGL. The first control sub-circuit 610 can provide the potential of the reference signal terminal VGL to the pull-up node Q under the control of the potential of the pull-down node QB. In some embodiments, the first control sub-circuit 610 includes a seventeenth transistor T17. The gate of the seventeenth transistor T17 is connected to the pull-down node QB, the first pole of the seventeenth transistor T17 is connected to the reference signal terminal VGL, and the second pole of the seventeenth transistor T17 is connected to the pull-up node Q.

The second control subcircuit 620 is connected to the pull-up node Q, the pull-down node QB and the reference signal terminal VGL. The second control subcircuit 620 can provide the potential of the reference signal terminal VGL to the pull-down node QB under the control of the potential of the pull-up node Q. In some embodiments, the second control subcircuit includes a twentieth transistor T20. The gate of the twentieth transistor T20 is connected to the pull-up node Q, the first pole of the twentieth transistor T20 is connected to the reference signal terminal VGL, and the second pole of the twentieth transistor is connected to the pull-down node QB.

Fig. 3 schematically shows a circuit diagram of a shift register unit according to yet another exemplary embodiment of the present disclosure.

As shown in FIG. 3, similar to FIG. 2, the shift register unit includes a first input circuit 100, a second input circuit 200', a first reset circuit, a second reset circuit 400, an output circuit 500 and a control circuit 600'. The first input circuit 100 , the second reset circuit 400 and the output circuit 500 may be the same as the above-mentioned first input circuit 100 , second reset circuit 400 and output circuit 500 respectively, and details are not repeated here. For the sake of brevity, the following will mainly describe the differences in detail.

As shown in Fig. 3, the second input circuit 200' includes not only the first transistor T1 and the second transistor T2, but also a third transistor T3, a fourth transistor T4 and a first capacitor C1.

The gate of the first transistor T1 is connected to the first clock signal terminal XCK, and the first pole of the first transistor T1 is connected to the input signal terminal STU. The gate of the second transistor T2 is connected to the third control signal terminal SC3, the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is connected to the pull-up node Q. The gate of the third transistor T3 is connected to the pull-up node Q, and the first electrode of the third transistor is connected to the second clock signal terminal. The gate of the fourth transistor T4 is connected to the third control signal terminal SC3, and the first pole of the fourth transistor T4 is connected to the second pole of the third transistor T3. A first end of the first capacitor C1 is connected to the pull-up node Q, and a second end of the first capacitor C1 is connected to the second pole of the fourth transistor T4.

As shown in FIG. 3 , the first reset circuit includes a first reset sub-circuit 310' and a second reset sub-circuit 320. Different from the first reset sub-circuit 310 of FIG. 2, the first reset sub-circuit 310' includes a thirteenth transistor T13 and a fourteenth transistor T14. The gate of the thirteenth transistor T13 is connected to the second control signal terminal SC2, and the first electrode of the thirteenth transistor T13 is connected to the reference signal terminal VGL. The gate of the fourteenth transistor T14 is connected to the second control signal terminal SC2 , the first electrode of the fourteenth transistor is connected to the second electrode of the thirteenth transistor T13 , and the second electrode of the fourteenth transistor T14 is connected to the pull-up node Q. The second reset sub-circuit 320 may be the same as the second reset sub-circuit 320 described above with reference to FIG. 2 , which will not be repeated here.

The control circuit 600' includes a first control sub-circuit 610' and a second control sub-circuit 620'. Different from the first control sub-circuit 610 in Fig. 2, the first control sub-circuit 610' includes an eighteenth transistor T18 and a nineteenth transistor T19. The gate of the eighteenth transistor T18 is connected to the pull-down node QB, and the first electrode of the eighteenth transistor is connected to the reference signal terminal VGL. The gate of the nineteenth transistor T19 is connected to the pull-down node QB, the first pole of the nineteenth transistor T19 is connected to the second pole of the eighteenth transistor, and the second pole of the nineteenth transistor is connected to the pull-up node Q. Different from the second control sub-circuit 620 of FIG. 2, the second control sub-circuit 620' includes a twenty-first transistor T21 and a twenty-second transistor T22. The gate of the twenty-first transistor T21 is connected to the pull-up node Q, and the first electrode of the twenty-first transistor is connected to the reference signal terminal VGL. The gate of the twenty-second transistor T22 is connected to the pull-up node Q, the first pole of the twenty-second transistor is connected to the second pole of the twenty-first transistor, and the second pole of the twenty-second transistor is connected to the pull-down node QB.

In FIG. 3 , the second pole of the thirteenth transistor T13 , the first pole of the fourteenth transistor T14 , the second pole of the eighteenth transistor T18 , and the first pole of the nineteenth transistor T19 are connected to the node off. In some embodiments, the shift register unit may further include a twenty-third transistor T23. The gate of the twenty-third transistor T23 is connected to the pull-up node Q, the first pole of the twenty-third transistor T23 is connected to the power signal terminal VGH, and the second pole of the twenty-third transistor T23 is connected to the node off. When the pull-up node Q is at a high level, the twenty-third transistor T23 is turned on, thereby providing the high level of the power signal terminal VGH to the node off. In this case, both the first pole and the second pole of the fourteenth transistor T14 are at a high level, thereby preventing the fourteenth transistor T14 from leaking electricity. Similarly, both the first pole and the second pole of the nineteenth transistor T19 are at high level, so as to prevent the nineteenth transistor T19 from leakage.

In some embodiments, the shift register unit further includes a load circuit 700 . The output circuit 500 is connected to the output signal terminal OUT of the shift register unit through the load circuit 700 . As shown in FIG. 3 , the load circuit 700 may include multiple load units, and each load unit includes a resistor R and a capacitor C. In a load unit, the first terminal of the resistor R is used as the input terminal of the load unit, the second terminal of the resistor R is used as the output terminal of the load unit, the first terminal of the capacitor C is connected to the second terminal of the resistor R, and the capacitor C The second end is grounded. The output end of each level of load unit is connected to the input end of the next level of load unit, thereby realizing the series connection of each load unit, wherein the input end of the first level of load unit is connected to the second pole of the tenth transistor and the second pole of the eleventh transistor The second pole is connected to the node G, and the output terminal of the last stage load unit is used as the output signal terminal OUT of the entire shift register unit.

Embodiments of the present disclosure also provide a gate drive circuit, which includes multi-stage cascaded shift register units as described above. The gate driving circuit will be described in detail below with reference to FIG. 4 .

FIG. 4 schematically shows a schematic block diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure.

As shown in FIG. 4 , the gate driving circuit includes multi-stage cascaded shift register units GOA_1 , GOA_2 , . . . (hereinafter collectively referred to as shift register unit GOA).

The first control signal terminal SC1 of each shift register unit GOA is connected to receive the first control signal Sc1, the second control signal terminal SC2 is connected to receive the second control signal Sc2, and the third control signal terminal SC3 is connected to receive the third control signal. Signal Sc3.

The input signal terminal STU of the shift register unit of the nth stage is connected to the output signal terminal OUT of the shift register unit of the n-x stage, wherein n is an integer greater than 1, and x is an integer greater than or equal to 1. For example, as shown in Figure 4, x=1, the input signal terminal STU of the first-stage shift register unit GOA_1 is connected to receive the start signal ST, and the input signal terminal STU of the second-stage shift register unit GOA_2 is connected to the first-stage shift register unit STU The output signal terminal OUT of the bit register unit GOA_1, the input signal terminal STU of the third-stage shift register unit GOA_3 is connected to the output signal terminal OUT of the second-stage shift register unit GOA_2, and so on.

The first clock signal terminal XCK of the shift register unit of the n-x stage is connected to receive the first clock signal XCk, and the second clock signal terminal CK of the shift register unit of the n-x stage is connected to receive the second clock signal Ck. The first clock signal terminal XCK of the shift register unit of the nth stage is connected to receive the second clock signal Ck, and the second clock signal terminal CK of the shift register unit of the nth stage is connected to receive the first clock signal XCk. For example, as shown in Figure 4, in the case of x=1, the first clock signal terminal XCK of the shift register unit GOA_1 of the first stage is connected to receive the first clock signal XCk, and the first clock signal terminal of the shift register unit GOA_1 of the first stage The second clock signal terminal CK is connected to receive the second clock signal Ck. The first clock signal terminal XCK of the second stage shift register unit GOA_2 is connected to receive the second clock signal Ck, and the second clock signal terminal CK of the second stage shift register unit GOA_2 is connected to receive the first clock signal XCk. The first clock signal terminal XCK of the third-stage shift register unit GOA_3 is connected to receive the first clock signal XCk, and the second clock signal terminal CK of the third-stage shift register unit GOA_3 is connected to receive the second clock signal Ck, thereby analogy.

In the embodiment of the present disclosure, the power signal terminal VGH of each shift register unit GOA is connected to receive the power signal Vgh, and the reference signal terminal VGL of each shift register unit GOA is connected to receive the reference signal Vgl.

Although the gate driving circuit of the embodiment of the present disclosure has been described above by taking x=1 as an example, the embodiment of the present disclosure is not limited thereto. In some embodiments, x can be set to other values as required. In this case, the signal waveform at the clock signal terminal and/or the number of clock signal terminals can be adaptively adjusted to achieve the same or the same as the above gate drive circuit. Similar functions will not be repeated here.

Embodiments of the present disclosure also provide a method for controlling the above-mentioned shift register unit. This method is applicable to the shift register unit of any of the above embodiments. The method includes a first phase and a second phase.

In the first stage, the first input circuit provides the potential of the power signal terminal to the pull-up node under the control of the signal of the first control signal terminal, and the potential of the pull-up node makes the output circuit provide the signal of the power signal terminal to the output signal terminal and makes the control circuit Pulling down the potential of the pull-down node, the first reset circuit provides the potential of the power signal terminal to the pull-down node and the potential of the reference signal terminal to the pull-up node under the control of the signal of the second control signal terminal, and the potential of the pull-down node makes the output circuit The reference signal The signal at the terminal is provided to the output signal terminal and causes the control circuit to pull down the potential of the pull-up node. The shift register unit generates gate drive signals for compensation and reset in the first phase, which is also referred to as the compensation and reset phase.

In the second stage, the second input circuit provides the potential of the input signal terminal to the pull-up node under the control of the third control signal terminal and the clock signal terminal, and the potential of the pull-up node makes the output circuit provide the signal of the power signal terminal to the output signal terminal and Make the control circuit pull down the potential of the pull-down node, the second reset circuit pulls up the potential of the pull-down node under the control of the signals of the clock signal terminal, the input signal terminal and the power signal terminal, and the potential of the pull-down node makes the output circuit provide the signal of the reference signal terminal to the output signal terminal and make the control circuit pull down the potential of the pull-up node Q. The shift register unit generates a gate driving signal for data writing in the second stage, which is also referred to as a data writing stage.

In some embodiments, in the first stage, the second reset circuit can also electrically isolate the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal.

The method for controlling the shift register unit provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 5 and FIG. 6 .

FIG. 5 schematically shows a signal timing diagram of a shift register unit according to an exemplary embodiment of the present disclosure. FIG. 6 schematically shows a simulation diagram of signal timing of a shift register unit according to an exemplary embodiment of the present disclosure. The signal timings in FIG. 5 and FIG. 6 will be described in detail below in conjunction with the shift register circuit in FIG. 3 .

As shown in Figure 5, the first clock signal terminal XCK, the second clock signal terminal CK, the first control signal terminal SC1, the second control signal terminal SC2 and the third control signal terminal SC3 of the shift register unit are respectively applied with the first The clock signal, the second clock signal, the first control signal, the second control signal and the third control signal apply the power signal and the reference signal to the power signal terminal VGH and the reference signal terminal VGL of the shift register unit respectively, and apply the power signal and the reference signal to the shift register The input signal terminal STU of the unit applies the input signal. The signals at the first clock signal terminal XCK, the second clock signal terminal CK, the first control signal terminal SC1, the second control signal terminal SC2 and the third control signal terminal SC3 may be AC signals, for example, the first clock signal terminal XCK and The signals at the second clock signal terminal CK are periodic signals and are mutually inverse, and the signals at the first control signal terminal SC1, the second control signal terminal SC2, the third control signal terminal SC3 and the input signal terminal STU are pulse signals. The signals at the power signal terminal VGH and the reference signal terminal VGL may be DC signals, for example, the power signal terminal VGH is at a constant high level, and the reference signal terminal VGL is at a constant low level.

The first stage includes period ① to period ⑤.

In period ①, as shown in Figure 5, the first control signal terminal SC1 is at high level, the second control signal terminal SC2 and the third control signal terminal SC3 are at low level, the input signal terminal STU is at high level, and the second control signal terminal SC1 is at high level. The second clock signal terminal CK is at low level, and the first clock signal terminal XCK is at high level. The high level of the first control signal terminal SC1 turns on the sixteenth transistor T16 to charge the pull-up node Q to a high level. The high level of the pull-up node Q turns on the tenth transistor T10 , and provides the high level of the power signal terminal VGH to the node G, so that the output signal terminal OUT outputs a high level. The high level of the input signal terminal STU turns on the sixth transistor T6, so that the point M is pulled to the low level of the second clock signal terminal CK. The low level at point M turns off the seventh transistor T7. At this time, although the high level of the first clock signal terminal XCK turns on the eighth transistor T8, due to the closing of the seventh transistor T7, the power signal terminal VGH is electrically isolated from the pull-down node QB, thereby avoiding the low voltage of the pull-down node QB. level is affected. The high level of the pull-up node Q also turns on the twenty-first transistor T21 and the twenty-second transistor T22, thereby pulling the pull-down node QB to a low level. The low level of the pull-down node QB turns off the eleventh transistor T11 so as not to affect the high level of the output signal terminal OUT. Here, due to resistance division, the voltage rise of the output signal terminal OUT is slower than the voltage rise of the pull-up node Q point, so the output signal terminal OUT and the pull-up node Q point are bootstrapped during the charging process, and the pull-up node Q point The potential should be higher than the power signal terminal VGH, thereby ensuring the lossless output of the output signal terminal OUT.

In period ②, the second clock signal terminal CK becomes high level, the first clock signal terminal XCK becomes low level, and the input signal terminal STU maintains high level. The second clock signal terminal CK becomes high level to turn on the fifth transistor T5, and the high level of the input signal terminal STU turns on the sixth transistor T6, so that point M is at high level. The high level of point M turns on the seventh transistor T7, and the low level of the first clock signal terminal XCK turns off the eighth transistor T8, which can still electrically isolate the power signal terminal VGH from the pull-down node QB, so that the pull-down node QB remains is low level. The presence of the first capacitor C1 keeps the pull-up node Q at a high level, and the output signal terminal OUT continues to output a high level.

In period ③, the second clock signal terminal CK becomes low level, the first clock signal terminal XCK becomes high level, and the input signal terminal STU maintains high level. The high level of the input signal terminal STU turns on the sixth transistor T6, thereby pulling down point M to the low level of the second clock signal terminal CK. The low level of the second clock signal terminal CK turns off the fifth transistor T5, the low level of point M turns off the seventh transistor T7, and the high level of the first clock signal terminal XCK turns on the eighth transistor T8. This makes the high level of the power signal terminal VGH still electrically isolated from the pull-down node QB, so that the pull-down node QB can continue to maintain a low level. The first capacitor C1 keeps the pull-up node Q at a high level, so that the output signal terminal OUT continuously outputs a high level.

In period ④, the operations of period ② and period ③ are repeated, the pull-up node Q is continuously at high level, and the pull-down node QB is continuously at low level, so that the output signal terminal OUT continuously outputs high level.

In period ⑤, the second control signal terminal SC2 is at high level, and the input signal terminal STU is at low level. The high level of the second control signal terminal SC2 turns on the fifteenth transistor T15 , thereby providing the high level of the power signal terminal VGH to the pull-down node QB. The high level of the pull-down node QB turns on the eighteenth transistor T18 and the nineteenth transistor T19 , thereby discharging the pull-up node Q point to the low level of the reference signal terminal VGL. The low level of the pull-up node Q turns off the twenty-first transistor T21 and the twenty-second transistor T22. The low level of the pull-up node Q also turns off the tenth transistor T10, and the high level of the pull-down node QB turns on the eleventh transistor T11, so that the node G is pulled down to the low level of the reference signal terminal VGL, and then the output The signal terminal OUT is pulled to low level.

After performing the operations from period ① to period ⑤, the full-screen reset and compensation time period is over. It can be seen from the function that its full-screen reset and compensation time can be adjusted through the second control signal terminal SC2. By setting the thirteenth transistor T13, The fourteenth transistor T14 , the eighteenth transistor T18 , the nineteenth transistor T19 and the seventh transistor T7 realize an anti-leakage design. From period ① to period ⑤, the high potential of the pull-up node Q needs to be maintained for a long time. This anti-leakage design can prevent the leakage of the pull-up node Q, thereby alleviating the abnormal output of the circuit due to the voltage instability of the pull-up node Q. Case.

The second stage may include period ⑥ to period ⑩.

In period ⑥, the second clock signal terminal CK and the third control signal terminal SC3 are at high level, and the first clock signal terminal XCK and the input signal terminal STU are at low level. The high level of the third control signal terminal SC3 turns on the second transistor T2. At this time, since the first clock signal terminal XCK is at low level, the first transistor T1 is turned off, and the pull-up node Q remains at low level. The high level of the second clock signal terminal CK turns on the fifth transistor T5, thereby providing the high level of the power signal terminal VGH to point M, and then turns on the seventh transistor T7. Although the seventh transistor T7 is turned on, the low level of the first clock signal terminal XCK makes the eighth transistor T8 turn off, so the pull-down node QB maintains a high level. The high level of the pull-down node QB turns on the twenty-first transistor T21 and the twenty-second transistor T22, thereby maintaining the pull-up node Q at a low level. The high level of the pull-down node QB turns on the eleventh transistor T11 , and the low level of the pull-up node Q turns off the tenth transistor T10 , so that the output signal terminal OUT remains at a low level.

In period ⑦, the second clock signal terminal CK is at low level, the first clock signal terminal XCK is at high level, and the third control signal terminal SC3 and the input signal terminal STU are at high level. The high levels of the third control signal terminal SC3 and the first clock signal terminal XCK enable the first transistor T1 and the second transistor T2 to be turned on, thereby charging the pull-up node Q to a high level. The high level of the pull-up node Q turns on the tenth transistor T10 , so that the output signal terminal OUT outputs a high level. The high level of the pull-up node Q also causes the pull-down node QB to discharge to a low level through the twenty-first transistor T21 and the twenty-second transistor T22, and the output signal terminal OUT outputs a high level. This stage is the gate pre-charging stage . During this process, the low level of the input signal terminal STU and the second clock signal terminal CK turns off both the fifth transistor T5 and the sixth transistor T6 , so that the point M is discharged to a low level. The low level at point M turns off the seventh transistor T7, and the high level at the first clock signal terminal XCK turns on the eighth transistor T8, so as not to affect the potential of the pull-down node QB.

In period ⑧, the second clock terminal CK is at high level, the first clock terminal XCK is at low level, and the third control signal terminal SC3 maintains high level. Since both the third control signal terminal SC3 and the pull-up node Q are at a high level, the third transistor T3 and the fourth transistor T4 are turned on, thereby providing the high level of the second clock signal terminal CK to the node A. At this time, due to the bootstrap effect of the first capacitor C1, the potential of the pull-up node Q is further increased, and due to the bootstrap effect of the third capacitor C3, the potential of the node G is also further increased, and the output signal terminal OUT generates lossless output .

In period ⑨, the second clock terminal CK is at low level, the first clock terminal XCK is at high level, and the input signal terminal STU is at low level. The presence of the second capacitor C2 keeps point M at a high level, so that the seventh transistor T7 and the eighth transistor T8 are turned on, and the pull-down node QB is charged to the high level of the first clock terminal XCK. The high level of the pull-down node QB turns on the eighteenth transistor T18 and the nineteenth transistor T19, and the pull-up node Q is pulled down to a low level by the eighteenth transistor T18 and the nineteenth transistor T19. Since the pull-up node Q is at a low level and the pull-down node Q is at a high level, the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, and the output signal terminal OUT is discharged to a low level.

In period ⑩, the second clock terminal CK receives a high level, and the first clock terminal XCK receives a low level. The eighth transistor T8 is turned off, so that the pull-down node QB maintains a high level, the pull-up node Q maintains a low level, and the output signal terminal OUT continues to maintain a low level.

Then, the operations of periods ⑨ and ⑩ are repeated, and the output signal terminal OUT is continuously maintained at a low level state.

As shown in Figure 6, in the first stage, that is, the reset and compensation stage, in response to the high level of the first control signal terminal SC1, the shift register unit generates a continuous high level output signal and outputs it at the output signal terminal OUT ; In response to the high level of the second control signal terminal SC2, the first reset circuit of the shift register unit resets the pull-down node QB to a high level and resets the pull-up node Q to a low level, so that the output signal terminal OUT The output signal goes low. In this way, the shift register unit generates gate drive signals for compensation and reset in the first stage.

In the second stage, that is, the data writing stage, the third control signal terminal SC3 is at a high level, and the shift register unit pulls the pull-up node Q to a high level based on the input signal at the input signal terminal STU, so that the output signal terminal OUT produces a high-level output signal. In response to the first arrival of the high level of the first clock signal XCK and the low level of the second clock signal CK, the second reset circuit of the shift register unit resets the pull-down node QB to a high level, and the control circuit pulls the pull-up node QB down to Low level, so that a low level output signal is generated at the output signal terminal OUT. In this way, the shift register unit generates gate driving signals for data writing in the second stage. It can be seen that the waveform of the gate driving signal generated in the second stage is different from the waveform of the gate driving signal generated in the first stage.

FIG. 7 schematically shows a simulation diagram of signal timing of a gate driving circuit according to an exemplary embodiment of the present disclosure. This timing diagram is applicable to the gate driving circuit of any of the above-mentioned embodiments.

The signal timing in FIG. 7 will be described in detail below in conjunction with the gate driving circuit in FIG. 4 . For ease of description, only the output signals OUT<1> of the shift registers from the first stage to the third stage, the shift registers from the 28th stage to the 30th stage, and the shift registers from the 52nd stage to the 54th stage are shown in FIG. 7 , OUT<2>, OUT<3>, OUT<28>, OUT<29>, OUT<30>, OUT<52>, OUT<53>, OUT<54>.

As shown in FIG. 7 , in the first stage, the shift registers of each stage perform the operations of the first stage described above under the control of the first control signal and the second control signal. For example, the first-stage shift register unit GOA1 adopts the signal timing of the first stage as shown in FIG. 5 to generate the output signal OUT<1>. Since the input signal terminal STU of the next-stage shift register unit GOA_2 is connected to the output signal terminal OUT of the upper-stage shift register unit GOA_1 and the clock signals of the two clock signal terminals are opposite to the first-stage shift register unit GOA_1, Therefore, the output signal OUT<1> of the output signal terminal OUT of the previous stage is used as the input signal of the input signal terminal STU of the next stage to generate the second stage output signal OUT<2 with the same waveform as the first stage output signal OUT<1> >. By analogy, the shift register units at all levels generate synchronous output signals in the first stage. As shown in the first stage in Figure 7, the outputs OUT<1>, OUT<2>, OUT<3>...OUT<28>, OUT<29>, OUT<30>...OUT<52>, OUT <53>, OUT<54> keep high level in the same period.

In the second stage, the shift registers of each stage perform the operation of the second stage as described above under the control of the first control signal and the second control signal. For example, the first-stage shift register unit GOA_1 adopts the signal timing of the first stage as shown in FIG. 5 to generate the output signal OUT<1>. Since the input signal terminal STU of the next-stage shift register unit GOA_2 is connected to the output signal terminal OUT of the upper-stage shift register unit GOA_1 and the clock signals of the two clock signal terminals are opposite to the first-stage shift register unit GOA_1, Therefore, the output signal OUT<1> of the output signal terminal OUT of the previous stage is used as the input signal of the input signal terminal STU of the next stage, and the second stage output signal OUT shifted relative to the output signal OUT<1> of the first stage is generated. <2>. By analogy, the shift register units at all levels generate sequentially shifted output signals in the first stage. As shown in the second stage in Figure 7, the outputs OUT<1>, OUT<2>, OUT<3>...OUT<28>, OUT<29>, OUT<30>...OUT<52>, OUT <53>, OUT<54> are sequentially shifted pulse signals.

FIG. 8 schematically shows a driving effect diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure.

As shown in FIG. 8, each frame includes a reset compensation phase, a data writing phase and a light emitting phase. In the reset compensation stage, the output signals of the shift registers at all levels in the gate drive circuit are all at high level, and remain at the high level for a period of time, thereby completing the functions of reset and compensation. After the reset compensation stage ends, the data writing stage is entered, and the shift registers in each cascade generate sequentially shifted output signals, so as to scan the pixels of the display area step by step, so as to write data to the pixels. After the data is written, it enters the light-emitting stage, and drives the pixels in the display area to emit light, thereby completing the display of one frame.

According to the embodiment of the present disclosure, by reducing the number of shift register units, the functions of reset compensation and data writing can be realized by using one shift register unit, which reduces the number of shift register units and can effectively reduce the The product frame adopts a shift register unit, which can reduce the number of signal lines, simplify the structure, and effectively improve the product yield.

Those skilled in the art can understand that the above-described embodiments are exemplary, and those skilled in the art can improve them, and the structures described in various embodiments do not conflict with each other in terms of structure or principle Can be combined freely.

After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and changes can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited by Implementation is limited to the exemplary embodiments set forth in the specification.

Claims (21)

1. A shift register unit, comprising: The first input circuit, connected to the first control signal terminal, the power signal terminal and the pull-up node of the shift register unit, is configured to provide the potential of the power signal terminal to the power supply signal terminal under the control of the signal of the first control signal terminal the pull-up node; The first reset circuit is connected to the second control signal terminal, the power signal terminal, the reference signal terminal, the pull-up node and the pull-down node of the shift register unit, and is configured as a signal at the second control signal terminal providing the potential of the power signal terminal to the pull-down node and providing the potential of the reference signal terminal to the pull-up node under the control of ; The second input circuit is connected to the input signal terminal, the third control signal terminal, the clock signal terminal and the pull-up node, and is configured to transfer the input signal under the control of the third control signal terminal and the clock signal terminal The potential of the terminal is provided to the pull-up node; The second reset circuit, connected to the clock signal terminal, the input signal terminal, the power signal terminal and the pull-down node, is configured to control the Pulling down the potential of the node, and electrically isolating the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal; an output circuit, connected to the pull-up node, the pull-down node, the power signal terminal, the reference signal terminal and the output signal terminal, configured to convert the power signal to The signal at the terminal is provided to the output signal terminal, and the potential of the reference signal terminal is provided to the output signal terminal under the control of the potential of the pull-down node; and a control circuit connected to the pull-up node and the pull-down node, configured to pull down the potential of the pull-down node according to the potential of the pull-up node, and pull down the pull-up node according to the potential of the pull-down node potential; The clock signal end includes a first clock signal end and a second clock signal end, and the second reset circuit includes: A fifth transistor, the gate of the fifth transistor is connected to the second clock signal terminal, and the first pole of the fifth transistor is connected to the power signal terminal; A sixth transistor, the gate of the sixth transistor is connected to the input signal terminal, the first pole of the sixth transistor is connected to the second clock signal terminal, and the second pole of the sixth transistor is connected to the first The second pole of the five transistors; a seventh transistor, the gate of the seventh transistor is connected to the second pole of the fifth transistor, and the first pole of the seventh transistor is connected to the first clock signal terminal; An eighth transistor, the gate of the eighth transistor is connected to the first clock signal terminal, the first pole of the eighth transistor is connected to the second pole of the seventh transistor, and the second pole of the eighth transistor connect said drop-down node; A second capacitor, the first end of the second capacitor is connected to the gate of the seventh transistor, and the second end of the second capacitor is connected to the second pole of the seventh transistor. 2. The shift register unit of claim 1, wherein the second input circuit comprises: a first transistor, the gate of the first transistor is connected to the clock signal terminal, and the first pole of the first transistor is connected to the input signal terminal; A second transistor, the gate of the second transistor is connected to the third control signal terminal, the first pole of the second transistor is connected to the second pole of the first transistor, and the second pole of the second transistor is Connect the pull-up node. 3. The shift register unit according to claim 2, wherein the clock signal terminal comprises a first clock signal terminal and a second clock signal terminal, and the gate of the first transistor is connected to the first clock signal terminal , the second input circuit further includes: a third transistor, the gate of the third transistor is connected to the pull-up node, and the first pole of the third transistor is connected to the second clock signal terminal; A fourth transistor, the gate of the fourth transistor is connected to the third control signal terminal, and the first pole of the fourth transistor is connected to the second pole of the third transistor; A first capacitor, the first end of the first capacitor is connected to the pull-up node, and the second end of the first capacitor is connected to the second pole of the fourth transistor. 4. The shift register unit according to claim 1, wherein the second reset circuit further comprises: a ninth transistor, the gate of which is connected to the second control signal terminal, and the ninth transistor The first pole of the transistor is connected to the power signal terminal, and the second pole of the ninth transistor is connected to the second pole of the fifth transistor. 5. The shift register unit of claim 3, wherein the output circuit comprises: A tenth transistor, the gate of the tenth transistor is connected to the pull-up node, the first pole of the tenth transistor is connected to the power signal terminal, and the second pole of the tenth transistor is connected to the output signal terminal ; An eleventh transistor, the gate of the eleventh transistor is connected to the pull-down node, the first pole of the eleventh transistor is connected to the reference signal terminal, and the second pole of the eleventh transistor is connected to the output signal terminal; a third capacitor, the first end of the third capacitor is connected to the pull-up node, and the second end of the third capacitor is connected to the output signal end; A fourth capacitor, the first terminal of the fourth capacitor is connected to the pull-down node, and the second terminal of the fourth capacitor is connected to the reference signal terminal. 6. The shift register unit according to claim 1, wherein the first reset circuit comprises: The first reset subcircuit, connected to the second control signal terminal, the reference signal terminal and the pull-up node, is configured to provide the potential of the reference signal terminal under the control of the signal of the second control signal terminal to said pull-up node; The second reset subcircuit, connected to the second control signal terminal, the power signal terminal and the pull-down node, is configured to provide the potential of the power signal terminal to the The dropdown node. 7. The shift register unit according to claim 6, wherein the first reset subcircuit comprises: A twelfth transistor, the gate of the twelfth transistor is connected to the second control signal terminal, the first pole of the twelfth transistor is connected to the reference signal terminal, and the second pole of the twelfth transistor Connect the pull-up node. 8. The shift register unit according to claim 6, the first reset subcircuit comprising: a thirteenth transistor, the gate of the thirteenth transistor is connected to the second control signal terminal, and the first pole of the thirteenth transistor is connected to the reference signal terminal; and A fourteenth transistor, the gate of the fourteenth transistor is connected to the second control signal terminal, the first pole of the fourteenth transistor is connected to the second pole of the thirteenth transistor, and the fourteenth transistor The second pole of the transistor is connected to the pull-up node. 9. The shift register unit according to claim 6, wherein the second reset subcircuit comprises: A fifteenth transistor, the gate of the fifteenth transistor is connected to the second control signal terminal, the first pole of the fifteenth transistor is connected to the power signal terminal, and the second pole of the fifteenth transistor is Connect the dropdown nodes. 10. The shift register cell of claim 1, wherein the first input circuit comprises: A sixteenth transistor, the gate of the sixteenth transistor is connected to the first control signal terminal, the first pole of the sixteenth transistor is connected to the power signal terminal, and the second pole of the sixteenth transistor is Connect the pull-up node. 11. The shift register unit of claim 1, wherein the control circuit comprises: The first control subcircuit, connected to the pull-up node, the pull-down node and the reference signal terminal, is configured to provide the potential of the reference signal terminal to the pull-up node under the control of the potential of the pull-down node node; The second control subcircuit, connected to the pull-up node, the pull-down node and the reference signal terminal, is configured to provide the potential of the reference signal terminal to the pull-down under the control of the potential of the pull-up node node. 12. The shift register unit of claim 11 , wherein the first control subcircuit comprises: A seventeenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first pole of the seventeenth transistor is connected to the reference signal terminal, and the second pole of the seventeenth transistor is connected to the Pull up nodes. 13. The shift register unit of claim 11 , wherein the first control subcircuit comprises: an eighteenth transistor, the gate of the eighteenth transistor is connected to the pull-down node, and the first pole of the eighteenth transistor is connected to the reference signal terminal; A nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first pole of the nineteenth transistor is connected to the second pole of the eighteenth transistor, and the second pole of the nineteenth transistor is Connect the pull-up node. 14. The shift register unit according to claim 11, wherein the second control subcircuit comprises a twentieth transistor, the gate of the twentieth transistor is connected to the pull-up node, and the twentieth A first pole of the transistor is connected to the reference signal terminal, and a second pole of the twentieth transistor is connected to the pull-down node. 15. The shift register unit of claim 11 , wherein the second control subcircuit comprises: A twenty-first transistor, the gate of the twenty-first transistor is connected to the pull-up node, and the first pole of the twenty-first transistor is connected to the reference signal terminal; A twenty-second transistor, the gate of the twenty-second transistor is connected to the pull-up node, the first pole of the twenty-second transistor is connected to the second pole of the twenty-first transistor, and the first pole of the twenty-second transistor is connected to the second pole of the twenty-first transistor. The second pole of the twenty-two transistor is connected to the pull-down node. 16. The shift register unit according to any one of claims 1 to 15, wherein the first reset subcircuit of the first reset circuit comprises a thirteenth transistor and a fourteenth transistor, and the control circuit The first control subcircuit includes an eighteenth transistor and a nineteenth transistor, and the shift register unit also includes: A twenty-third transistor, the gate of the twenty-third transistor is connected to the pull-up node, the first pole of the twenty-third transistor is connected to the power signal terminal, and the first pole of the twenty-third transistor is connected to the power signal terminal. Diodes are connected to the second pole of the thirteenth transistor, the first pole of the fourteenth transistor, the second pole of the eighteenth transistor, and the first pole of the nineteenth transistor. 17. The shift register unit according to any one of claims 1 to 15, further comprising: a load circuit, the output circuit is connected to an output signal terminal of the shift register unit through the load circuit. 18. A gate drive circuit comprising multi-stage cascaded shift register units according to any one of claims 1 to 17. 19. The gate drive circuit according to claim 18, wherein, The first control signal end of each shift register unit is connected to receive the first control signal, the second control signal end is connected to receive the second control signal, and the third control signal end is connected to receive the third control signal; The input signal end of the nth stage shift register unit is connected to the output signal end of the n-x stage shift register unit, wherein n is an integer greater than 1, and x is an integer greater than or equal to 1; The first clock signal end of the n-x shift register unit is connected to receive the first clock signal, and the second clock signal end of the n-x shift register unit is connected to receive the second clock signal; The first clock signal end of the shift register unit of the nth stage is connected to receive the second clock signal, and the second clock signal end of the shift register unit of the nth stage is connected to receive the first clock signal. 20. A method for controlling the shift register unit according to any one of claims 1 to 17, comprising: In the first stage, the first input circuit provides the potential of the power signal terminal to the pull-up node under the control of the signal of the first control signal terminal, and the potential of the pull-up node makes the output circuit provide the signal of the power signal terminal to the output signal terminal and make The control circuit pulls down the potential of the pull-down node, the first reset circuit provides the potential of the power signal terminal to the pull-down node and the potential of the reference signal terminal to the pull-up node under the control of the signal of the second control signal terminal, and the pull-down node The potential of the output circuit provides the signal of the reference signal terminal to the output signal terminal and causes the control circuit to pull down the potential of the pull-up node; In the second stage, the second input circuit provides the potential of the input signal terminal to the pull-up node under the control of the third control signal terminal and the clock signal terminal, and the potential of the pull-up node makes the output circuit provide the signal of the power signal terminal to the output signal terminal and make the control circuit pull down the potential of the pull-down node, and the second reset circuit pulls up the potential of the pull-down node under the control of the signals of the clock signal terminal, the input signal terminal and the power signal terminal, The potential of the pull-down node makes the output circuit provide the signal of the reference signal terminal to the output signal terminal and makes the control circuit pull down the potential of the pull-up node. 21. The method according to claim 20, further comprising: in the first stage, a second reset circuit electrically isolates the power signal terminal from the pull-down node under the control of the clock signal terminal and the input signal terminal .

Images