CN113900580B - Memory device, electronic device and related reading method - Google Patents

Abstract

The invention discloses a memory device capable of synchronously reading a plurality of memory modules, an electronic device and a reading method related to the memory device. The electronic device comprises a main control device, a first memory module and a second memory module. The main control device executes a read operation on the first memory module and the second memory module simultaneously. When the first memory module generates an update conflict during the read operation, the first memory module reports the update conflict to the master control device. After the synchronous data preparation period passes, the first memory module and the second memory module respectively transmit the first synchronous read data and the second synchronous read data to the master control device in the synchronous data reading period. Wherein the sync data preparation period is greater than the default read delay.

Description

Memory device, electronic device and related reading method

Technical Field

The present invention relates to a memory device, an electronic device and a related reading method, and in particular to a memory device capable of synchronously reading a plurality of memory modules, an electronic device and a related reading method.

Background Art

Portable electronic devices are becoming more and more popular, and the trend of audio and video applications has increased the demand for memory modules. Therefore, the storage capacity of memory modules is getting larger and larger. However, due to different applications, some electronic devices do not need to use large-capacity memory modules. In addition, large-capacity memory modules require more pin numbers, which becomes a limitation when designing embedded systems.

Please refer to FIG. 1, which is a schematic diagram of a memory module in an electronic device using a dynamic random access memory DRAM. The electronic device 10a includes a main control device 13a and a memory module 11a. The main control device 13a can be a controller or a digital signal processor (DSP) in an embedded system, and the memory module (DRAM) 11a uses dynamic random access memory (DRAM) technology. The main control device 13a uses a chip selection signal CS# to select the memory module (DRAM) 11a and transmits a control signal CTL to the memory module (DRAM) 11a. According to the control signal CTL and the system clock signal SCLK, the main control device 13a and the memory module (DRAM) 11a transmit the memory address and the read data DATm via the 64-bit system input and output signal line SIO[64:1]. The memory address includes the column address ADRr and the row address ADRc of the memory module (DRAM) 11a.

With the development of memory technology, the capacity of the memory module (DRAM) 11a using DRAM technology may be too large and the number of connections may be too many. Therefore, a memory module using pseudo static random access memory (PSRAM) has been developed on the market.

Please refer to FIG. 2, which is a schematic diagram of a memory module in an electronic device using a virtual static random access memory PSRAM. The electronic device 10b includes a main control device 13b and a memory module (PSRAM) 11b. The memory module (PSRAM) 11b uses a virtual static random access memory PSRAM technology. After the main control device 13b selects the memory module (PSRAM) 11b using the chip selection signal CS#, the control signal CTL is transmitted to the memory module (PSRAM) 11b. According to the control signal CTL, the system frequency signal SCLK and the data strobe mask signal (Read Data strobe/Write Data Mask, referred to as DQSM), the main control device 13 and the memory module (PSRAM) 11b use the 8-bit system input and output signal line SIO[8:1] to transmit the memory address and read data. For ease of explanation, the present invention uses the same symbol to represent the signal line and the signal transmitted using the signal line. For example, the control signal line CTL is used to transmit the control signal CTL.

Comparing FIG. 1 and FIG. 2, it can be seen that the number of system input and output signal lines SIO in the two drawings is very different. In addition, the number of control signals CTL required by the main control device 13a of FIG. 1 is more than the number of control signals CTL required by the main control device 13b of FIG. 2. Therefore, when the memory module (PSRAM) 11b is used, the main control device 13 requires fewer pins. In conjunction, the memory module (PSRAM) 11b using PSRAM technology has also become a trend in embedded systems.

When using PSRAM technology, the memory module needs to be continuously refreshed to maintain the stored data. If the memory module is being refreshed and a read command is received from the master device, the memory module cannot immediately perform the read operation because it is being refreshed. This phenomenon of being unable to immediately perform the read operation because the memory module is being refreshed is called a refresh collision.

When the memory module (PSRAM) 11b adopts the virtual static random access memory PSRAM technology, when the main control device 13b performs a read operation on the memory module (PSRAM) 11b, there may be two situations due to the different states of the memory module (PSRAM) 11b: a normal read operation, or a read operation under an update conflict. Below, FIG. 3A illustrates the waveform of the read operation of the memory module (PSRAM) 11b under normal circumstances (when no update conflict occurs), and FIG. 3B illustrates the waveform of the memory module (PSRAM) 11b when an update conflict occurs during the read operation.

3A and 3B , from top to bottom are the chip select signal CS#, the system clock signal SCLK, the data strobe mask signal DQSM, and the system input/output signal line SIO[8:1]. In the present invention, the horizontal axis of the waveform diagram is time.

Please refer to FIG. 3A, which is a waveform diagram of a general read operation performed by the master control device using the PSRAM memory module. First, the master control device 13b pulls down the chip select signal CS# corresponding to the memory module (PSRAM) 11b from a high level to a low level. Then, after the memory module 11b pulls down the data flash mask signal DQSM to a low level, the master control device 13b uses the system input and output signal lines SIO[8:1] to sequentially send a read command mCMDrd, a row address ADRr, and a row address ADRc to the memory module (PSRAM) 11b.

In the present invention, the period during which the master control device 13b transmits a read command mCMDrd is defined as a read command transmission period Tcmd; the period during which the master control device 13b transmits a memory address is defined as an address transmission period Tadr; the period during which the master control device 13b transmits a column address ADRr is defined as a column address period Tadr_r; the period during which the master control device 13b transmits a row address ADRc is defined as a row address period Tadr_c. For ease of explanation, the present invention uses dotted shading to represent the read command mCMDrd; uses horizontal shading to represent the column address ADRr; and uses vertical shading to represent the row address ADRc.

In the memory module (PSRAM) 11b, a read latency count (LC) may be defined. The read latency count LC represents the time required for the memory module (PSRAM) 11b to read the read data DATm from the memory array to the internal buffer after the master control device 13b obtains the row address. The present invention assumes that the read latency count LC is three times the system frequency period Tclk (LC=3*Tclk).

After the memory module (PSRAM) 11b receives the read command mCMDrd, the column address ADRr and the row address (columnaddress) ADRc, it needs to wait for a period of time before it can copy the read data DATm from the memory array to the internal buffer. As shown in FIG3A , if the memory module (PSRAM) 11b does not have an update collision, the period required by the memory module (PSRAM) 11b to copy the read data DATm from the memory array to the internal buffer depends on the preset read delay (dftLC=LC*1). The preset read delay (dftLC=LC*1) is calculated from the time when the memory module (PSRAM) 11b receives the column address mADRr (i.e., time point t5).

Once the preset read delay (dftLC=LC*1) ends (time point t8), the memory module (PSRAM) 11b generates two read strobe pulse signals mstrb1 and mstrb2 in succession using the data strobe mask signal DQSM at the next rising edge of the system clock signal SCLK (i.e., time point t9). While the read strobe pulse signals mstrb1 and mstrb2 are being generated, the memory module 11b also uses the system input/output signal line SIO[8:1] to transmit the read data DATm in the internal buffer to the main control device 13b.

Please refer to FIG3B, which is a waveform diagram of an update conflict occurring inside the memory module when the master device uses the PSRAM memory module for a read operation. Since the waveforms of FIG3A and FIG3B are roughly similar, the sequence of changes of the chip selection signal CS#, the system clock signal SCLK, the data flash mask signal DQSM, and the system input and output signal SIO[8:1] will not be repeated here.

Comparing FIG. 3A and FIG. 3B , it can be seen that in FIG. 3A , the memory module (PSRAM) 11b can transmit the read data DATm to the main control device 13b after waiting for the preset read delay (dftLC=LC*1). In FIG. 3B , the memory module (PSRAM) 11b must wait for the updated read delay rfcLC (for example, rfcLC=LC*2) before transmitting the read data DATm to the main control device 13b. The updated read delay rfcLC represents the number of read delay counts LC required for data reading after the update conflict occurs in the memory module (PSRAM) 11b. For ease of explanation, the present invention assumes that the updated read delay is two read delay counts (rfcLC=LC*2). In actual application, the number of read delay counts LC included in the updated read delay rfcLC is not limited to this.

In FIG. 3A , the data strobe mask signal DQSM rises from a low level to a high level at time t9, and is used to send read strobe pulse signals m1strb1 and m1strb2 during the period from time t9 to time t11. The memory module (PSRAM) 11b can notify the master control device 13b that the read data DATm is ready in the internal buffer through the change of the data strobe mask signal DQSM. Then, the memory module (PSRAM) 11b transmits the read data previously stored in the internal buffer to the system input/output signal line SIO[8:1] for access by the master control device 13b. Since the read operation performed by the master control device 13b on the memory module (PSRAM) 11b may be continuous, while the memory module (PSRAM) 11b transmits the read data previously stored in the internal buffer to the system input/output signal line SIO[8:1], the memory module (PSRAM) 11b will also continue to read data from the memory array and transmit it to the internal buffer.

In some applications, an electronic device may need to use multiple memory modules using PSRAM technology at the same time. For such an electronic device including multiple PSRAM memory modules at the same time, the host control device may not be able to correctly and synchronously obtain read data from multiple memory modules due to different update conflict states of the memory modules themselves.

Summary of the invention

The present invention relates to a memory device, an electronic device and a related reading method capable of synchronously reading multiple memory modules. When the memory device includes multiple memory modules and one of the memory modules has an update conflict, a main control device in the electronic device can still synchronously obtain read data from the memory module.

According to a first aspect of the present invention, a memory device electrically connected to a main control device is provided. The main control device performs a read operation on a first memory device during a read operation period (Trd), and the memory device includes: a first memory module (PSRAM1) and a second memory module (PSRAM2). The first memory module (PSRAM1) generates an update conflict during the read operation period. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first read instruction (m1CMDrd) and a second read instruction (m2CMDrd) transmitted by the main control device during a read instruction transmission period (Tcmd). The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first memory address (m1ADDr, m1ADDc) and a second memory address (m2ADDr, m2ADDc) during an address transmission period (Tadr). The read instruction transmission period (Tcmd) is earlier than the address transmission period (Tadr). After the synchronous data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the main control device during the synchronous data read period (Tdat_sync), respectively, wherein the synchronous data preparation period (Tsdatpr) is greater than a preset read delay (dftLC=LC*1).

According to a second aspect of the present invention, an electronic device is provided. The electronic device comprises: a memory device and a main control device. The memory device comprises: a first memory module (PSRAM1) and a second memory module (PSRAM2). The first memory module (PSRAM1) generates an update conflict during a read operation. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first read instruction (m1CMDrd) and a second read instruction (m2CMDrd) transmitted by the main control device during a read instruction transmission period (Tcmd). The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first memory address (m1ADDr, m1ADDc) and a second memory address (m2ADDr, m1ADDc) during an address transmission period (Tadr). The read instruction transmission period (Tcmd) is earlier than the address transmission period (Tadr). After the synchronous data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the main control device during the synchronous data read period (Tdat_sync), respectively, wherein the synchronous data preparation period (Tsdatpr) is greater than a preset read delay (dftLC=LC*1).

According to a third aspect of the present invention, a reading method applied to an electronic device is proposed. The electronic device includes a main control device, a first memory module (PSRAM1) and a second memory module (PSRAM2). The main control device performs a reading operation on the first memory module (PSRAM1) and the second memory module (PSRAM2) during a reading operation (Trd). The first memory module (PSRAM1) generates an update conflict during the reading operation, and the reading method includes the following steps. First, the first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first reading instruction (m1CMDrd) and a second reading instruction (m2CMDrd) transmitted by the main control device during a reading instruction transmission period. Secondly, the first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first memory address (m1ADRr, ADRc) and a second memory address (m2ADRr, m2ADRc) during an address transmission period (Tadr). Among them, the reading instruction transmission period (Tcmd) is earlier than the address transmission period (Tadr). After the synchronous data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the main control device during the synchronous data read period (Tdat_sync), respectively, wherein the synchronous data preparation period (Tsdatpr) is greater than a preset read delay (dftLC=LC*1).

In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a memory module in an electronic device using a dynamic random access memory DRAM.

FIG. 2 is a schematic diagram of a memory module in an electronic device using a virtual static random access memory PSRAM.

FIG. 3A is a waveform diagram of a general read operation performed by a master control device using a PSRAM memory module.

FIG. 3B is a waveform diagram showing an update conflict occurring inside the memory module when the master control device uses the PSRAM memory module to perform a read operation.

FIG. 4 is a schematic diagram of an electronic device including two memory modules using a pseudo static random access memory PSRAM.

FIG. 5 is a schematic diagram showing a master control device performing a read operation on the memory modules PSRAM1 and PSRAM2 in a default data synchronization manner.

FIG. 6 is a flow chart of a synchronous reading operation performed by a master control device on memory modules PSRAM1 and PSRAM2 in an electronic device according to an embodiment of the present invention.

FIG. 7A is a flow chart showing that when an update conflict occurs in the memory module PSRAM1, the memory module PSRAM1 notifies the host device in an immediate reporting mode (mode A) and performs a synchronous read operation according to the concept of the present invention.

7B is a flowchart of the memory module PSRAM1 notifying the host device in a delayed reporting mode (mode B) and performing a synchronous read operation when an update conflict occurs according to the concept of the present invention.

FIG. 8A is a waveform diagram of an embodiment of a synchronous read operation between the memory module PSRAM1 and the host device using the data strobe mask signal DQSM in combination with an immediate reporting mode (mode A) according to the concept of the present invention.

8B is a waveform diagram of an embodiment of a synchronous read operation between the memory module PSRAM1 and the host device using the data strobe mask signal DQSM in combination with a delayed reporting mode (mode B) according to the concept of the present invention.

FIG. 9A is a schematic diagram showing that a memory bank busy signal line BRBB is set between the memory modules PSRAM1 and PSRAM2 and the main control device, and is driven by the main control device.

FIG. 9B is a schematic diagram showing that a bank busy signal line BRBB is set between the memory modules PSRAM1 and PSRAM2 and the main control device, and is driven by the memory module PSRAM1 .

FIG. 10 is a waveform diagram of an embodiment of a synchronous read operation between the memory modules PSRAM1 and PSRAM2 and the host device using the bank busy signal line BRBB in combination with the immediate reporting mode (mode A) according to the concept of the present invention.

FIG. 11 is a waveform diagram of another embodiment of a synchronous read operation between the memory modules PSRAM1 and PSRAM2 and the host device in an immediate reporting mode (mode A) according to the concept of the present invention.

FIG. 12A is a schematic diagram showing that the chip select signal CS# is used as a communication interface for updating conflicts between the memory modules PSRAM1 and PSRAM2 and the host control device, and the chip select signal CS# is driven by the host control device.

12B is a schematic diagram showing that the memory modules PSRAM1 and PSRAM2 use the chip select signal CS# as a communication interface for updating conflicts with the main control device, and the chip select signal CS# is driven by the memory module PSRAM1.

13 is a waveform diagram of an embodiment in which the chip select signal CS# is used as the communication interface for updating conflicts between the memory modules PSRAM1 and PSRAM2 and the host device, and the memory module PSRAM1 notifies the host device according to the immediate reporting mode (mode A) and then performs a synchronous read operation.

14 is a waveform diagram of an embodiment of a synchronous read operation between the memory modules PSRAM1 and PSRAM2 and the host device using the chip select signal CS# in combination with the system clock signal SCLK according to the immediate reporting mode (mode A).

15 is a waveform diagram of an embodiment of setting frequency ignore signals ICK1 and ICK2 between the main control device and the memory modules PSRAM1 and PSRAM2 to perform a synchronous read operation when an update conflict occurs in the memory module PSRAM1.

16 is a schematic diagram showing that after the master control device learns that an update conflict occurs in the memory module PSRAM1 , the master control device stops generating the system clock signal SCLK so as to allow the memory modules PSRAM1 and PSRAM2 to perform a synchronous read operation.

FIG. 17 is a schematic diagram showing that the main control device issues a repeated read instruction to cause the memory modules PSRAM1 and PSRAM2 to perform a read operation synchronously.

18 is a waveform diagram of an embodiment of how to perform a synchronous read operation after an update conflict occurs in the memory module PSRAM1 using the chip selection signal CS# in combination with the system frequency signal SCLK between the memory modules PSRAM1 and PSRAM2 and the main control device according to the time difference of the pilot pulse signals m1pre and m2pre.

【Explanation of symbols】

11a, DRAM, 11b, 21, 22, PSRAM1, PSRAM2, 51, 52, 41, 42: memory modules

13a, 13b, 23, 53, 43: Main control device

CS#: Chip select signal (line)

SCLK: System frequency signal (line)

SIO[64:1], SIO[8:1], SIO[16:9]: system input and output signal lines

DQSM, DQSM[2:1], DQSM[1], DQSM[2]: Data strobe shield signal (line)

CTL: control signal (line)

10a, 10b, 20, 50, 40: Electronic devices

t1～t21: time point

Trd: During read operation

Tcs: Chip selection period

Tset: set period

LC: Read Latency Count

Tclk, Tclk1~Tclk10: system frequency cycle

Tend: End period

Tadr_r: Column address period

Tadr_c: row address period

mstrb1, mstrb2, m1strb1, m1strb2, m2strb1, m2strb2, m2strb1′, m2strb2′: read the flash pulse signal

mCMDrd: read command

ADRr, m1ADRr, m2ADRr: column address

ADRc, m1ADRc, m2ADRc: row address

DATm: Synchronous reading of data

Tcmd: Read command transmission period

Tadr: Address transfer period

25: Memory device

Tsdatpr: Synchronous data preparation period

Tdat_sync: Synchronous data reading period

DATm1, DATm2: Synchronous reading of data

m1CMDrd, m2CMDrd: read command

Trdnm: Normal read period

S51, S53, S55, S57, S59, S301a, S302a, S303a, S305a, S307a, S101a, S103a, S105a, S107a, S201a, S203a, S301b, S303b, S305b, S307b, S309b, S101b, S103b, S105b, S107b, S201b, S203b: Steps

Trdrf: Update conflict during read

Trfrp: Update conflict notification period

Taddwt: Additional waiting period

drpDATm2: discard data

Tdrp2: Data discard period

m1CMDrd_sp, m2CMDrd_sp: special read instructions

m2CMDext: Extended read command

Tcmdext: Extend the read instruction period

501, 511, 521, 401, 421, 411: Bidirectional interface circuit

501a, 521a, 511a, 401a, 421a, 411a: Output inverter

501b, 521b, 511b, 401b, 421b, 411b: Input inverter

BRBBh, BRBBm1, BRBBm2: Bank busy signals (lines)

50A, 40A: Pull-up resistor

Vcc: supply voltage

Tstp: Pause reading notification period

Tick: Frequency Ignore Period

ICK1, ICK2: Frequency ignore signal

m1CMDrtry, m2CMDrtry: Repeated read instruction

Tcmd_rtry: Repeated read instruction period

T2rd: Repeated read period

Tint: Chip selection spacing

m1pre, m2pre: pilot pulse signal

DETAILED DESCRIPTION

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

4 is a schematic diagram of an electronic device including two virtual static random access memory (PSRAM) memory modules. The electronic device 20 includes a main control device 23 and a memory device 25 , and the memory device 25 includes memory modules (PSRAM1 ) 21 and (PSRAM2 ) 22 .

The system input/output signal line SIO[16:1] of the master control device 23 includes 16 bits, of which 8 system input/output signal lines SIO[8:1] are connected to the memory module (PSRAM1) 21; the other 8 system input/output signal lines SIO[16:9] are connected to the memory module (PSRAM2) 22. The master control device 23 has two data strobe shield signal lines DQSM[2:1], of which the data strobe shield signal line DQSM[1] is connected to the memory module (PSRAM1) 21, and the data strobe shield signal line DQSM[2] is connected to the memory module (PSRAM2) 22.

The main control device 23 uses the chip selection signal CS# to select the memory modules (PSRAM1) 21 and (PSRAM2) 22. According to the system clock signal SCLK, the main control device 23 uses the system input and output signal lines SIO[8:1] and SIO[16:9] to transmit the memory addresses corresponding to the memory modules (PSRAM1) 21 and (PSRAM2) 22 to the memory modules (PSRAM1) 21 and (PSRAM2) 22, respectively, and the memory modules (PSRAM1) 21 and (PSRAM2) 22 use the system input and output signal lines SIO[8:1] and SIO[16:9] to transmit the read data DATm1 and DATm2 to the main control device 23. Among them, the memory address of the memory module (PSRAM1) 21 includes the column address m1ADRr and the row address m1ADRc, and the memory address of the memory module (PSRAM2) 22 includes the column address m2ADRr and the row address m2ADRc.

Please refer to FIG5, which is a schematic diagram of the master control device performing a read operation on the memory modules PSRAM1 and PSRAM2 in a default data synchronization mode. The waveforms in FIG5 are, from top to bottom, the chip select signal CS# and the system clock signal SCLK transmitted to the memory modules (PSRAM1) 21 and (PSRAM2) 22 at the same time, the data strobe mask signal DQSM[1] and the system input/output signal SIO[8:1] transmitted to the memory module (PSRAM1) 21, and the data strobe mask signal DQSM[2] and the system input/output signal SIO[16:9] transmitted to the memory module (PSRAM2) 22. When the data strobe mask signals DQSM[1] and DQSM[2] are not driven, they may be in a floating state. Alternatively, the undriven data strobe mask signals DQSM[1] and DQSM[2] may be maintained at a high level through a pull-up resistor, or the undriven data strobe mask signals DQSM[1] and DQSM[2] may be maintained at a low level through a pull-down resistor. The present invention assumes that the undriven data strobe mask signals DQSM[1] and DQSM[2] are maintained at a low level.

To simplify the description, several time parameters are defined in the following waveform diagram. These time parameters include: read operation period Trd, chip selection period Tcs, setting period Tset, read command transmission period Tcmd, address transmission period Tadr, synchronous data preparation period Tsdatpr, synchronous data reading period Tdat_sync. Next, the definitions of these time parameters are briefly introduced.

The read operation period Trd is the time required for the master control device 23 to perform a read operation on the memory modules (PSRAM1) 21 and (PSRAM2) 22. The chip selection period Tcs is the period during which the chip selection signal CS# is pulled low when the master control device 23 performs a read operation on the memory modules (PSRAM1) 21 and (PSRAM2) 22. The setting period Tset is the time difference between the time when the master control device 23 pulls the chip selection signal CS# low and before the master control device 23 starts to transmit the read instructions m1CMDrd and m2CMDre. The read instruction transmission period Tcmd is the time required for the master control device 23 to transmit the read instructions m1CMDrd and m2CMDre to the memory modules (PSRAM1) 21 and (PSRAM2) 22.

The address transmission period Tadr is the time required for the master control device 23 to synchronously transmit the memory address (including the column address m1ADRr and the row address m1ADRc) corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and to transmit the memory address (including the column address m2ADRr and the row address m2ADRc) corresponding to the memory module (PSRAM2) 22 to the memory module (PSRAM2) 22. The address transmission period Tadr further includes the column address period Tadr_r and the row address period Tadr_c. During the column address period Tadr_r, the master control device 23 transmits the column address m1ADRr corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and synchronously transmits the column address m2ADRr corresponding to the memory module (PSRAM2) 22 to the memory module (PSRAM2) 22. During the row address period Tadr_c, the master device 23 transmits the row address m1ADRc corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and synchronously transmits the row address m2ADRc corresponding to the memory module (PSRAM2) 22 to the memory module (PSRAM2) 22.

In addition, the synchronous data preparation period Tsdatpr is a period of time from the time when the master control device 23 transmits the memory address to the memory modules (PSRAM1) 21 and (PSRAM2) 22 to the time when the synchronous data reading period Tdat_sync starts. The length of the synchronous data preparation period Tsdatpr may vary significantly depending on the embodiment. The synchronous data reading period Tdat_sync is a period when the memory module (PSRAM1) 21 transmits the synchronous reading data DATm1 from the internal buffer to the master control device 23 via the system input-output signal line SIO[8:1], and the memory module (PSRAM2) 22 transmits the synchronous reading data DATm2 from the internal buffer to the master control device via the system input-output signal line SIO[16:9]. The end period Tend is the time difference between the end point of the chip selection period Tcs and the end point of the read operation period Trd.

In FIG5 , time point t1 to time point t11 is the read operation period Trd; time point t1 to time point t10 is the chip selection period Tcs; time point t1 to time point t2 is the setting period Tset; time point t2 to time point t3 is the read instruction transmission period Tcmd; time point t4 to time point t7 is the address transmission period Tadr; time point t7 to time point t9 is the synchronous data preparation period Tsdatpr; time point t9 to time point t11 is the synchronous data reading period Tdat_sync; time point t10 to time point t11 is the end period Tend. Among them, the synchronous data reading period Tdat_sync is less than 1 read delay count LC. In the default data synchronization mode, the memory module (PSRAM1) 21, (PSRAM2) 22 only needs to spend the period from time point t5 to time point t9 to start transferring the data of the internal memory to the system input and output signal line SIO[16:1]. Therefore, the period from the time point t5 to the time point t9 can be defined as the normal reading period Trdnm.

Since update conflicts do not frequently occur in the memory modules (PSRAM1) 21 and (PSRAM2) 22, the memory modules (PSRAM1) 21 and (PSRAM2) 22 usually perform normal read operations as shown in FIG5. However, in some cases, an update conflict may occur in one of the memory modules (PSRAM1) 21 and (PSRAM2) 22, causing the main control device 23 to be unable to correctly read the data stored in the memory modules (PSRAM1) 21 and (PSRAM2) 22 due to inconsistent read speeds.

Therefore, the present invention proposes a method that allows the memory modules (PSRAM1) 21 and (PSRAM2) 22 to flexibly respond to the occurrence of update conflicts and dynamically adjust the reading of data in the memory modules (PSRAM1) 21 and (PSRAM2) 22 in a manner of 1 read delay count LC or 2 read delay counts LC. For ease of explanation, it is assumed that an update conflict occurs in the memory module (PSRAM1) 21, while the memory module (PSRAM2) 22 can perform a normal read operation.

When no update conflict occurs in all memory modules (PSRAM1) 21 and (PSRAM2) 22, data is read with 1 read delay count LC. On the contrary, if any memory module (e.g., memory module (PSRAM1) 21) has an update conflict, the main control device 23 can still synchronously read data from the memory modules (PSRAM1) 21 and (PSRAM2) 22 through the reporting and notification mechanism. The present invention provides multiple embodiments, and the basic processes of these embodiments are shown in FIG6 .

Please refer to FIG. 6 for a flowchart of a synchronous read operation of the memory modules PSRAM1 and PSRAM2 by the main control device in an electronic device according to an embodiment of the present invention. First, the main control device 23 pulls down the level of the chip selection signal CS# and issues a read instruction to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (step S51). Next, it is determined whether any of the memory modules (PSRAM1) 21 and (PSRAM2) 22 has an update conflict (step S53). The method of step S53 may be determined by the main control device 23 after detection, or reported by the memory module (PSRAM1) 21 where the update conflict occurs. Regarding the determination method of step S53, different embodiments will be described later.

If the judgment result of step S53 is negative, it means that all memory modules (PSRAM1) 21 and (PSRAM2) 22 can complete the reading operation in the general data reading manner as shown in FIG5. Therefore, after the memory modules (PSRAM1) 21 and (PSRAM2) 22 prepare to read data in the default data synchronization manner (Tsdatpr＜LC) during the synchronous data preparation period Tsdatpr (step S55), they transmit the synchronous read data DATm1 and DATm2 to the master control device 23 during the synchronous data reading period Tdat_sync (step S59).

On the other hand, the judgment result of step S53 is positive, which means that one or more memory modules (PSRAM1) 21 have an update conflict. At this time, the one or more memory modules (PSRAM1) 21 that have an update conflict cannot complete data acquisition within the preset read delay (dftLC=LC*1). Since the memory module (PSRAM1) 21 that has an update conflict needs a longer read period to copy the read data from the memory array to the internal buffer. Therefore, the memory module (PSRAM2) 22 that has no update conflict must delay its read operation speed to be consistent with the read speed of the memory module (PSRAM1) 21. Therefore, the main control device 23 needs to notify the memory module (PSRAM2) 22 that has no update conflict that it will prepare to read data in a special data synchronization manner. When reading data using a special data synchronization method, the memory modules (PSRAM1) 21 and (PSRAM2) 22 need to wait for a longer synchronization data preparation period Tsdatpr (Tsdatpr＞LC) (step S57), and then transmit the synchronization read data DATm1 and DATm2 to the main control device 23 during the synchronization data reading period Tdat_sync.

According to the concept of the present invention, the main control device 23 can automatically sense the phenomenon of update conflict in the memory module (PSRAM1) 21. Alternatively, when the memory module (PSRAM1) 21 has an update conflict, it can actively report this situation to the main control device 23. The memory module (PSRAM1) 21 can notify the main control device 23 of the phenomenon of update conflict occurring inside it through two reporting modes, immediate reporting mode (mode A) and delayed reporting mode (mode B). The immediate reporting mode (mode A) means that if the memory module (PSRAM1) 21 has an internal update conflict, the memory module (PSRAM1) 21 immediately notifies the main control device 23 about the update conflict occurring inside it after the chip select signal CS# is pulled low. The delayed reporting mode (mode B) means that if the memory module (PSRAM1) 21 has an internal update conflict, the memory module (PSRAM1) 21 will not notify the main control device 23 about the situation of update conflict occurring inside it until the memory module (PSRAM1) 21 receives the column address m1ADRr from the main control device 23.

Next, FIG. 7A illustrates the read process when the memory module (PSRAM1) 21 notifies the master control device 23 of the update conflict situation that occurs inside it in the immediate reporting mode (mode A); and FIG. 7B illustrates the read process when the memory module (PSRAM1) 21 notifies the master control device 23 of the update conflict situation that occurs inside it in the delayed reporting mode (mode B). In FIG. 7A and FIG. 7B, the order of the processes is from top to bottom, and from left to right are the processes performed by the master control device 23, the memory module (PSRAM1) 21, and the memory module (PSRAM2) 22. In FIG. 7A and FIG. 7B, the arrow direction represents the transmission direction of the signal, and the dashed arrow direction represents that it can be selectively executed according to different embodiments.

Please refer to FIG. 7A for a flowchart of the memory module PSRAM1 notifying the main control device in an immediate reporting mode (mode A) and performing a synchronous read operation when an update conflict occurs according to the concept of the present invention. First, the main control device 23 pulls down the chip selection signal CS# corresponding to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (S301a). Then, the memory module (PSRAM1) 21 confirms that an update conflict has occurred (step S101a). Then, the memory module (PSRAM1) 21 notifies the main control device 23 about the situation in which an update conflict has occurred internally (step S103a). The details of how the memory module (PSRAM1) 21 notifies the main control device 23 of the update conflict that has occurred internally may vary according to different embodiments, and will be further explained later.

Afterwards, the main control device 23 transmits the read commands m1CMDrd and m2CMDrd to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (step S302a), and notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that they must be read in a special data synchronization manner (step S303a). Depending on the embodiment, step S302a and step S303a may be performed together, or step S302a and step S303a may be performed separately.

The method by which the master control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 to read data in a special data synchronization manner may vary according to different embodiments, and will be further described later. Please also note that although step S303a must wait until step S103a is completed before it can be performed, step S303a is not limited to being performed immediately after step S103a is completed. For example, step S303a can also be performed after step S307a is completed.

Next, the main control device 23 uses the system input-output signal SIO[16:1] to transmit the column addresses m1ADRr, m2ADRr and row addresses m1ADRc, m2ADRc of the memory modules (PSRAM1) 21 and (PSRAM2) 22 in sequence (steps S305a and S307a). The system input-output signal SIO[8:1] is used to transmit the column address m1ADRr and row address m1ADRc corresponding to the memory module (PSRAM1) 21; the system input-output signal SIO[16:9] is used to transmit the column address m2ADRr and row address m2ADRc corresponding to the memory module (PSRAM2) 22.

After the memory module (PSRAM1) 21 waits for the update conflict to end (step S105a), it transmits the synchronous read data DATm1 to the master device 21 using the system input-output signal SIO[8:1] (step S107a). While the memory module (PSRAM1) 21 transmits the read data DATm1, the memory module (PSRAM2) 22 waits for the synchronous data preparation period Tsdatpr to end (step S201a), and then transmits the synchronous read data DATm2 to the master device 23 using the system input-output signal SIO[16:9] (step S203a).

Please refer to FIG. 7B for a flowchart of the memory module PSRAM1 notifying the master device in delayed reporting mode (mode B) and performing a synchronous read operation according to the present invention when an update conflict occurs. First, the master device 23 pulls down the chip select signal CS# of the memory modules (PSRAM1) 21 and (PSRAM2) 22 (S301b). Then, the master device 23 sends read commands m1CMDrd, m2CMDrd and column addresses m1ADRr, m2ADRr to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (steps S303b, S305b).

After the memory module (PSRAM1) 21 confirms that an update conflict has occurred (step S101b), the memory module (PSRAM1) 21 will notify the master control device 23 of the situation in which an update conflict has occurred internally (step S103b). At the same time, the master control device 23 uses the system input/output signal line SIO[16:1] to transmit the row addresses m1ADRc and m2ADRc to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (step S307b). Afterwards, the master control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that they must be read in a special data synchronization manner (step S309a).

After the memory module (PSRAM1) 21 waits for the update conflict to end (step S105b), it transmits the synchronous read data DATm1 of the internal buffer to the master device 21 using the system input-output signal SIO[8:1] (step S107b). On the other hand, after the memory module (PSRAM2) 22 waits for the synchronous data preparation period Tsdatpr to end (step S201b), it transmits the synchronous read data DATm2 of the internal buffer to the master device 21 using the system input-output signal SIO[16:9] (step S203b).

Please refer to FIG. 7A and FIG. 7B at the same time. It can be seen that the steps required to be performed in the two flow charts are roughly similar. The main difference between the two is that the memory module (PSRAM1) 21 notifies the main control device 23 that an update conflict occurs (step S103a of FIG. 7A and step S103b of FIG. 7B), and the main control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that they must be read in a special data synchronization manner (step S303a of FIG. 7A and step S309b of FIG. 7B). In the immediate reporting mode (mode A) (FIG. 7A), the memory module (PSRAM1) 21 notifies the main control device 23 of the update conflict before the main control device 23 transmits the read commands m1CMDrd, m2CMDrd and the column addresses m1ADRr, m2ADRr. In the delayed reporting mode (mode B) ( FIG. 7B ), the memory module ( PSRAM1 ) 21 notifies the host control device 23 of the update conflict only after the host control device 23 transmits the read commands m1CMDrd, m2CMDrd and the column addresses m1ADRr, m2ADRr.

Memory modules can be divided into single bank and multi-bank. Among them, the memory module of single bank can know whether there is an update conflict inside it at the moment when the chip select signal CS# is pulled low. On the other hand, the memory module of multi-bank must wait for the column address m1ADRr and m2ADRr to be received before determining whether an update conflict occurs. Therefore, the immediate reporting mode (Mode A) can be applied to the memory module of single bank, and the delayed reporting mode (Mode B) can be applied to the memory modules of single bank and multi-bank. The embodiments provided below will respectively illustrate the method of using the immediate reporting mode (Mode A) and the delayed reporting mode (Mode B) of the memory module (PSRAM1) 21 to report the update conflict.

According to the embodiment of the present invention, when the memory module (PSRAM1) 21 reports the update conflict situation to the main control device 23, in addition to the reporting time point that can be changed according to different embodiments, the medium and means by which the memory module (PSRAM1) 21 notifies the main control device 23 can also be different. For example, the memory module (PSRAM1) 21 can use different signal lines and various combinations of control waveforms of the signal lines to notify the main control device 23.

Next, the present invention will describe the corresponding waveform diagrams of the embodiments of the reading method based on the concept of the present invention. First, FIG8A and FIG8B use the existing data flash mask signal DQSM as the transmission medium to respectively describe the methods of using the immediate reporting mode (mode A) and the delayed reporting mode (mode B). The following will provide related embodiments using different signal lines as the transmission medium.

Please refer to FIG8A, which is a waveform diagram of an embodiment of a synchronous read operation between a memory module and a host device using a data flash mask signal DQSM in combination with an immediate reporting mode (mode A) according to the concept of the present invention. In this figure, time point t1 to time point t15 is a read operation period Trd; time point t1 to time point t14 is a chip selection period Tcs; time point t1 to time point t3 is a setting period Tset; time point t3 to time point t4 is a read command transmission period Tcmd; time point t4 to time point t8 is an address transmission period Tadr; time point t8 to time point t13 is a synchronous data preparation period Tsdatpr; time point t13 to time point t15 is a synchronous data reading period Tdat_sync; time point t14 to time point t15 is an end period Tend.

After the master control device 23 pulls the chip select signal CS# to a low level at time t1, the memory module (PSRAM1) 21 starts to notify the master control device 23 that an update conflict has occurred by pulling the level of the data strobe mask signal DQSM[1] high at time t2. The memory module (PSRAM1) 21 maintains the data strobe mask signal DQSM[1] at a high level from time t2 to time t7, and starts to pull the data strobe mask signal DQSM[1] to a low level at time t7. The period from time t2 to time t7 can be defined as the update conflict notification period Trfrp, in which the memory module (PSRAM1) 21 that has an update conflict notifies the master control device 23 of the update conflict.

On the other hand, the memory module (PSRAM2) 22 has been maintaining the data strobe mask signal DQSM[2] at a low level before time t10. At time t2, the master control device 23 has grasped the status of the memory modules (PSRAM1) 21 and (PSRAM2) 22 through the high-level data strobe mask signal DQSM[1] and the low-level data strobe mask signal DQSM[2], respectively. Among them, the high-level data strobe mask signal DQSM[1] indicates that the memory module PSRAM1 has an update conflict, while the low-level data strobe mask signal DQSM[2] indicates that the memory module (PSRAM2) 22 has not an update conflict.

Next, during the period from time point t3 to time point t4 (the period Tcmd during which the read command is transmitted), the master control device 23 uses the system input-output signal SIO[8:1] to send a special read command m1CMDrd_sp to the memory module (PSRAM1) 21, and uses the system input-output signal SIO[16:9] to send a special read command m2CMDrd_sp to the memory module (PSRAM2) 22. Once the memory module (PSRAM2) 22 receives the special read command m2CMDrd_sp, it knows that the read operation should be slowed down. Here, the dotted background with a thick frame represents the special read commands m1CMDrd_sp and m2CMDrd_sp. Accordingly, at time point t4, the memory module (PSRAM2) 22 has learned through the special read command m2CMDrd_sp issued by the master control device 23 that it should not be performed at the speed of the general read operation, and needs to wait for the memory module (PSRAM1) 21 to complete its update conflict.

As mentioned above, the memory modules (PSRAM1) 21 and (PSRAM2) 22 start counting the read delay count after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG8A that the memory modules (PSRAM1) 21 and (PSRAM2) 22 both start counting the read delay count from time point t5. Among them, the memory module (PSRAM1) 21 needs to spend two read delay counts (LC*2) until time point t12 to obtain the read data from the internal memory array to the internal buffer, while the memory module (PSRAM2) 22 only needs one read delay count (LC*1) to obtain the read data from the internal memory array to the internal buffer from time point t9. Next, how and when the memory modules (PSRAM1) 21 and (PSRAM2) 22 transmit the synchronous read data DATm1 and DATm2 from the internal buffer are respectively described.

The update conflict of the memory module (PSRAM1) 21 ends at time t12, and at the next rising edge of the system clock signal SCLK (i.e., time t13), the read strobe pulse signals m1strb1 and m1strb2 are generated successively with the data strobe mask signal DQSM[1]. Here, the time point t5 to the time point t13 is defined as the update conflict read period Trdrf. The update conflict read period Trdrf represents the read delay count (LC*2) required for the memory module to wait for the update to complete, plus the period required to wait for the next rising edge of the system clock signal SCLK. That is, Trdrf=LC*2+(time point t12 to time point t13). In FIG. 8A, the memory module (PSRAM1) 21 starts to transmit the synchronous read data DATm1 from time point t13.

Since the memory module (PSRAM2) 22 can prepare the read data in the internal buffer at the end of a read delay count (i.e., time point t9), and transmit the read strobe pulse signals m2strb1′, m2strb2′ to the master device 23 in succession using the data strobe mask signal DQSM[2] at the next rising edge of the system clock signal SCLK (i.e., time point t10), the memory module (PSRAM2) 22 starts to transmit the read data from the internal buffer to the system input/output signal SIO[16:9] from time point t10. Since the read data transmitted by the memory module (PSRAM2) 22 from time point t10 to time point t11 will not be adopted by the master device 23, the read data transmitted by the memory module (PSRAM2) 22 from time point t10 to time point t11 can be referred to as discarded data drpDATm2, and the period during which the memory module (PSRAM2) 22 transmits the discarded data drpDATm2 can be defined as the data discard period Tdrp2.

After that, the memory module (PSRAM2) 22 will remain idle for a period of time (from time t11 to time t13), and then generate and transmit the read strobe pulse signals m2strb1 and m2strb2 again using the data strobe mask signal DQSM[2] from time t13. In addition, the memory module (PSRAM2) 22 will also transmit the read data from the internal buffer to the system input/output signal SIO[16:9] from time t13. According to the concept of the present invention, the read data transmitted by the memory module (PSRAM2) 22 from time t13 is synchronized with the read data transmitted by the memory module (PSRAM1) 21 from time t13. Therefore, the read data transmitted by the memory modules (PSRAM1) 21 and (PSRAM2) 22 from time t13 are referred to as synchronized read data DATm1 and DATm2.

According to the concept of the present invention, the main control device 23 does not use the discarded data drpDATm2 transmitted by the memory module (PSRAM2) 22 during the period from time t10 to time t11, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2) 22 during the period from time t13 to time t15. Therefore, the period from time t10 to t11 is defined as the data discard period Tdrp2. The content of the discarded data drpDATm2 transmitted by the internal buffer of the memory module (PSRAM2) 22 after reading the strobe pulse signals m2strb1′, m2strb2′ using the system input and output signal SIO[16:9] and the content of the synchronous read data DATm2 transmitted after reading the strobe pulse signals m2strb1, m2strb2 are exactly the same.

Even if the memory module (PSRAM2) 22 transmits read data during the period from time point t10 to time point t11, it is still necessary to retransmit the read data starting from time point t13. Therefore, time point t9 to time point t13 is equivalent to the period that the memory module (PSRAM2) 22 needs to spend waiting for the update conflict of the memory module (PSRAM1) 21 to end. Since the period from time point t9 to time point t13 is not the period required for the memory module (PSRAM2) 22 (where no update conflict occurs) to perform its own read operation, it is the period of waiting for the read operation to be suspended in response to the end of the update conflict of the memory module (PSRAM1) 21 (where an update conflict actually occurs). Therefore, time point t9 to time point t13 is defined here as the additional waiting period Taddwt (additional waiting duration) of the memory module (PSRAM2) 22 (where no update conflict occurs).

As can be seen from FIG8A, the memory module (PSRAM1) 21 transmits read data during the period from time point t13 to time point t15, and the memory module (PSRAM2) 22 transmits read data during the period from time point t13 to time point t15. Therefore, the period from time point t13 to time point t15 can be referred to as the synchronous data read period Tdat_sync, and the read data transmitted by the memory modules (PSRAM1) 21 and (PSRAM2) 22 are referred to as synchronous read data DATm1 and DATm2.

In some applications, the memory module (PSRAM2) 22 can be designed to suspend the transmission of read data from the internal buffer to the system input-output signal SIO[16:9] once it is known that the memory module (PSRAM1) 21 has an update conflict, and wait until after time point t13, the memory module (PSRAM2) 22 starts to transmit the read strobe pulse signals m2strb1, m2strb2 and the synchronous read data DATm2. That is, the data strobe mask signal DQSM[2] corresponding to the memory module (PSRAM2) 22 maintains a low level during the period from time point t2 to time point t13, and the system input-output signal SIO[16:9] corresponding to the memory module (PSRAM2) 22 is suspended from being output during the period from time point t8 to time point t13.

Please refer to FIG8B for a waveform diagram of an embodiment of synchronous reading operation between memory modules PSRAM1, PSRAM2 and the main control device using data flash mask signal DQSM with delayed reporting mode (mode B) according to the concept of the present invention. In this figure, time point t1 to time point t17 is the reading operation period Trd; time point t1 to time point t16 is the chip selection period Tcs; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the reading instruction transmission period Tcmd; time point t4 to time point t9 is the address transmission period Tadr; time point t9 to time point t15 is the synchronous data preparation period Tsdatpr; time point t15 to time point t17 is the synchronous data reading period Tdat_sync; time point t16 to time point t17 is the end period Tend.

After the master control device 23 pulls the chip select signal CS# to a low level at time t1, the memory modules (PSRAM1) 21 and (PSRAM2) 22 maintain the data strobe mask signals DQSM[1] and DQSM[2] at a low level at time t2. Then, during the period from time t3 to time t4, the master control device 23 issues read commands m1CMDrd and m2CMDrd to the memory modules (PSRAM1) 21 and (PSRAM2) 22 through the system input/output signal line SIO[16:1]. Then, during the period from time t4 to time t6, the master control device 23 transmits the column address m1ADRr corresponding to the memory module (PSRAM1) 21 using the system input/output signal SIO[8:1], and transmits the column address m2ADRr corresponding to the memory module (PSRAM2) 22 using the system input/output signal SIO[16:9]. During the period from time t6 to time t9, the main control device 23 uses the system input and output signal SIO[8:1] to transmit the row address m1ADRc corresponding to the memory module (PSRAM1) 21, and uses the system input and output signal SIO[16:9] to transmit the row address m2ADRc corresponding to the memory module (PSRAM2) 22.

As mentioned above, when the memory module (PSRAM1) 21 adopts the delayed reporting mode (mode B), it must wait until the memory module (PSRAM1) 21 receives the column address m1ADRr before notifying the main control device 23. Therefore, during the period between time point t7 and time point t8, the memory module (PSRAM1) 21 notifies the main control device 23 of the update conflict generated inside by pulling up the level of the data flash mask signal DQSM[1]. Among them, the period from time point t7 to time point t8 can be defined as the new conflict notification period Trfrp required for the memory module (PSRAM1) 21 that has an update conflict to notify the main control device 23 of the update conflict.

Next, during the period from time t9 to time t10 (extended read instruction period Tcmdext), the master control device 23 uses the data strobe mask signal DQSM[1] to transmit the extended read instruction m1CMDext to the memory module (PSRAM1) 21, and uses the data strobe mask signal DQSM[2] to transmit the extended read instruction m2CMDext to the memory module (PSRAM2) 22. Accordingly, at time t10, the memory module (PSRAM2) 22 has learned through the master control device 23 that the current read operation should not be performed at the speed of the general read operation, and needs to wait for the memory module (PSRAM1) 21 to complete the update conflict.

As mentioned above, the memory modules (PSRAM1) 21 and (PSRAM2) 22 start to calculate the read delay count LC after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG8B that the memory modules (PSRAM1) 21 and (PSRAM2) 22 both start to calculate the read delay count from time point t5. Among them, the memory module (PSRAM1) 21 needs two read delay counts (LC*2) to obtain the read data from the internal memory array to the internal buffer, while the memory module (PSRAM2) 22 only needs one read delay count (LC) to obtain the read data from the internal memory array to the internal buffer. Next, how and when the memory modules (PSRAM1) 21 and (PSRAM2) 22 transmit the synchronous read data DATm1 and DATm2 will be described respectively.

The memory module (PSRAM1) 21 ends its update conflict at time t14, and generates read strobe pulse signals m1strb1 and m1strb2 with the data strobe mask signal DQSM[1] at the next rising edge of the system clock signal SCLK (i.e., time t15). Therefore, the internal buffer of the memory module (PSRAM1) 21 starts to transmit the synchronous read data DATm1 using the system input and output signal SIO[16:9] from time t15. Here, time t5 to time t15 is defined as the update conflict read period Trdrf.

Since the memory module (PSRAM2) 22 can complete the reading at the end of a read delay count (i.e., time point t11), and successively generate the read strobe pulse signals m2strb1′ and m2strb2′ with the data strobe mask signal DQSM[2] at the next rising edge of the system clock signal SCLK (i.e., time point t12), the memory module (PSRAM2) 22 will transmit the read data from the internal buffer from time point t12 to time point t13.

After that, the memory module (PSRAM2) 22 will remain idle for a period of time (from time t13 to time t15), and then generate the read strobe pulse signals m2strb1 and m2strb2 again using the data strobe mask signal DQSM[2] from time t15. In addition, the memory module (PSRAM2) 22 will also transmit the synchronous read data DATm2 again using the system input/output signal SIO[16:9] from time t15.

Similar to FIG8A , the master control device 23 does not use the read data transmitted by the memory module (PSRAM2) 22 during the period from time t12 to time t13, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2) 22 during the period from time t15 to time t17. Therefore, the read data transmitted by the memory module (PSRAM2) 22 during the period from time t12 to time t13 can be referred to as discarded data drpDATm2, and the period during which the memory module (PSRAM2) 22 transmits the discarded data drpDATm2 can be defined as the data discard period Tdrp2. The discarded data drpDATm2 transmitted by the system input/output signal SIO[16:9] during the period from time t12 to time t13, and the synchronous read data DATm2 transmitted during the period from time t15 to time t17, are both provided by the internal buffer of the memory module (PSRAM2) 22, and the contents of the two are exactly the same.

The time point t11 to the time point t15 is equivalent to the additional waiting period required for the memory module (PSRAM2) 22 to wait for the update conflict of the memory module (PSRAM1) 21 to end. Since the period from the time point t11 to the time point t15 is not the period required for the memory module (PSRAM2) 22 (where no update conflict occurs) to perform its own read operation, but the period of waiting for the read operation to be suspended in response to the end of the update conflict of the memory module (PSRAM1) 21 (where an update conflict actually occurs). Therefore, the time point t11 to the time point t15 is defined here as the additional waiting period Taddwt of the memory module (PSRAM2) 22 (where no update conflict occurs).

As can be seen from FIG. 8B , the memory module (PSRAM1) 21 transmits the synchronous read data DATm1 during the period from time point t15 to time point t17, and the memory module (PSRAM2) 22 transmits the synchronous read data DATm2 during the period from time point t15 to time point t17. Therefore, the period from time point t15 to time point t17 is the synchronous data read period Tdat_sync. During the synchronous data read period Tdat_sync, the internal buffers of the memory modules (PSRAM1) 21 and (PSRAM2) 22 can synchronously transmit the read data to the main control device 23 through the system input and output signals SIO[8:1] and SIO[16:9].

Please also note that in actual applications, the method of FIG. 8B may also be combined with other changes. For example, because the memory module (PSRAM1) 21 itself has an update conflict, the master control device 23 only needs to notify the memory module (PSRAM2) 22 that has no update conflict. Therefore, in some applications, the master control device 23 may send an extended read instruction m2CMDext to the memory module (PSRAM2) 22, but not send an extended read instruction m1CMDext to the memory module (PSRAM1) 21.

In addition, in some applications, the memory module (PSRAM2) 22 may only use the system input and output signal SIO[16:9] to transmit the synchronous read data DATm2 without transmitting the discarded data drpDATm2. Therefore, the memory module PSRAM2 stops transmitting any data during the period from time t10 to time t15, and the data flash mask signal DQSM[2] is maintained at a low level during the period from time t2 to time t15. The changes in these applications are not described in detail here.

Please refer to FIG. 8A and FIG. 8B at the same time. Since the immediate reporting mode (mode A) described in FIG. 8A reports the update conflict to the master control device 23 earlier than the delayed reporting mode (mode B) described in FIG. 8B, the update conflict notification period Trfrp of FIG. 8A is shorter than the update conflict notification period Trfrp of FIG. 8B. In addition, the length of the additional waiting period Taddwt and the update conflict reading period Trdrf does not vary due to the different reporting modes adopted. Furthermore, in actual applications, different memory modules may also be equipped with different reporting modes.

In the embodiment shown in FIG8A and FIG8B, the existing data flash shield signal lines DQSM[1] and DQSM[2] are used as the medium for the memory modules PSRAM1 and PSRAM2 to report whether the update conflict occurs or not. In some applications, an additional signal line can be used as the medium for the memory modules PSRAM1 and PSRAM2 to report whether the update conflict occurs or not. FIG9A, FIG9B and FIG10 are examples of setting a bank read busy signal line (BRBB for short) between the memory modules (PSRAM1) 51 and (PSRAM2) 52 and the main control device 53, and using the bank read busy signal line BRBB as an example of the memory modules (PSRAM1) 51 and (PSRAM2) 52 reporting the update conflict to the main control device 53. Among them, FIG9A and FIG9B are examples of setting a bank read busy signal line BRBB between the main control device 53 and the memory modules (PSRAM1) 51 and (PSRAM2) 52, and changing the driving end of the wiring according to the different states of the read operation.

In FIG. 9A and FIG. 9B , the electronic device 50 includes a main control device 53 and memory modules 51 and 52. The main control device 53 is electrically connected to the memory modules (PSRAM1) 51 and (PSRAM2) 52 through CS# and the system clock signal SCLK. In addition, the main control device 53 is electrically connected to the memory module 51 through the system input/output signal SIO[8:1] and the data strobe mask signal DQSM[1], and is electrically connected to the memory module (PSRAM2) 52 through the system input/output signal SIO[16:9] and the data strobe mask signal DQSM[2]. Furthermore, the bank busy signal line BRBBh of the main control device 53, the bank busy signal line BRBBm1 of the memory module (PSRAM1) 51, and the bank busy signal line BRBBm2 of the memory module (PSRAM2) 52 are electrically connected together. According to an embodiment of the present invention, the bank busy signal lines BRBBh, BRBBm1, and BRBBm2 can be connected to each other using common wiring. Alternatively, the bank busy signal lines BRBBh, BRBBm1, BRBBm2 can be used in conjunction with bidirectional interface circuits 501, 511, 521 and pull-up resistors 50a as shown in FIG9A and FIG9B. The pull-up resistor 50a is electrically connected between the supply voltage Vcc and the bank busy signal line BRBBh. In FIG9A and FIG9B, the signal driving directions on the bank busy signal lines BRBBh, BRBBm1, BRBBm2 are indicated by dotted lines.

When the bank busy signal lines BRBBh, BRBBm1, BRBBm2 are used in conjunction with the bidirectional interface circuits 501, 511, 521 and the pull-up resistor 50a, the memory module (e.g., memory module (PSRAM1) 51) that has an update conflict can achieve the effect of simultaneously notifying the master control device 53 and other memory modules (e.g., memory module (PSRAM2) 52) that have not had an update conflict based on the wired OR connection method. In FIG9A and FIG9B, the bidirectional interface circuit 501 of the master control device 53 includes an output inverter 501a and an input inverter 501b that are connected in opposite ways; the bidirectional interface circuit 511 of the memory module (PSRAM1) 51 includes an output inverter 511a and an input inverter 511b that are connected in opposite ways; and the bidirectional interface circuit 521 of the memory module (PSRAM2) 52 includes an output inverter 521a and an input inverter 521b that are connected in opposite ways.

Please refer to FIG9A for a schematic diagram of setting a bank busy signal line BRBB between the memory module and the master control device and driven by the master control device. When the bank busy signal line uses the master control device 53 as the driving end, the driving signal sent by the master control device 53 is first transmitted to the bank busy signal line BRBBh by the output inverter 501a in the bidirectional interface circuit 501, and then transmitted to the memory module (PSRAM1) 51 via the bank busy signal line BRBBm1 and the input inverter 511b of the bidirectional interface circuit 511, and transmitted to the memory module (PSRAM2) 52 via the bank busy signal line BRBBm2 and the input inverter 521b of the bidirectional interface circuit 521.

Please refer to FIG. 9B for a schematic diagram of a memory bank busy signal line BRBB set between the memory module and the main control device and driven by the memory module. When the memory bank busy signal line uses the memory module (PSRAM1) 51 as the driving end, the memory module (PSRAM1) 51 first transmits the driving signal to the memory bank busy signal line BRBBm1 through the output inverter 511a in the bidirectional interface circuit 511, and then transmits it to the main control device 53 through the memory bank busy signal line BRBBh and the input inverter 501b of the bidirectional interface circuit 501, and transmits it to the memory module (PSRAM2) 52 through the memory bank busy signal line BRBBm2 and the input inverter 521b of the bidirectional interface circuit 521.

In the default state, if the master control device 53 and the memory modules (PSRAM1) 51 and (PSRAM2) 52 do not generate a driving signal, the pull-up resistor 50a is used to maintain the memory bank busy signals BRBBh, BRBBm1 and BRBBm2 at a high level. In the present invention, it is assumed that the driving capability of the memory modules (PSRAM1) 51 and (PSRAM2) 52 for the memory bank busy signals BRBBm1 and BRBBm2 is greater than the driving capability of the master control device 53 for the memory bank busy signal BRBBh. Moreover, the driving capability of the memory bank busy signal BRBBh issued by the master control device 53 is greater than the driving capability of the pull-up resistor 50a.

Next, the connection diagrams shown in FIG. 9A and FIG. 9B are used together with FIG. 10 to illustrate an example in which the memory module uses the bank busy signals BRBB (PSRAM1) 51 and (PSRAM2) 52 to report to the master control device 53 whether an update conflict occurs.

Please refer to FIG. 10 for a waveform diagram of an embodiment of a synchronous read operation between a memory module and a main control device using a bank busy signal line BRBB in combination with an immediate reporting mode (mode A) according to the concept of the present invention. In this figure, time point t1 to time point t15 is a read operation period Trd; time point t1 to time point t14 is a chip selection period Tcs; time point t1 to time point t3 is a setting period Tset; time point t3 to time point t4 is a read instruction transmission period Tcmd; time point t4 to time point t8 is an address transmission period Tadr; time point t8 to time point t13 is a synchronous data preparation period Tsdatpr; time point t13 to time point t15 is a synchronous data reading period Tdat_sync; time point t14 to time point t15 is an end period Tend.

After the master control device 53 pulls the chip selection signal CS# to a low level at time t1, the memory module (PSRAM1) 51 notifies the master control device 53 that an update conflict has occurred in the memory module 51 by pulling down the level of the memory bank busy signal BRBBm1 at time t2. The memory module (PSRAM1) 51 maintains the memory bank busy signal BRBBm1 at a low level from time t2 to time t7, and starts to pull up the memory bank busy signal BRBBm1 to a high level at time t7. The period from time t2 to time t7 can be defined as the update conflict notification period Trfrp.

On the other hand, during the period from time t1 to time t7, the memory module PSRAM2 maintains the bank busy signal BRBBm2 at a high level. At this time, the signal driving conditions between the bank busy signal lines BRBBh, BRBBm1, and BRBBm2 will be as shown in FIG. 9B. That is, the bank busy signal BRBBm1 issued by the memory module (PSRAM1) 51 will drive the bank busy signal BRBBh of the master device and the bank busy signal BRBBm2 corresponding to the memory module (PSRAM2) 22.

Although in FIG10 , the bank busy signal BRBBm2 issued by the memory module (PSRAM2) 52 is at a high level, the bank busy signal line BRBBm2 of the memory module PSRAM2 also starts to decrease in level at time t2 because the memory module (PSSRAM1) 51 is actively driven from time t2. In addition, the memory module (PSRAM2) 52 can immediately know that the other memory module (i.e., the memory module (PSRAM1) 51) has an update conflict through the phenomenon of the decrease in the level of the bank busy signal BRBBm2.

In Fig. 10, the effect of notifying the memory module PSRAM2 is achieved by the hardware wiring shown in Fig. 9A and Fig. 9B. Therefore, in Fig. 10, the main control device 53 does not need to use the method shown in Fig. 8A and Fig. 8B to notify the memory module PSRAM2 by means of instructions.

In some applications, the bank busy signal lines BRBBh, BRBBm1, BRBBm2 may be used without the bidirectional interface circuit and the pull-up circuit. For these applications, the master control device 53 may notify the memory module (PSRAM2) 52 as shown in FIG. 8A and FIG. 8B.

As mentioned above, the memory modules (PSRAM1) 51 and (PSRAM2) 52 start counting the read delay count after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG. 10 that the memory modules (PSRAM1) 51 and (PSRAM2) 52 both start counting the read delay count from time point t5. Among them, the memory module (PSRAM1) 51 needs two read delay counts (LC*2) to prepare the read data in the internal buffer, while the memory module PSRAM2 only needs one read delay count (LC) to prepare the read data in the internal buffer. Next, how and when the memory modules PSRAM1 and PSRAM2 transmit the synchronous read data DATm1 and DATm2 are described respectively.

The update conflict of the memory module (PSRAM1) 51 ends at time t12, and at the next rising edge of the system clock signal SCLK (i.e., time t13), the read strobe pulse signals m1strb1 and m1strb2 are generated successively by the data strobe mask signal DQSM[1]. Therefore, the memory module (PSRAM1) 51 starts to transmit the synchronous read data DATm1 by using the system input/output signal SIO[8:1] from time t13.

Since the memory module (PSRAM2) 52 can complete the reading at the end of a read delay count (i.e., time point t9), and generate the read strobe pulse signals m2strb1′ and m2strb2′ successively with the data strobe mask signal DQSM[2] at the next rising edge of the system clock signal SCLK (i.e., time point t10), the memory module (PSRAM2) 52 starts to transmit the discard data drpDATm2 using the system input/output signal SIO[16:9] from time point t10. The period during which the memory module (PSRAM2) 52 transmits the discard data drpDATm2 is defined as the data discard period Tdrp2.

After that, the memory module (PSRAM2) 52 will remain idle for a period of time (from time t11 to time t13), and then generate the read strobe pulse signals m2strb1 and m2strb2 again with the data strobe mask signal DQSM[2] from time t13. The time from t9 to time t13 can be defined as the additional waiting period Taddwt that the memory module (PSRAM2) 22 needs to spend to wait for the update conflict of the memory module (PSRAM1) 51 to end. The memory module (PSRAM2) 52 will also transmit the synchronous read data DATm2 again from time t13.

According to the concept of the present invention, the master control device 53 does not use the discarded data drpDATm2 transmitted by the memory module (PSRAM2) 52 during the period from time t9 to time t10, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2) 52 during the period from time t13 to time t15. The discarded data drpDATm2 transmitted via the system input/output signal SIO[16:9] and the synchronous read data DATm2 are both provided by the memory module (PSRAM2) 22, and the contents of the two are exactly the same.

Here, the time point t5 to the time point t13 is defined as the update conflict reading period Trdrf required for waiting for the memory module (PSRAM1) 51 to copy the read data to the internal buffer in response to the update conflict occurring in the memory module (PSRAM1) 51. As can be seen from FIG. 10, the memory module (PSRAM1) 51 transmits the synchronous read data DATm1 during the period from the time point t13 to the time point t15, and the memory module (PSRAM2) 52 transmits the synchronous read data DATm2 during the period from the time point t13 to the time point t15 (synchronous data reading period Tdat_sync). Therefore, the memory modules (PSRAM1) 51 and (PSRAM2) 52 can synchronously transmit the read data to the master device 53.

FIG10 shows a waveform diagram of the memory module (PSRAM1) 51, (PSRAM2) 52 and the main control device 53, using the memory bank busy signal lines BRBBh, BRBBm1, BRBBm2 with the immediate reporting mode (mode A). In actual application, the delayed reporting mode (mode B) can also be used. The method of using the delayed reporting mode (mode B) can be inferred from the description of FIG8B and FIG10, so it will not be described in detail.

Furthermore, the present invention can also use existing signal lines (e.g., chip select signal CS#, system clock signal SCLK, data strobe mask signal DQSM, etc.) between the main control device and the memory modules PSRAM1 and PSRAM2, as well as additional signal lines, to generate specific waveform changes to report the status of the memory modules (PSRAM1) 51 and (PSRAM2) 52. For example, in FIG11 , it is assumed that the data strobe mask signal DQSM[1] is used in combination with the changes of the memory bank busy signals BRBBm1 and BRBBh.

Please refer to FIG. 11 for another embodiment of the synchronous reading operation between the memory module PSRAM1 and the main control device in the immediate reporting mode (mode A) according to the concept of the present invention. In this figure, the time point t1 to the time point t13 is the reading operation period Trd; the time point t1 to the time point t12 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the reading instruction transmission period Tcmd; the time point t4 to the time point t8 is the address transmission period Tadr; the time point t8 to the time point t11 is the synchronous data preparation period Tsdatpr; the time point t11 to the time point t13 is the synchronous data reading period Tdat_sync; the time point t12 to the time point t13 is the end period Tend.

After the master control device 53 pulls the chip select signal CS# low at time t1, the memory module (PSRAM1) 51 simultaneously pulls the level of the memory bank busy signal BRBBm1 low and pulls the level of the data strobe mask signal DQSM[1] high at time t2 to notify the master control device 53 that an update conflict has occurred. The memory module (PSRAM1) 51 maintains the memory bank busy signal BRBBm1 at a low level and maintains the data strobe mask signal DQSM[1] at a high level during the period from time t2 to time t7 (update conflict notification period Trfrp).

Since the memory module (PSRAM1) 51 maintains the bank busy signal BRBBm1 at a low level during the update conflict notification period Trfrp, the bank busy signal BRBBh will be affected by the bank busy signal BRBBm1 from the memory module (PSRAM1) 51 as shown in FIG. 9B and Trfrp will be maintained at a low level during the update conflict notification period. The memory module (PSRAM1) 51 stops pulling the bank busy signal BRBBm1 high at time t7 and starts pulling the data flash mask signal DQSM[1] down to a low level.

On the other hand, during the period from time t1 to time t7, the memory module (PSRAM2) 52 maintains the bank busy signal BRBBm2 at a high level and maintains the data flash mask signal DQSM[2] at a low level. Although the memory module (PSRAM2) 52 maintains the bank busy signal BRBBm2 at a high level during the period from time t2 to time t7, because the bank busy signals BRBBh, BRBBm1, and BRBBm2 are connected in a wired OR manner, the change of the bank busy signal BRBBm1 being pulled down to a low level by the memory module (PSRAM1) 51 during the period from time t2 to time t7 will still be reflected in the bank busy signal BRBBm2, causing the level of the bank busy signal BRBBm2 to fluctuate. Therefore, the memory module (PSRAM2) 52 can learn that the memory module (PSRAM1) 51 has an update conflict through the signal fluctuation of the bank busy signal BRBBm2.

Accordingly, the master control device 53 can know that the memory module (PSRAM1) 51 has an update conflict according to the bank busy signal BRBBh. In addition, the memory module (PSRAM2) 52 can also directly grasp the situation that the memory module (PSRAM1) 51 has an update conflict through the wired OR connection method as shown in Figure 9B. In other words, when the wired OR connection method is adopted, the memory module (PSRAM2) 52 can directly know that the memory module (PSRAM1) 51 has an update conflict through the bank busy signal BRBBm2, without indirectly knowing it through the master control device 53.

As mentioned above, the memory modules (PSRAM1) 51 and (PSRAM2) 52 start to count the read delay count after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG. 11 that the memory modules (PSRAM1) 51 and (PSRAM2) 52 both start to count the read delay count from time point t5. Among them, the memory module (PSRAM1) 51 needs to spend two read delay counts (LC*2) to obtain the read data from the internal memory array to the internal buffer, while the memory module (PSRAM2) 52 only needs one read delay count (LC) to obtain the read data from the internal memory array to the internal buffer. Next, how and when the memory modules (PSRAM1) 51 and (PSRAM2) 52 transmit the synchronous read data DATm1 and DATm2 will be described respectively.

The memory module (PSRAM1) 51 starts at time t5, and after the update read delay rfcLC (for example, rfcLC=LC*2), its update conflict ends at time t10. The memory module (PSRAM1) 51 generates read strobe pulse signals m1strb1 and m1strb2 with the data strobe mask signal DQSM[1] at the next rising edge of the system clock signal SCLK after time t10 (i.e., time t11). Therefore, the memory module (PSRAM1) 51 starts to transmit the synchronous read data DATm1 from time t11.

On the other hand, the memory module (PSRAM2) 52 can prepare the read data in the internal buffer at time t9 after the preset read delay (dftLC=LC*1) from time t5. Because the memory module (PSRAM1) 51 has an update conflict, the memory module (PSRAM2) 52 knows that after the preset read delay (dftLC=LC*1) ends, it cannot immediately transmit the read data at the next rising edge of the system clock signal SCLK after the preset read delay (dftLC=LC*1) ends (time t9). The time from t9 to t11 can be defined as the additional waiting period Taddwt that the memory module (PSRAM2) 22 needs to spend to wait for the update conflict of the memory module (PSRAM1) 51 to end.

Here, the time point t5 to the time point t11 is defined as the update conflict read period Trdrf required for waiting for the memory module (PSRAM1) 51 to copy the read data to the internal buffer in response to the update conflict occurring in the memory module (PSRAM1) 51. As can be seen from FIG. 11, the memory module (PSRAM1) 51 transmits the synchronous read data DATm1 during the period from the time point t11 to the time point t13, and the memory module (PSRAM2) 52 transmits the synchronous read data DATm2 during the period from the time point t11 to the time point t13. The period from the time point t11 to the time point t13 can be defined as the synchronous data read period Tdat_sync. Therefore, the memory modules (PSRAM1) 51 and (PSRAM2) 52 can synchronously transmit the read data in the internal buffer to the master device 53 using the system input and output signal SIO[16:1].

In addition to the example shown in FIG. 9A and FIG. 9B , the additionally provided memory bank busy signal BRBB is used in conjunction with the bidirectional interface circuit and the pull-up resistor 50a. The present invention can also use the chip select signal CS# in conjunction with the bidirectional interface circuit and the pull-up resistor 40a, as shown in FIG. 12A and FIG. 12B .

In FIG. 12A and FIG. 12B , the electronic device 40 includes a main control device 43 and memory modules (PSRAM1) 41 and (PSRAM2) 42. The main control device 43 is electrically connected to the memory modules (PSRAM1) 41 and (PSRAM2) 42 via the chip select signal CS# and the system clock signal SCLK. In addition, the main control device 43 is electrically connected to the memory module (PSRAM1) 41 via the system input/output signal SIO[8:1] and the data strobe mask signal DQSM[1], and is electrically connected to the memory module (PSRAM2) 42 via the system input/output signal SIO[16:9] and the data strobe mask signal DQSM[2]. It is assumed here that the chip select signal CS# is used in conjunction with the bidirectional interface circuits 401, 411, 421 and the pull-up resistor 40a.

When the chip select signal CS# is used in conjunction with the bidirectional interface circuits 401, 411, 421 and the pull-up resistor 40a, the memory module (e.g., memory module (PSRAM1) 41) that has an update conflict can achieve the effect of simultaneously notifying the master device 43 and other memory modules (e.g., memory module (PSRAM2) 42) that have not had an update conflict based on the wired OR connection method. In FIG. 12A and FIG. 12B, the bidirectional interface circuit 401 of the master device 43 includes an output inverter 401a and an input inverter 401b that are connected in opposite ways; the bidirectional interface circuit 411 of the memory module (PSRAM1) 41 includes an output inverter 411a and an input inverter 411b that are connected in opposite ways; and the bidirectional interface circuit 421 of the memory module (PSRAM2) 42 includes an output inverter 421a and an input inverter 421b that are connected in opposite ways.

Please refer to Figures 12A and 12B, which are schematic diagrams showing that the chip select signal CS# is used as the communication interface for updating conflicts between the memory module and the main control device, and the chip select signal CS# is driven by the main control device 43 and the memory module (PSRAM1) 41, respectively. The driving method of the chip select signal CS# in Figures 12A and 12B can be similar to the signal driving method of the bank busy signal BRBB in Figures 9A and 9B, so it will not be described in detail.

When the chip select signal CS# is connected in a wired OR manner as shown in FIG. 12A and FIG. 12B, the memory modules (PSRAM1) 41 and (PSRAM2) 42 may also affect the level of the chip select signal CS#. Therefore, in some applications, the chip select signal CS# can be used as a communication for performing a synchronous read operation. For example, FIG. 13 shows an embodiment in which the memory module (PSRAM1) 41 performs a synchronous read operation according to an immediate reporting mode (mode A) through the chip select signal CS#.

Please refer to FIG. 13, which is a waveform diagram of an embodiment in which the memory module and the main control device use the chip selection signal CS# as the communication interface for update conflict, and the memory module notifies the main control device according to the immediate reporting mode (mode A) and then performs a synchronous read operation. In this figure, time point t1 to time point t13 is the read operation period Trd; time point t1 to time point t4 is the chip selection period Tcs; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the read instruction transmission period Tcmd; time point t4 to time point t7 is the address transmission period Tadr; time point t7 to time point t12 is the synchronous data preparation period Tsdatpr; time point t12 to time point t13 is the synchronous data reading period Tdat_sync. Here, time point t5 to time point t12 is the update conflict reading period Trdrf. The time point t8 to the time point t12 can be defined as the additional waiting period Taddwt that the memory module (PSRAM2) 42 needs to spend to wait for the update conflict of the memory module (PSRAM1) 41 to end. The time point t5 to the time point t12 here is the update conflict read period Trdrf.

Please also note that in this embodiment, if any memory module (e.g., memory module PSRAM1) has an update conflict, the memory module having the update conflict will pull the chip select signal CS# high to force the read operation to end. Therefore, the read operation period Trd shown in FIG13 does not include the end period Tend, and the length of the chip select period Tcs is much shorter than the chip select period Tcs of other embodiments. In FIG13, because the chip select signal CS# is used for notification, the update conflict notification period Trfrp is almost the same length as the chip select period Tcs.

In this embodiment, the memory module (PSRAM1) 41 senses the moment when the main control device 43 pulls the chip selection signal CS# low at time point t1, and thus knows that there is an update conflict inside it. Therefore, at time point t4, the memory module (PSRAM1) 41 pulls the chip selection signal CS# high, and in this way notifies the main control device 43 that there is an update conflict inside it. That is, before time point t4, the main control device 43, as shown in FIG. 12A, acts as the driver of the chip selection signal CS#. During the period from time point t4 to time point t13, the memory module (PSRAM2) 42, as shown in FIG. 12B, acts as the driver of the chip selection signal CS#.

Since the main control device 43, the memory module (PSRAM1) 41, and (PSRAM2) 42 are all connected to the chip select signal CS#, the memory module (PSRAM2) 42 can also know at time point t4 that an update conflict occurs inside the memory module (PSRAM1) 41. Therefore, the memory module (PSRAM2) 42 can know that it is impossible to immediately transmit the read data in the internal buffer to the main control device 43 at the next rising edge (time point t9) of the system clock signal SCLK after the preset read delay (dftLC=LC*1) ends (time point t8).

As shown in FIG. 13 , the memory module (PSRAM2) 42 immediately transmits the read data to the master device 43 during the data discard period Tdrp2 at the next rising edge of the system clock signal SCLK (time point t9) after the preset read delay (dftLC=LC*1). However, the read data transmitted during the data discard period Tdrp2 will be discarded by the master device 43, and is therefore called discarded data drpDATm2. Therefore, the memory module (PSRAM2) 42 still needs to start at time point t12, and use the data strobe mask signal DQSM[2] to issue the read strobe pulse signals m2strb1 and m2strb2 again, and use the system input and output signal SIO[16:9] to transmit the synchronous read data DATm2 again. The discarded data drpDATm2 and the synchronous read data DATm2 transmitted via the data strobe mask signal DQSM[2] are both provided by the memory module (PSRAM2) 42, and the contents of the two are exactly the same.

FIG13 shows a waveform diagram of the chip selection signal CS# used between the memory module (PSRAM1) 41 and the host device in an immediate reporting mode (mode A). In actual application, the memory module (PSRAM1) 41 and the host device 43 may also be used in a delayed reporting mode (mode B). The method of using the delayed reporting mode (mode B) can be analogized to the description of FIG8B and FIG13 and will not be described in detail.

Please refer to FIG. 14, which is a waveform diagram of an embodiment of synchronous read operation between the memory module and the main control device using the chip select signal CS# and the system clock signal SCLK according to the immediate reporting mode (mode A). In this figure, the time point t1 to the time point t12 is the read operation period Trd; the time point t1 to the time point t12 is the chip select period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; the time point t4 to the time point t8 is the address transmission period Tadr; the time point t8 to the time point t13 is the synchronous data preparation period Tsdatpr; the time point t13 to the time point t15 is the synchronous data reading period Tdat_sync; the time point t14 to the time point t15 is the end period Tend. Here, the time point t5 to the time point t13 is the update conflict reading period Trdrf. The time point t5 to the time point t11 is the preset read delay (dftLC=LC*1) required for the memory module (PSRAM2) 42 to perform the read operation. The time point t11 to the time point t13 can be defined as the additional waiting period Taddwt that the memory module (PSRAM2) 42 needs to spend to wait for the update conflict of the memory module (PSRAM1) 41 to end.

In this embodiment, it is assumed that the memory device (PSRAM1) 41, during a complete cycle of the system frequency signal SCLK, reaches the effect of notifying the master control device 43 and the memory module (PSRAM2) 42 about the update conflict by pulling up the level of the chip selection signal CS#. In FIG14 , it is assumed that the master control device 43 pulls up the level of the chip selection signal CS# during the period from time point t9 to time point t10 (equivalent to the period of the entire cycle of the system frequency cycle Tclk4). Therefore, the period from time point t9 to time point t10 can be defined as the pause reading notification period Tstp used by the master control device 43 to notify the memory module (PSRAM2) 42 that the read operation needs to be suspended. In this figure, it is assumed that the update conflict notification period Trfrp is equivalent to the system frequency cycle Tclk4 of the system frequency signal SCLK.

In actual application, the method of the master control device 43 using the chip select signal CS# and the system frequency signal SCLK to know the memory module (PSRAM2) 42 does not need to be limited. For example, the master control device 43 can choose to pull the chip select signal CS# high at any one of the system frequency cycles Tclk1 to Tclk8. Since the preset read delay (dftLC=LC*1) required for the memory module PSRAM2 to perform a read operation ends at time point t11, if the position where the master control device 43 pulls the chip select signal CS# high is earlier than time point t11, the memory module (PSRAM2) 42 can know in real time that it should temporarily stop transmitting the read data from the internal buffer after the preset read delay ends. If the master control device 43 pulls the chip select signal CS# high before time point t11, the memory module PSRAM2 will suspend transmitting the data in the internal buffer after the end of time point t11. After the synchronous data preparation period Tsdatpr ends, the memory module (PSRAM2) 42 starts to transmit the synchronous read data DATm2 from the internal buffer.

On the other hand, if the master control device 43 pulls the chip select signal CS# high later than the time point t11, for example, the master control device 43 pulls the chip select signal CS# high in the system frequency cycles Tclk6, Tclk7, and Tclk8, then the memory module (PSRAM2) 42 needs to transmit the read data from the internal buffer to the system input/output signal SIO[16:9] twice.

FIG14 shows a waveform diagram of the memory module (PSRAM1) 41 notifying the host device 43 using the immediate reporting mode (mode A), and the host device 43 notifying the memory module (PSRAM2) 42 using the combination of the chip selection signal CS# and the system clock signal SCLK. In actual application, the delayed reporting mode (mode B) can also be used in combination with the chip selection signal CS# and the system clock signal SCLK. The method of using the delayed reporting mode (mode B) can be inferred from the description of FIG8B and will not be described in detail.

According to the concept of the present invention, the method by which the memory module PSRAM2 learns that it needs to wait for the synchronization data preparation period Tsdatpr is quite flexible. For example, in actual application, frequency ignore signal lines ICK1 and ICK2 can be additionally set between the master control device and the memory modules PSRAM1 and PSRAM2. The frequency ignore signal lines ICK1 and ICK2 are at a low level most of the time, but when the master control device pulls the frequency ignore signal ICK1 and ICK2 high, the memory modules PSRAM1 and PSRAM2 will temporarily skip the change of the system frequency signal SCLK during the period when the frequency ignore signal ICK1 and ICK2 are pulled high.

Please refer to FIG. 15 for a waveform diagram of an embodiment of setting frequency ignore signal lines ICK1 and ICK2 between the main control device and the memory modules PSRAM1 and PSRAM2, and performing synchronous read operation when an update conflict occurs in the memory module PSRAM1. In this figure, time point t1 to time point t14 is the read operation period Trd; time point t1 to time point t13 is the chip selection period Tcs; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the read instruction transmission period Tcmd; time point t4 to time point t8 is the address transmission period Tadr; time point t8 to time point t12 is the synchronous data preparation period Tsdatpr; time point t12 to time point t14 is the synchronous data reading period Tdat_sync; time point t12 to time point t13 is the end period Tend. Here, the period from time point t2 to time point t7 can be defined as the update conflict notification period Trfrp during which the memory module PSRAM1 that has an update conflict notifies the main control device. The time point t5 to the time point t11 can be defined as the update conflict read period Trdrf. The time point t5 to the time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the memory module PSRAM2 to perform the read operation. The time point t9 to the time point t11 can be defined as the additional waiting period Taddwt required for the memory module PSRAM2 to wait for the update conflict of the memory module PSRAM1 to end.

In FIG. 15 , the master control device temporarily raises the level of the frequency ignore signal ICK2 during the period from time point t10 to time point t11. Here, the period from time point t10 to time point t11 can be defined as the frequency ignore period Tick. During the frequency ignore period Tick, the memory module PSRAM2 will suspend receiving the system frequency signal SCLK. Therefore, the memory module PSRAM2 suspends operation during the frequency ignore period Tick. After the frequency ignore period Tick ends (time point t11), the master control device pulls the frequency ignore signal ICK2 down to a low level again, and the memory module PSRAM2 will receive the frequency of the system frequency signal SCLK again and continue the read operation. Therefore, at time point t12, the memory modules PSRAM and PSRAM2 begin to synchronously transmit the read data.

In the example of FIG15 , the master control device generates a frequency ignore signal ICK2 to the memory module PSRAM2, thereby notifying the memory module PSRAM2 to suspend receiving the system frequency signal SCLK. In the embodiment of FIG16 , it is assumed that the master control device actually stops transmitting the system frequency signal SCLK to the memory module PSRAM2. Compared with FIG15 , the method of FIG16 does not require additional wiring, and its cost is relatively low.

Please refer to FIG. 16 for a schematic diagram showing that after the main control device learns that the memory module PSRAM1 has an update conflict, it postpones its read operation by suspending the provision of the system frequency signal SCLK to the memory modules PSRAM1 and PSRAM2, thereby allowing the memory modules PSRAM1 and PSRAM2 to perform a synchronous read operation. In this figure, time point t1 to time point t13 is the read operation period Trd; time point t1 to time point t12 is the chip selection period Tcs; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the read instruction transmission period Tcmd; time point t4 to time point t8 is the address transmission period Tadr; time point t8 to time point t11 is the synchronous data preparation period Tsdatpr; time point t11 to time point t13 is the synchronous data reading period Tdat_sync; time point t12 to time point t13 is the end period Tend. Here, the period from time point t2 to time point t7 can be defined as the update conflict notification period Trfrp during which the memory module PSRAM1 that has an update conflict notifies the master device. The period from time point t5 to time point t11 can be defined as the update conflict read period Trdrf. The period from time point t5 to time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the memory module PSRAM2 to perform a read operation. The period from time point t9 to time point t11 can be defined as the additional waiting period Taddwt required for the memory module PSRAM2 to wait for the update conflict of the memory module PSRAM1 to end.

In FIG. 16 , the master control device stops transmitting the system frequency signal SCLK to the memory modules PSRAM1 and PSRAM2 during the period from time point t9 to time point t11. During this period, because of the internal update conflict of the memory module PSRAM1, even if the memory module PSRAM1 does not receive the system frequency signal SCLK, it will not affect its operation. On the other hand, during the period from time point t9 to time point t11, the memory module PSRAM2 stops operating because it does not receive the frequency of the system frequency signal SCLK. Starting from time point t11, the master control device restarts transmitting the system frequency signal SCLK to the memory modules PSRAM1 and PSRAM2, and the memory module PSRAM2 will restart operation. Therefore, at time point t11, the memory modules PSRAM and PSRAM2 start synchronously transmitting the synchronous read data DATm1 and DATm2.

In the above embodiment, it is assumed that the main control device learns that an update conflict occurs inside the memory module PSRAM1 through the report of the memory module PSRAM1. In actual application, the main control device can also actively grasp the update conflict occurs inside the memory module PSRAM1 through other methods.

The aforementioned embodiments all use one chip selection period Tcs to complete the synchronous read operation. In these embodiments, the synchronous data preparation period Tsdatpr is greater than the default read delay (dftLC=LC*1), and the synchronous data preparation period (Tsdatpr) is less than the update read delay (rfcLC=2*LC). In actual applications, the memory modules PSRAM1 and PSRAM2 can also use two (or more) chip selection periods Tcs to complete the synchronous read operation.

Please refer to FIG. 17, which is a schematic diagram of the master control device sending repeated read commands m1CMDrtry and m2CMDrtry to synchronize the read operation of the memory modules PSRAM1 and PSRAM2. In this figure, time point t1 to time point t21 is the read operation period Trd; time point t1 to time point t12 is the chip selection period Tcs1; time point t12 to time point t14 is the chip selection interval Tint; time point t14 to time point t19 is the chip selection period Tcs2; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the read command transmission period Tcmd; time point t4 to time point t6 is the address transmission period Tadr; time point t6 to time point t18 is the synchronous data preparation period Tsdatpr; time point t19 to time point t21 is the synchronous data reading period Tdat_sync; time point t20 to time point t21 is the end period Tend.

In this embodiment, the read operation period Trd includes a chip selection period Tcs1, a chip selection interval Tint, a chip selection period Tcs2, and an end period Tend in sequence. The chip selection signal CS# is at a low level during the chip selection periods Tcs1 and Tcs2, and the chip selection signal CS# is at a high level during the chip selection interval Tint and the end period Tend.

During the chip selection period Tcs1, the master control device successively receives the read data transmitted by the memory module PSRAM2 during the data discard period Tdrp2, and the read data transmitted by the memory module PSRAM1 during the data discard period Tdrp1. If the master control device finds that the time when the data is transmitted from the internal buffer of the memory modules PSRAM1 and PSRAM2 to the system input and output signals SIO[8:1] and SIO[16:9] is inconsistent during the chip selection period Tcs1, it means that the master control device cannot use the data correctly. Therefore, the read data can be regarded as discarded data drpDATm1 and drpDATm2. The time point t5 to the time point t11 here is the update conflict read period Trdrf.

As described above, during the chip selection period Tcs1, the read data transmitted from the memory modules PSRAM1 and PSRAM2 to the master device, including the read data transmitted from the memory module PSRAM1 during the period from time t11 to time t13, and the read data transmitted from the memory module PSRAM2 during the period from time t8 to time t9, will be ignored. During the chip selection period Tcs1, the read data transmitted from the memory modules PSRAM1 and PSRAM2 to the master device are regarded as discarded data drpDATm1 and drpDATm2.

The middle of the chip selection periods Tcs1 and Tcs2 is the chip selection interval Tint. At the chip selection interval Tint, the master control device pulls the chip selection signal CS# to a high level and maintains the system clock signal SCLK at a low level. In the chip selection period Tcs2, during the period from time point t14 to time point t15 (the repeated read instruction period Tcmd_rtry), the master control device issues repeated read instructions m1CMDrtry and m2CMDrtry to the memory modules PSRAM1 and PSRAM2. The repeated read instructions m1CMDrtry and m2CMDrtry represent that the memory modules PSRAM1 and PSRAM2 wait again for the update read delay rfcLC (for example, rfcLC=LC*2) before performing a read operation. The time point t14 to the time point t19 here is the period during which the memory modules PSRAM1 and PSRAM2 perform a read operation for the second time, so it is defined as the repeated read period T2rd.

Since the memory modules PSRAM1 and PSRAM2 have already received the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc during the address transmission period Tadr (the period from time point t4 to time point t6) of the chip selection period Tcs1, the master control device does not need to transmit the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc to the memory modules PSRAM1 and PSRAM2 again during the chip selection period Tcs2.

When the memory modules PSRAM1 and PSRAM2 receive the repeated read commands m1CMDrtry and m2CMDrtry, they wait together for the update of the read delay rfcLC (for example, rfcLC=LC*2). After the time point t18, the synchronous generation of the read strobe pulse signals m1strb1 and m2strb1 begins. During the period from the time point t18 to the time point t20, the memory module PSRAM1 transmits the read strobe pulse signals m1strb1 and m1strb2 to the master device using the data strobe mask signal DQSM[1], and transmits the synchronous read data DATm1 from the internal buffer to the master device using the system input-output signal SIO[8:1]. At the same time, the memory module PSRAM2 transmits the read strobe pulse signals m2strb1 and m2strb2 to the master device using the data strobe mask signal DQSM[2], and transmits the synchronous read data DATm2 from the internal buffer to the master device using the system input-output signal SIO[16:9].

In FIG17 , the discarded data drpDATm1 and the synchronous read data DATm1 transmitted via the system input/output signal SIO[8:1] are both transmitted from the internal buffer of the memory module PSRAM1, so the contents of the two are exactly the same. Similarly, the discarded data drpDATm2 and the synchronous read data DATm2 transmitted via the system input/output signal SIO[16:9] are both transmitted from the internal buffer of the memory module PSRAM2, so the contents of the two are exactly the same.

In the embodiment of FIG. 17 , the synchronous data preparation period Tsdatpr also covers a part of the chip selection periods Tcs1 and Tcs2. Therefore, the synchronous data preparation period Tsdatpr is longer than the update read delay rfcLC (Tsdatpr＞rfcLC＝2*LC). In addition, in the embodiment of FIG. 18 , the synchronous data preparation period Tsdatpr is slightly shorter than the update read delay rfcLC (Tsdatpr＜rfcLC＝2*LC).

When the memory module PSRAM adopts PSRAM technology, the master control device can enable the notification function of the pre-cycle pulse of the pilot pulse signal mstrb of the data strobe mask signal DQSM by setting the register. The pilot pulse signal mstrb refers to the period during which the memory module PSRAM pulls the level of the data strobe mask signal DQSM high for a short period of time before the data strobe mask signal DQSM sends the read strobe pulse signals mstrb1 and mstrb2. That is, before the actual pilot pulse signals mstrb1 and mstrb2 are generated, the master control device is notified in advance that the subsequent read data will be transmitted.

In the embodiment of FIG. 17 , the main control device can determine whether the memory module PSRAM1 has an update conflict by active sensing. Therefore, in this embodiment, the update conflict notification period Trfrp is not drawn. In actual application, the embodiment of FIG. 17 can also be implemented in combination with the immediate reporting mode (mode A) and the delayed reporting mode (mode B). That is, the memory module PSRAM1 that has an update conflict still notifies the main control device.

FIG18 is another embodiment of actively sensing the update conflict of the memory module PSRAM1 by the master device. Please refer to FIG18, which is a waveform diagram of an embodiment of how to perform a synchronous read operation after the memory module PSRAM1 has an update conflict by using the chip selection signal CS# in combination with the system frequency signal SCLK between the memory module and the master device, according to the time difference of the generation time of the pilot pulse signals m1pre and m2pre. In this figure, the time point t1 to the time point t15 is the read operation period Trd; the time point t1 to the time point t14 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read instruction transmission period Tcmd; the time point t4 to the time point t7 is the address transmission period Tadr; the time point t7 to the time point t13 is the synchronous data preparation period Tsdatpr; the time point t13 to the time point t15 is the synchronous data reading period Tdat_sync; the time point t14 to the time point t15 is the end period Tend. Here, the time point t5 to the time point t13 is the update conflict read period Trdrf. The time point t5 to the time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the memory module PSRAM2 to perform the read operation. The time point t9 to the time point t13 can be defined as the additional waiting period Taddwt required for the memory module PSRAM2 to wait for the update conflict of the memory module PSRAM1 to end.

In the example of FIG. 18 , it is assumed that the functions of the memory modules PSRAM1 and PSRAM2 to generate the pilot pulse signals m1pre and m2pre are both enabled. Because the memory module PSRAM1 has an update conflict, the period during which the memory module PSRAM1 generates the pilot pulse signal m1pre will be later than the period during which the memory module PSRAM2 generates the pilot pulse signal m2pre. The memory module PSRAM1 generates the pilot pulse signal m1pre using the data strobe mask signal DQSM[1] during the period from time t11 to time t12; and the memory module PSRAM2 generates the pilot pulse signal m2pre using the data strobe mask signal DQSM[2] during the period from time t8 to time t9.

As can be seen from FIG. 18 , the master control device only receives the pilot pulse signal m2pre generated by the memory module PSRAM2 using the data strobe shielding signal line DQSM[2] during the period from time t8 to time t9. The master control device needs to wait until the period from time t11 to time t12 to receive the pilot pulse signal m1pre generated by the memory module PSRAM1 using the data strobe shielding signal line DQSM[1]. Based on this, the master control device can know that there is a time difference in the process of providing the corresponding read data of the memory modules PSRAM1 and PSRAM2 based on the pilot pulse signals m1pre and m2pre generated successively (asynchronously). That is, since the master control device receives the pilot pulse signal m2pre from the memory module PSRAM2 first, the master control device can judge that the memory module PSRAM2 has not generated an update conflict; the master control device receives the pilot pulse signal m1pre from the memory module PSRAM1 later, and can judge that the memory module PSRAM1 has generated an update conflict. In this embodiment, since the main control device actively learns that the memory module PSRAM1 has an update conflict, and the memory module PSRAM1 does not notify it, this embodiment does not include the update conflict notification period Trfrp.

In FIG18 , the master control device can know that the memory module PSRAM1 needs to spend a longer time to perform the read operation according to the phenomenon that only the pilot pulse signal m2pre corresponding to the memory module PSRAM2 is generated during the period from time point t8 to time point t9, and the pilot pulse signal m1pre corresponding to the memory module PSRAM1 is not generated, and thus determines that the memory module PSRAM1 has an update conflict. Here, during the period from time point t5 to time point t11, the memory module PSRAM2 needs to wait for the update read delay rfcLC (for example, rfcLC=LC*2). Thereafter, the memory module PSRAM1 sends the pilot pulse signal m1pre during the period from time point t11 to time point t12.

Therefore, in FIG18 , it is assumed that the master device pulls up the chip select signal CS# during the system frequency cycle Tclk6 to notify the memory module PSRAM2 that it needs to wait for the memory module PSRAM1 to complete the update conflict. In actual application, the master device can also choose to pull up the chip select signal CS# during the system frequency cycles Tclk7 and Tclk8 to notify the memory module PSRAM2 that the read operation speed needs to be postponed.

Please note that, as mentioned in FIG. 18 , the master control device determines whether the memory module PSRAM1 has an update collision by guiding the pulse signals m1pre and m2pre, and notifies the memory module PSRAM2 that its read operation needs to be delayed by pulling the chip selection signal CS# high according to the system frequency cycle, but the actual application is not limited to this. Therefore, as mentioned in the other embodiments above, the methods of setting the memory bank busy signal BRBB and the frequency ignore signal ICK can also be modified and applied to the situation where the master control device determines whether the memory module PSRAM1 has an update collision by guiding the pulse signals m1pre and m2pree.

Incidentally, the main control device only chooses to use one of the system frequency cycles Tclk6, Tclk7, and Tclk8 to pull the chip selection signal CS# high. If the main control device pulls the chip selection signal CS# high for a period longer than one system frequency cycle Tclk, the memory module PSRAM2 may mistakenly believe that the main control device is preparing to force the end of the read operation. Therefore, in order to avoid malfunction of the memory module PSRAM2, this embodiment assumes that the main control device uses the method of pulling the chip selection signal CS# high for one system frequency cycle Tclk to notify the memory module PSRAM2 that the read operation period needs to be extended.

As can be seen from the above-mentioned multiple embodiments, the application of the present invention is quite flexible. First, the main control device can passively learn that an update conflict occurs inside the memory module PSRAM1 through the report of the memory module PSRAM1 (Figures 8A, 8B, 10, 11, 13, 14, 15, and 16); the main control device can actively determine that an update conflict occurs inside the memory module PSRAM1 by comparing the generation time points of the read flash pulse signals m1strb1 and m2strb1 (Figure 17); or the main control device can actively determine that an update conflict occurs inside the memory module PSRAM1 by detecting the guide pulse signals m1pre and m2pre (Figure 18). In addition, as for the report mode of the memory module PSRAM1, it can be further divided into an immediate report mode (mode A) and a delayed report mode (mode B) according to the report time point.

Furthermore, the aforementioned different embodiments also illustrate that if an update conflict occurs in the memory module PSRAM1, the memory module PSRAM1 can notify the main control device through different types of signal lines. For example: data flash mask signal DQSM[1], DQSM[2], memory bank busy signal BRBBh, BRBBm1, BRBBm2, chip select signal CS#, or a combination of chip select signal CS# and system clock signal SCLK waveform. In actual application, the type of signal line that the memory module PSRAM1 notifies the main control device and the control of its waveform are not limited to the aforementioned embodiments.

In addition, according to different embodiments, the memory module PSRAM2 may indirectly learn from the main control device that the memory module PSRAM1 has an update conflict; or the memory module PSRAM2 may directly learn from the memory module PSRAM1 that the memory module PSRAM1 has an update conflict.

In the aforementioned embodiment, the method for the memory module PSRAM2 to indirectly learn from the main control device that the memory module PSRAM1 has an update conflict includes: the main control device issues special read instructions m1CMDrd_sp, m2CMDrd_sp (Figure 8A), the main control device issues extended read instructions m1CMDext, m2CMDext (Figure 8B), the main control device changes the level of the chip select signal CS# (Figure 13), the main control device changes the combination of the chip select signal CS# and the system frequency signal SCLK (Figure 14), the main control device sets the additional frequency ignore signal lines ICK1, ICK2 (Figure 15), the main control device suspends the transmission of the system frequency signal SCLK (Figure 16), and repeats the read instructions m1CMDrtry, m2CMDrtry (Figure 17). In the aforementioned embodiment, the memory module PSRAM2 can directly receive the update conflict situation generated by the memory module PSRAM1 from the memory module PSRAM1, including: as shown in Figures 9A and 9B, the memory bank busy signal line BRBB is set in a wired OR manner; and, as shown in Figures 12A and 12B, the chip selection signal CS# is set in a wired OR manner.

According to the above description, it can be seen that the reading method of the present invention can be applied to electronic devices in a very flexible manner. In actual application, the memory module PSRAM2 indirectly learns from the main control device that the memory module PSRAM1 generates an update conflict, and the memory module PSRAM2 directly learns from the memory module PSRAM1 that the memory module PSRAM1 generates an update conflict, which is not limited to the above embodiment.

When the concept of the present invention is adopted, the main control device can know whether there is an update conflict in the memory module, and then notify other memory modules in the system to delay the time point of transmitting the read data, and ensure that the main control device can synchronously receive the read data from multiple memory modules. The memory module using PSRAM technology described in the present invention includes but is not limited to OctaRAM, HyperRAM, Xccela PSRAM, etc., and the transmission protocol adopted by the PSRAM technology can be a serial peripheral interface (Serial Peripheral Interface Bus, referred to as SPI), a double serial peripheral interface (Dual-SPI), a quadruple serial peripheral interface (QSPI), etc. In addition, although the waveform diagram of the present invention assumes that a read delay count LC is equivalent to three times the system frequency period (LC=3*Tclk), the actual application is not limited to this.

Please also note that although in the above description, it is assumed that the electronic device only includes two memory modules PSRAM1 and PSRAM2, the practical application of the present invention is not limited to this. For example, the electronic device may include four or eight memory modules. Or, multiple memory modules included in the electronic device may have update conflicts in turn. Then, the aforementioned reading method can still be based on a similar control method, and after all memory modules with update conflicts have completed the update conflicts, all memory modules are controlled to synchronously transmit read data. The aforementioned embodiments can be applied to these different types of electronic devices after modification.

The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A memory device, wherein the memory device is electrically connected to a host device, wherein the host device performs a read operation on the memory device during a read operation period, and the memory device comprises: a first memory module that generates an update conflict during the read operation; and a second memory module, wherein: The first memory module and the second memory module respectively receive a first read instruction and a second read instruction sent by the main control device during a read instruction transmission period; The first memory module and the second memory module respectively receive a first memory address and a second memory address during an address transmission period at the same time, wherein the read instruction transmission period is earlier than the address transmission period; and After a synchronous data preparation period, the first memory module and the second memory module simultaneously transmit a first synchronous read data and a second synchronous read data to the main control device during a synchronous data reading period, wherein the synchronous data preparation period is greater than a preset read delay; The main control device determines that the update conflict occurs in the first memory module during the synchronous data preparation period, and the main control device notifies the second memory module during the synchronous data preparation period that the read operation must be performed in a special data synchronization manner; wherein the special data synchronization manner is that the synchronous data preparation period of the first memory module and the second memory module is greater than the preset read delay when reading data; The first memory module sends a first pilot pulse signal in response to the read operation, and the second memory module sends a second pilot pulse signal in response to the read operation, wherein: The main control device determines whether the first memory module generates the update conflict according to the comparison between the first pilot pulse signal and the second pilot pulse signal. 2. The memory device according to claim 1, wherein: The master control device notifies the second memory module that the read operation should be performed in the special data synchronization mode; or The first memory module notifies the second memory module that the read operation should be performed in the special data synchronization manner. 3. The memory device according to claim 1, wherein: The first memory module reports the update conflict situation to the main control device before the read command transmission period starts; or The first memory module reports the update conflict situation to the main control device during the address transmission period. 4. The memory device according to claim 1, wherein the first memory module reports the update conflict situation to the main control device through one or a combination of a chip selection signal line, a data flash shield signal line, a dedicated signal line, a system frequency signal line, and a frequency ignore signal line. 5 . The memory device according to claim 1 , wherein the second memory module transmits a discard data during the synchronous data preparation period, wherein the content of the discard data is the same as the content of the second synchronous read data. 6. The memory device according to claim 1, wherein: The synchronous data preparation period is less than an update read delay, wherein the read operation period includes: A chip selection period is used to select the first memory module and the second memory module at the same time, wherein the chip selection period includes a setting period, the read instruction transmission period, the address transmission period, the synchronous data preparation period and a part of the synchronous data reading period. 7. The memory device of claim 1 , wherein the synchronous data preparation period is greater than an update read delay, wherein the read operation period comprises: A first chip selection period for selecting the first memory module and the second memory module at the same time, wherein the first chip selection period includes a setting period, the read command transmission period, the address transmission period and a portion of the synchronous data preparation period; One chip selects the spacing; A second chip selection period for selecting the first memory module and the second memory module at the same time, wherein the second chip selection period includes a command repetition transmission period, another part of the synchronous data preparation period and a part of the synchronous data reading period; and An end period, wherein the end period includes another portion of the synchronous data reading period. 8. The memory device according to claim 7, wherein: The first memory module transmits a first discarded data during the synchronous data preparation period, and the second memory module transmits a second discarded data during the synchronous data preparation period, The content of the first discarded data is the same as the content of the first synchronously read data, and the content of the second discarded data is the same as the content of the second synchronously read data. 9. The memory device according to claim 8, wherein: The first chip selection period includes the read instruction transmission period and the address transmission period, and The second chip selection period includes a command repetition transmission period, the synchronous data preparation period and the synchronous data reading period. 10 . The memory device according to claim 1 , wherein the read operation period comprises the read command transmission period, the address transmission period, the synchronous data preparation period and the synchronous data reading period. 11. An electronic device, comprising: A memory device comprising: a first memory module that generates an update conflict during a read operation; and a second memory module; and A main control device is electrically connected to the first memory module and the second memory module, wherein the main control device performs a read operation on the first memory module and the second memory module simultaneously during the read operation period, wherein: The first memory module and the second memory module simultaneously receive a read command sent by the main control device during a read command transmission period; The first memory module and the second memory module respectively receive a first memory address and a second memory address during an address transmission period at the same time, wherein the read instruction transmission period is earlier than the address transmission period; and After a synchronous data preparation period, the first memory module and the second memory module respectively transmit a first synchronous read data and a second synchronous read data to the main control device during a synchronous data reading period, wherein the synchronous data preparation period is greater than a preset read delay; The master control device determines that the first memory module generates the update conflict during the synchronous data preparation period, and the master control device notifies the second memory module during the synchronous data preparation period that the read operation must be performed in a special data synchronization mode; wherein the special data synchronization mode is that the synchronous data preparation period of the first memory module and the second memory module is greater than the preset read delay when reading data; The first memory module sends a first pilot pulse signal in response to the read operation, and the second memory module sends a second pilot pulse signal in response to the read operation, wherein: The main control device determines whether the first memory module generates the update conflict according to the comparison between the first pilot pulse signal and the second pilot pulse signal. 12. A reading method applied to an electronic device, wherein the electronic device comprises a main control device, a first memory module and a second memory module, wherein the main control device simultaneously performs a reading operation on the first memory module and the second memory module during a reading operation period, the first memory module generates an update conflict during the reading operation period, and the reading method comprises the following steps: The first memory module and the second memory module respectively receive a first read instruction and a second read instruction sent by the main control device during a read instruction transmission period; The first memory module and the second memory module respectively receive a first memory address and a second memory address during an address transmission period at the same time, wherein the read instruction transmission period is earlier than the address transmission period; and After a synchronous data preparation period, the first memory module and the second memory module respectively transmit a first synchronous read data and a second synchronous read data to the main control device during a synchronous data reading period, wherein the synchronous data preparation period is greater than a preset read delay; The main control device determines that the update conflict occurs in the first memory module during the synchronous data preparation period, and the main control device notifies the second memory module during the synchronous data preparation period that the read operation must be performed in a special data synchronization manner; wherein the special data synchronization manner is that the synchronous data preparation period of the first memory module and the second memory module is greater than the preset read delay when reading data; The first memory module sends a first pilot pulse signal in response to the read operation, and the second memory module sends a second pilot pulse signal in response to the read operation, wherein: The main control device determines whether the first memory module generates the update conflict according to the comparison between the first pilot pulse signal and the second pilot pulse signal.