CN113900579B - Memory device and writing method thereof - Google Patents
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- CN113900579B CN113900579B CN202010638044.2A CN202010638044A CN113900579B CN 113900579 B CN113900579 B CN 113900579B CN 202010638044 A CN202010638044 A CN 202010638044A CN 113900579 B CN113900579 B CN 113900579B
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000015654 memory Effects 0.000 claims abstract description 124
- 238000012795 verification Methods 0.000 claims abstract description 50
- 238000010586 diagram Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
本发明公开了一种存储器装置及其写入方法。控制电路对非易失性存储器的多个存储单元执行第一写入操作及第一写入验证操作，于上述多个存储单元通过第一写入验证操作后，对上述多个存储单元中对应至少一目标阈值电压的多个目标存储单元执行第二写入验证操作，于上述多个目标存储单元的失效位数未小于预设位数时，对上述多个存储单元执行第二写入操作及第三写入验证操作。
The present invention discloses a memory device and a writing method thereof. A control circuit performs a first writing operation and a first writing verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first writing verification operation, performs a second writing verification operation on a plurality of target memory cells corresponding to at least one target threshold voltage among the plurality of memory cells, and when the number of failure bits of the plurality of target memory cells is not less than a preset number of bits, performs a second writing operation and a third writing verification operation on the plurality of memory cells.
Description
Technical Field
The present invention relates to an electronic device, and more particularly, to a memory device and a writing method thereof.
Background
In recent years, nonvolatile memories are widely used in various electronic devices such as personal computers, notebook computers, smart phones, tablet computers, and the like. In response to the storage of large amounts of data, memories are moving toward greater capacity. The memory capacity can be effectively improved by the widely used three-dimensional stacked flash memory, however, the random telegraph noise (random telegraph noise, RTN) characteristic of the three-dimensional stacked element easily causes the threshold voltage of the memory cell to fluctuate, thereby causing the reading error. In addition, the three-dimensional stacked flash memory has a problem of lateral charge migration, which is likely to generate a negative shift of the threshold voltage immediately after writing because the charge trapping layers of the three-dimensional stacked flash memory are shared between word lines. The variation of the threshold voltage will reduce the read window, and the read error will occur easily, so how to ensure the threshold voltage distribution curve of the memory cell meets the expectations is an important issue.
Disclosure of Invention
The invention provides a memory device and a writing method thereof, which can effectively avoid the reduction of a reading window and reduce the situation of reading errors.
The memory device of the present invention includes a nonvolatile memory and a control circuit. The control circuit performs a first write operation and a first write verify operation on a plurality of memory cells of the nonvolatile memory. After the memory cells pass the first write verification operation, a second write verification operation is performed on a plurality of target memory cells corresponding to at least one target threshold voltage among the memory cells. And executing a second write operation and a third write verification operation on the plurality of memory cells when the failure bit number of the plurality of target memory cells is not smaller than the preset bit number.
The invention also provides a writing method of the memory device, the memory device comprises a plurality of memory units, and the writing method of the memory device comprises the following steps. And executing a first writing operation and a first writing verification operation on the plurality of memory cells. After the memory cells pass the first write verification operation, a second write verification operation is performed on a plurality of target memory cells corresponding to at least one target threshold voltage among the memory cells. Judging whether the failure bit number of the target storage unit is smaller than a preset bit number. And if the failure bit number of the target memory cells is not smaller than the preset bit number, executing a second write operation and a third write verification operation on the memory cells.
Based on the above, the control circuit according to the embodiment of the invention may perform the second write verification operation on the target memory cell corresponding to the at least one target threshold voltage in the memory cells after the memory cells pass the first write verification operation. And when the failure bit number of the target memory cell is not smaller than the preset bit number, executing a second write operation and a third write verification operation on the memory cell. Thus, the possibility of reading error can be effectively improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention.
FIG. 2 is a schematic diagram of threshold voltage distribution of a memory cell according to an embodiment of the invention.
FIG. 3 is a flow chart of a method of writing to a memory device according to an embodiment of the invention.
[ Symbolic description ]
100 Circle selection frame
102 Control circuit
104 Non-volatile memory
VT 1-VT 7 threshold voltage
PV, PV': write verification voltage
S302-S308 write method steps of memory device
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Fig. 1 is a schematic diagram of a memory device according to an embodiment of the invention, please refer to fig. 1. The memory device includes a control circuit 102 and a nonvolatile memory 104, the nonvolatile memory 104 may include a plurality of memory blocks, each memory block may include a plurality of memory pages, and the control circuit 102 may perform an access operation to the nonvolatile memory 104 in units of one memory page. Wherein each memory page includes a plurality of memory cells, which may be, for example, single level memory cells, multiple level memory cells, three level memory cells, or four level memory cells.
In this embodiment, taking a third-level memory cell as an example, each memory cell can store 3 bits of data, as shown in fig. 2 (a), each memory cell can have 8 logic states, and threshold voltages VT1 to VT7 can be used to distinguish states of data stored in the memory cells. The control circuit 102 may perform a first write operation and a first write verify operation on the memory cells in the memory page. Further, the control circuit 102 may apply an initial write voltage to the memory cells for writing data, for example, may apply a write pulse to each memory cell to move the threshold voltage of each memory cell to a desired corresponding voltage value (e.g., to move to or beyond one of the threshold voltages VT 1-VT 7), and apply a write verification voltage PV for write verification to the memory cell to determine whether each memory cell reaches the desired corresponding threshold voltage value (e.g., VT1, VT3 or other threshold voltages of the threshold voltages VT 1-VT 7) to determine whether the data is correctly written to the memory cell. In the present embodiment, the third-order memory cell has 8 logic states, and each logic state has a corresponding threshold voltage VT1 to VT7. If some memory cells fail the write verification of their corresponding threshold voltages, the data can be written again using the incremental step pulse programmable (INCREMENTAL STEP Pulse Programming, ISPP) voltages. That is, after each write verification failure, the write voltage is increased by a fixed voltage, and then data is written into the memory cells until all the memory cells pass the write verification of the corresponding threshold voltage. After all pass the first write verify operation, an offset occurs between the actual threshold voltage distribution curve (the distribution curve shown by the dotted line) and the expected threshold voltage distribution curve (the distribution curve shown by the solid line) of the memory cells in the memory page. A threshold voltage shift will likely occur due to random telegraph noise and lateral charge migration. As can be seen from fig. 2 (a), there is a maximum threshold voltage shift (shown by the dotted line) among the threshold voltage shifts of VT1 to VT7 on the distribution curve. This maximum threshold voltage shift is related to the highest threshold voltage VT7 as circled by circled box 100. The memory cells related to the distribution curve selected by the circled selection box 100 may be the target memory cell. It is noted that in other embodiments, memory cells associated with different threshold voltages may be used as the target memory cell. For example, memory cells distributed between threshold voltages VT3 and VT4 may be targeted memory cells. The selection of the target memory cell is not limited to the embodiment (a) of fig. 2.
As previously described, a second write verify operation may be performed on the target storage unit. As shown in fig. 2 (B), the control circuit 102 may apply the second write verification voltage PV' only to the target memory cell to determine whether the failure bit number (Failure Bit Count, FBC) is smaller than a preset bit number (e.g., 5 bits). The second write verification voltage PV' may be equal to or less than the first write verification voltage PV of the first write verification operation. For example, the second write verification voltage PV' may be less than or equal to 500mV, but is not limited thereto. The setting of the second write verification voltage PV' may be adjusted according to the actual requirements. The voltage value of the second write verification voltage PV' is determined, for example, according to the number of allowable fail bits. When the failure bit number (e.g. 3 bits) is smaller than the preset bit number (e.g. 5 bits), the writing method of the memory page is completed.
When the number of failed bits (e.g., 10 bits) is not smaller than the predetermined number of bits (e.g., 5 bits), the control circuit 102 may perform the second write operation and the third write verification operation on all the memory cells of the memory page to avoid the read window from shrinking. As shown in fig. 2 (C), the threshold voltage distribution curve of the memory cell is changed from the distribution curve shown by the dotted line to the distribution curve shown by the solid line, thereby reducing the possibility of occurrence of a read error. The second write operation and the third write verify operation ensure that the threshold voltage distribution curve of the memory cell is as expected.
As described above, the target memory cell may be the memory cell having the largest threshold voltage offset as circled by the circled frame 100 of fig. 2 (a). Therefore, only the second write verification is performed on the target memory cell to determine whether the second write operation is necessary, so that the data write efficiency of the memory page can be effectively improved by only the second write verification is performed on the target memory cell.
It should be noted that, when the control circuit 102 performs the second write operation and the third write verification operation, the operating parameters of the second write operation and the third write verification operation can be adjusted according to the actual requirements. For example, the operation parameters of the second write operation and the third write verification operation can be adjusted according to at least one of the failure bit number of the target memory cell and the data write efficiency requirement of the memory cell. The operating parameters may include, but are not limited to, an incremental step pulse programmable voltage, an initial write voltage, or a write verify voltage. For example, when the number of failed bits of the target memory cell is large or data writing is required to be completed in a short time, the voltage values of the incremental step pulse programmable voltage and the initial writing voltage can be increased. In addition, the voltage value of the write verification voltage can also be reduced.
FIG. 3 is a flow chart of a method of writing to a memory device according to an embodiment of the invention. As can be seen from the above embodiments, the method for writing a memory device can include the following steps. In step S302, a first write operation and a first write verify operation are performed on a plurality of memory cells, which may be, for example, single level memory cells, multi-level memory cells, third level memory cells, or fourth level memory cells. In step S304, after the plurality of memory cells pass the first write verification operation, a second write verification operation is performed on a plurality of target memory cells corresponding to at least one target threshold voltage among the plurality of memory cells. The at least one target threshold voltage may be a maximum threshold voltage among all threshold voltages of the plurality of memory cells. Further, the write verify voltage of the second write verify operation may be equal to or less than the write verify voltage of the first write verify operation, e.g., a voltage difference between the write verify voltage of the second write verify operation and the write verify voltage of the first write verify operation may be equal to or less than 500mV. In step S306, it is determined whether the number of fail bits of the plurality of target memory cells is smaller than a predetermined number of bits, and if the number of fail bits is smaller than the predetermined number of bits, the data writing method may be ended. In step S308, if the failure bit number is not smaller than the preset bit number, a second write operation and a third write verification operation are performed on the plurality of memory cells. Thus, the threshold voltage distribution curve of the memory cell is expected. The operating parameters of the second write operation and the third write verify operation may be adjusted while the second write operation and the third write verify operation are performed. The operating parameter is adjusted according to at least one of the failure bit number of the target memory cell and the data writing efficiency requirement of the plurality of memory cells. For example, parameters such as the incremental step pulse programmable voltage, the write voltage, and the write verify voltage may be adjusted.
The above embodiments disclose that the control circuit of the present invention may perform the second write verification operation on the target memory cell corresponding to at least one target threshold voltage in the plurality of memory cells after the plurality of memory cells pass the first write verification operation. And when the failure bit number of the target memory cell is not smaller than the preset bit number, executing a second write operation and a third write verification operation on the plurality of memory cells. As such, the actual threshold voltage distribution curve of the plurality of memory cells may conform to the expected threshold voltage distribution curve. The read window reduction and the possibility of read errors can be improved.
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.
Claims (10)
1. A memory device, comprising:
A nonvolatile memory, and
The control circuit is used for executing a first write operation and a first write verification operation on a plurality of storage units of the nonvolatile memory, executing a second write verification operation on a plurality of target storage units corresponding to at least one target threshold voltage in the storage units after the storage units pass through the first write verification operation, and executing a second write operation and a third write verification operation on the storage units when the failure bit number of the target storage units is not smaller than a preset bit number;
the first write verification operation is used for judging whether the memory cells reach expected corresponding threshold voltage values or not.
2. The memory device of claim 1, wherein a write verify voltage of the second write verify operation is less than or equal to a write verify voltage of the first write verify operation.
3. The memory device of claim 2, wherein a voltage difference between a write verify voltage of the second write verify operation and a write verify voltage of the first write verify operation is less than or equal to 500mV.
4. The memory device of claim 1, wherein the at least one target threshold voltage comprises a maximum threshold voltage of all threshold voltages of the memory cells.
5. The memory device of claim 1, wherein the control circuit adjusts the operating parameters of the second write operation and the third write verify operation according to at least one of a failure bit number of the target memory cell and a data write efficiency requirement of the memory cells.
6. The memory device of claim 5, wherein the operating parameters of the second write operation and the third write verify operation comprise an incremental step pulse programmable voltage, a write voltage, or a write verify voltage.
7. A method of writing to a memory device, the memory device comprising a plurality of memory cells, wherein the method of writing to the memory device comprises:
performing a first write operation and a first write verification operation on the memory cells, wherein the first write verification operation is used for judging whether the memory cells reach expected corresponding threshold voltage values or not;
after the memory cells pass the first write verification operation, performing a second write verification operation on a plurality of target memory cells corresponding to at least one target threshold voltage in the memory cells;
Judging whether the failure bit number of the target storage units is smaller than a preset bit number or not;
If the failure bit number of the target memory cells is not smaller than the preset bit number, a second write operation and a third write verification operation are executed on the memory cells.
8. The method of claim 7, wherein the second write verify operation has a write verify voltage less than or equal to the first write verify operation.
9. The method of claim 8, wherein a voltage difference between a write verify voltage of the second write verify operation and a write verify voltage of the first write verify operation is less than or equal to 500mV.
10. The method of claim 7, wherein the at least one target threshold voltage comprises a maximum threshold voltage of all threshold voltages of the memory cells.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/908,626 | 2020-06-22 | ||
| US16/908,626 US11056205B1 (en) | 2020-06-22 | 2020-06-22 | Memory device and write method thereof |
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| CN113900579A CN113900579A (en) | 2022-01-07 |
| CN113900579B true CN113900579B (en) | 2024-11-29 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201535384A (en) * | 2014-03-13 | 2015-09-16 | Phison Electronics Corp | Data storing method, memory control circuit unit and memory storage apparatus |
| CN109388518A (en) * | 2017-08-11 | 2019-02-26 | 华邦电子股份有限公司 | data writing method |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001243782A (en) * | 2001-02-13 | 2001-09-07 | Toshiba Corp | Non-volatile semiconductor memory |
| JP4270898B2 (en) * | 2003-02-07 | 2009-06-03 | Ｎｅｃエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
| US7577030B2 (en) * | 2007-01-17 | 2009-08-18 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
| US8325542B2 (en) * | 2008-08-25 | 2012-12-04 | Halo Lsi Inc. | Complementary reference method for high reliability trap-type non-volatile memory |
| JP2013125576A (en) * | 2011-12-16 | 2013-06-24 | Samsung Electronics Co Ltd | Nonvolatile semiconductor storage device |
| CN103870399B (en) * | 2012-12-18 | 2017-03-01 | 群联电子股份有限公司 | Memory management method, memory controller and memory storage device |
| JP2019057345A (en) * | 2017-09-20 | 2019-04-11 | 東芝メモリ株式会社 | Semiconductor memory device |
| KR102612891B1 (en) * | 2018-05-31 | 2023-12-13 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof and memory system |
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- 2020-06-22 US US16/908,626 patent/US11056205B1/en active Active
- 2020-07-03 CN CN202010638044.2A patent/CN113900579B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201535384A (en) * | 2014-03-13 | 2015-09-16 | Phison Electronics Corp | Data storing method, memory control circuit unit and memory storage apparatus |
| CN109388518A (en) * | 2017-08-11 | 2019-02-26 | 华邦电子股份有限公司 | data writing method |
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| US11056205B1 (en) | 2021-07-06 |
| CN113900579A (en) | 2022-01-07 |
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