CN113889040A - Grid driving circuit and display device - Google Patents
Grid driving circuit and display device Download PDFInfo
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- CN113889040A CN113889040A CN202111388978.6A CN202111388978A CN113889040A CN 113889040 A CN113889040 A CN 113889040A CN 202111388978 A CN202111388978 A CN 202111388978A CN 113889040 A CN113889040 A CN 113889040A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a gate driving circuit and a display device, which can comprise a first driving circuit layer and a second driving circuit layer which are stacked on a substrate, wherein the first driving circuit layer comprises at least one first thin film transistor, the second driving circuit layer comprises at least one second thin film transistor, the orthographic projection of the at least one first thin film transistor on the substrate is at least partially overlapped with the orthographic projection of the at least one second thin film transistor on the substrate, and the carrier mobility of the second thin film transistor is larger than that of the first thin film transistor. Through the stacked layer arrangement, on one hand, the occupied area of a gate driving circuit is reduced, narrow frame design is facilitated, the number of pixel units is increased, and the resolution and the aperture opening ratio of the display panel are improved; on the other hand, at least one driving circuit layer can avoid the influence of illumination, thereby improving the overall illumination stability of the gate driving circuit.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit and a display device.
Background
With the rapid development of smart devices and the Internet of Things (IoT), Augmented Reality (AR), Virtual Reality (VR), and Mixed or Merged Reality (MR) are receiving increasing attention. By collecting and exchanging information of both parties, a super-connected society can be realized. With the development of AR, VR and MR technologies, the demand for ultra-high resolution and high quality displays is increasing. The near-eye format of AR terminals requires high definition to make the pixel density exceed the mode resolution capability of the human retina.
In recent years, Active-matrix organic light-emitting diode (AMOLED) displays based on an Oxide TFT (Thin Film Transistor) substrate have attracted more and more attention, wherein a Transparent Amorphous Oxide Semiconductor (TAOS) may be used in some large-sized AMOLED displays, which is advantageous for the AMOLED displays to produce high device performance even at low process temperature. However, the resolution required in the current VA or VR product high PPI (pixel density) scene is about 10-100 times that of the television handset, etc., and the carrier mobility of the oxide can only be 10cm at present2V · s, the demand for ultra high definition display cannot be satisfied. Therefore, development of a high-resolution display substrate having excellent TFT performance is an urgent problem to be solved.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the existing display panel has low resolution, and how to effectively improve the resolution of the display panel through the arrangement of a gate drive circuit.
In order to solve the above technical problems, the present invention provides a gate driving circuit and a display device.
In a first aspect of the present invention, there is provided a gate driving circuit, comprising:
a first driving circuit layer and a second driving circuit layer stacked on the substrate;
the first driving circuit layer comprises at least one first thin film transistor, the second driving circuit layer comprises at least one second thin film transistor, the orthographic projection of the at least one first thin film transistor on the substrate at least partially overlaps with the orthographic projection of the at least one second thin film transistor on the substrate, and the carrier mobility of the second thin film transistor is larger than that of the first thin film transistor.
In some embodiments, the first driving circuit layer is disposed between the substrate and the second driving circuit layer, and a distance from the first thin film transistor to the substrate is smaller than a distance from the second thin film transistor to the substrate.
In some embodiments, the gate driving circuit includes: the display device comprises an input circuit, an output circuit, a noise reduction circuit and a reset circuit, wherein the input circuit, the output circuit, the noise reduction circuit and the reset circuit comprise at least one first thin film transistor and at least one second thin film transistor, and the orthographic projection of at least one first thin film transistor in the input circuit, the output circuit, the noise reduction circuit and the reset circuit on the substrate at least partially overlaps with the orthographic projection of at least one second thin film transistor on the substrate.
In some embodiments, the input circuit and the output circuit each include at least one of the second thin film transistors, and the noise reduction circuit and the reset circuit each include at least one of the first thin film transistors.
In some embodiments, at least one of the input circuit, the output circuit, the noise reduction circuit, and the reset circuit includes at least one set of the first thin film transistor and the second thin film transistor disposed to overlap.
In some embodiments, the input circuit includes a switch unit M1, a first terminal and a control terminal of the switch unit M1 are respectively connected to the signal input terminals, and a second terminal of the switch unit M1 is connected to the pull-up node;
the output circuit comprises a switch unit M3 and a capacitor C1; a first terminal of the switch unit M3 is connected to a first clock signal input terminal, a control terminal of the switch unit M3 is connected to the pull-up node, a second terminal of the switch unit M3 is connected to a signal output terminal, a first terminal of the capacitor C1 is connected to the pull-up node, and a second terminal of the capacitor C1 is connected to the signal output terminal;
the noise reduction circuit comprises a switch unit M5, a switch unit M6, a switch unit M8, a switch unit M9 and a switch unit M10; a first terminal and a control terminal of the switch unit M9 are respectively connected to a second clock signal input terminal, and a second terminal of the switch unit M9 is connected to a first pull-down node; a first terminal of the switch unit M5 is connected to the second clock signal input terminal, a control terminal of the switch unit M5 is connected to the first pull-down node, and a second terminal of the switch unit M5 is connected to the second pull-down node; control terminals of the switch unit M8 and the switch unit M6 are connected to the pull-up node, a first terminal of the switch unit M8 is connected to the first pull-down node, and a first terminal of the switch unit M6 is connected to the second pull-down node; a control terminal of the switch unit M10 is connected to the second pull-down node, and a first terminal of the switch unit M10 is connected to the pull-up node; second ends of the switch unit M6, the switch unit M8 and the switch unit M10 are connected with a constant voltage signal input end;
the reset circuit comprises a switch unit M2 and a switch unit M11; a control terminal of the switch unit M2 is connected to a reset signal input terminal, a first terminal of the switch unit M2 is connected to the pull-up node, and a second terminal of the switch unit M2 is connected to the constant voltage signal input terminal; the control end of the switch unit M11 is connected to the second pull-down node, the first end of the switch unit M11 is connected to the signal output end, and the second end of the switch unit M11 is connected to the constant voltage signal input end.
In some embodiments, at least one of the switch unit M1, the switch unit M3, the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2, and the switch unit M11 is the first thin film transistor, and the rest is the second thin film transistor, and a front projection of at least one switch unit disposed as the first thin film transistor on the substrate and a front projection of at least one switch unit disposed as the second thin film transistor on the substrate at least partially overlap.
In some embodiments, the switch unit M1 and the switch unit M3 are both the second thin film transistor; the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2, and the switch unit M11 are all the first thin film transistors.
In some embodiments, at least one of the switching unit M5, the switching unit M6, the switching unit M8, the switching unit M9, and the switching unit M10 is the second thin film transistor and the rest are the first thin film transistor; and/or the presence of a gas in the gas,
one of the switch unit M2 and the switch unit M11 is the second thin film transistor and the other is the first thin film transistor, and an orthographic projection of the switch unit M2 on the substrate at least partially overlaps with an orthographic projection of the switch unit M11 on the substrate.
In some embodiments, the active layer of the second thin film transistor comprises a metal oxide semiconductor arranged in a stacked manner, and the active layer of the first thin film transistor is a single layer of metal oxide semiconductor.
In some embodiments, at least one of the first thin film transistors and/or at least one of the second thin film transistors is a double gate transistor.
In a second aspect of the invention, there is provided a display device comprising a gate driver circuit as described in any one of the above.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the gate driving circuit to which the present invention is applied may include a first driving circuit layer and a second driving circuit layer stacked on a substrate, wherein the first driving circuit layer includes at least one first thin film transistor therein, the second driving circuit layer includes at least one second thin film transistor therein, an orthographic projection of the at least one first thin film transistor on the substrate at least partially overlaps an orthographic projection of the at least one second thin film transistor on the substrate, and a carrier mobility of the second thin film transistor is greater than a carrier mobility of the first thin film transistor. Through the stacked layer arrangement, on one hand, the occupied area of a gate driving circuit is reduced, narrow frame design is facilitated, the number of pixel units is increased, and the resolution and the aperture opening ratio of the display panel are improved; on the other hand, at least one driving circuit layer can avoid the influence of illumination, thereby improving the overall illumination stability of the gate driving circuit.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Wherein the included drawings are:
fig. 1 is a schematic cross-sectional view illustrating a gate driving circuit according to the present invention;
fig. 2 is a schematic cross-sectional view illustrating another gate driving circuit according to an embodiment of the invention;
fig. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view illustrating a gate driving circuit provided with multiple active layers according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will describe in detail an implementation method of the present invention with reference to the accompanying drawings and embodiments, so that how to apply technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.
With the rapid development of smart devices and the Internet of Things (IoT), Augmented Reality (AR), Virtual Reality (VR), and Mixed or Merged Reality (MR) are receiving increasing attention. By collecting and exchanging information of both parties, a super-connected society can be realized. With the development of AR, VR and MR technologies, the demand for ultra-high resolution and high quality displays is increasing. The near-eye format of AR terminals requires high definition to make the pixel density exceed the mode resolution capability of the human retina.
In recent years, Active-matrix organic light-emitting diode (AMOLED) displays based on an Oxide TFT (Thin Film Transistor) substrate have attracted more and more attention, wherein a Transparent Amorphous Oxide Semiconductor (TAOS) may be used in some large-sized AMOLED displays, which is advantageous for the AMOLED displays to produce high device performance even at low process temperature. However, the resolution required in the current VA or VR product high PPI (pixel density) scene is about 10-100 times that of the television handset, etc., and the carrier mobility of the oxide can only be 10cm at present2V · s, the demand for ultra high definition display cannot be satisfied. Therefore, development of a high-resolution display panel having excellent TFT performance is an urgent problem to be solved.
In view of the foregoing, the present invention provides a display panel, which may include a first driving circuit layer and a second driving circuit layer stacked on a substrate, wherein the first driving circuit layer includes at least one first thin film transistor, the second driving circuit layer includes at least one second thin film transistor, an orthographic projection of the at least one first thin film transistor on the substrate at least partially overlaps an orthographic projection of the at least one second thin film transistor on the substrate, and a carrier mobility of the second thin film transistor is greater than a carrier mobility of the first thin film transistor. Through the stacked layer arrangement, on one hand, the occupied area of a gate driving circuit is reduced, narrow frame design is facilitated, the number of pixel units is increased, and the resolution and the aperture opening ratio of the display panel are improved; on the other hand, at least one driving circuit layer can avoid the influence of illumination, thereby improving the overall illumination stability of the gate driving circuit.
Example one
Referring to fig. 1, fig. 1 is a schematic cross-sectional view illustrating a gate driving circuit according to the present invention, which may include:
a gate driving circuit on the substrate 10, the gate driving circuit including a first driving circuit layer 11 and a second driving circuit layer 12 stacked on the substrate 10;
the first driving circuit layer 11 includes at least one first thin film transistor 13, the second driving circuit layer 12 includes at least one second thin film transistor 14, an orthographic projection of the at least one first thin film transistor 13 on the substrate 10 at least partially overlaps an orthographic projection of the at least one second thin film transistor 14 on the substrate 10, and a carrier mobility of the second thin film transistor 14 is greater than a carrier mobility of the first thin film transistor 13.
In some embodiments, the gate driving circuit may be applied to a liquid crystal display panel, the first driving circuit layer 11 is disposed between the substrate 10 and the second driving circuit layer 12, and a distance from the first thin film transistor 13 to the substrate 10 is smaller than a distance from the second thin film transistor 14 to the substrate 10. The thin film transistor with the high carrier mobility is greatly influenced by illumination, the second driving circuit layer 12 comprising the second thin film transistor 14 is arranged on the first driving circuit layer 11, the first thin film transistor 13 with the low carrier mobility is closer to the substrate 10, and the second thin film transistor 14 is far away from the substrate 10 relative to the first thin film transistor 13, so that the second thin film transistor 14 with the high carrier mobility is protected, and the overall illumination stability of the gate driving circuit is further improved.
In other embodiments, the gate driving circuit may also be applied to an organic light emitting display panel, in some embodiments, when the organic light emitting display panel is a top emission organic light emitting display panel, the first driving circuit layer 11 may be disposed between the substrate 10 and the second driving circuit layer 12, a distance from the first thin film transistor 13 to the substrate 10 is smaller than a distance from the second thin film transistor 14 to the substrate 10, and the second driving circuit layer 12 with a higher requirement on illumination stability is disposed on the first driving circuit layer 11 to avoid an influence of light reflected by a back film on the back surface of the substrate 10 on the second thin film transistor 14 in the second driving circuit layer 12; in other embodiments, when the organic light emitting display panel is a bottom emission organic light emitting display panel, the second driving circuit layer 12 may be disposed between the substrate 10 and the first driving circuit layer 11, and a distance from the first thin film transistor 13 to the substrate 10 is greater than a distance from the second thin film transistor 14 to the substrate 10, so that the second thin film transistor 14 which is greatly affected by illumination is far away from the illumination, thereby improving the illumination stability of the whole gate driving circuit.
It should be noted that, in the following embodiments, a gate driving circuit in which the first driving circuit layer 11 is disposed between the substrate 10 and the second driving circuit layer 12 and the distance from the first thin film transistor 13 to the substrate 10 is smaller than the distance from the second thin film transistor 14 to the substrate 10 will be described as an example.
In some embodiments, the gate driving circuit may further include a protective layer 15 disposed between the first driving circuit layer 11 and the second driving circuit layer 12 for isolating adjacent driving circuit layers. The protective layer 15 may be made of an insulating material, and in some embodiments, the protective layer 15 may be provided as a single-layer or multi-layer structure.
In some embodiments, the carrier mobility of the first thin film transistor 13 may be less than or equal to 20cm2Vs, the carrier mobility of the second TFT 14 may be greater than 20cm2/Vs。
In some embodiments, the first thin film transistor 13 and/or the second thin film transistor 14 may employ a bottom gate structure or a top gate structure.
As shown in fig. 1, in some embodiments, the first thin film transistor 13 and the second thin film transistor 14 may each adopt a bottom-gate structure, the first thin film transistor 13 may include a gate electrode 131, an interlayer dielectric layer 132, an active layer 133, a source electrode 134, and a drain electrode 135 on the substrate 10, the source electrode 134 and the drain electrode 135 are electrically connected to the active layer 133, and the protective layer 15 covers a portion of the interlayer dielectric layer 132, a portion of the active layer 133, the source electrode 134, and the drain electrode 135 on the first driving circuit layer 11. The second thin film transistor 14 may include a gate electrode 141, an interlayer dielectric layer 142, an active layer 143, a source electrode 144, and a drain electrode 145 on the protective layer 15, the source electrode 144 and the drain electrode 145 being electrically connected to the active layer 143.
In other embodiments, at least one of the first thin film transistor 13 and/or the second thin film transistor 14 may be a double gate transistor. Referring to fig. 2, fig. 2 is a schematic cross-sectional view illustrating another gate driving circuit according to an embodiment of the present invention, wherein the first thin film transistor 21 in the first driving circuit layer 11 may be a double-gate transistor, which may include:
a first gate 211, a first interlayer dielectric layer 212, an active layer 213, a second interlayer dielectric layer 214 and a second gate 215 which are sequentially stacked on the substrate;
the projection of the second gate 215 on the substrate 10 at least partially overlaps the projection of the first gate 211 on the substrate 10.
In the embodiment of the present invention, as shown in fig. 2, the first thin film transistor 21 may further include a source electrode 216 and a drain electrode 217 electrically connected to the active layer 213, the second thin film transistor 22 may have a bottom gate structure, and the second thin film transistor 22 may be configured in the same manner as the second thin film transistor 14 in fig. 1.
By configuring the first thin film transistor 21 as a double gate transistor, the induced charges generated by the potentials of the first gate electrode 211 and the second gate electrode 215 are not limited to the bottom interface region or the top interface region of the active layer 213, but may extend to the entire thickness of the active layer 213, and the concentration of the carriers in the first thin film transistor 21 is increased, thereby effectively improving the carrier mobility of the first thin film transistor 21 and further improving the resolution of the display panel.
As shown in fig. 2, the first thin film transistor 21 in the first driving circuit layer 11 and the second thin film transistor 22 in the second driving circuit layer 12 may share a gate drive, and the gate of the second thin film transistor 22 may be electrically connected to the source 216 of the first thin film transistor 21 through a via hole penetrating through the protective layer 15 and the second interlayer dielectric layer 214.
In some embodiments, referring to fig. 3, fig. 3 illustrates a schematic diagram of a gate driving circuit provided by an embodiment of the present invention, which may include:
an input circuit 31, an output circuit 32, a noise reduction circuit 33, and a reset circuit 34;
the INPUT end and the output end of the INPUT circuit 31 are respectively connected to the signal INPUT end INPUT and the pull-up node PU, and are used for controlling the signal of the pull-up node PU according to the signal of the signal INPUT end INPUT;
an OUTPUT circuit 32, an input terminal of which is connected to the first clock signal input terminal CLK, a control terminal of which is connected to the pull-up node PU, and an OUTPUT terminal of which is connected to the signal OUTPUT terminal OUTPUT, for outputting the signal of the first clock signal input terminal CLK according to the signal control signal OUTPUT terminal OUTPUT of the pull-up node PU;
a noise reduction circuit 33 having a first input terminal connected to the second clock signal input terminal GCH, a second input terminal connected to the constant voltage signal input terminal VSS, a control terminal connected to the pull-up node PU, and an OUTPUT terminal connected to the signal OUTPUT terminal OUTPUT, for controlling the OUTPUT of the signal OUTPUT terminal OUTPUT according to the signal of the pull-up node PU, the second clock signal input terminal GCH, or the constant voltage signal input terminal VSS;
the RESET circuit 34 has an input terminal connected to the constant voltage signal input terminal VSS, a control terminal connected to the RESET signal input terminal RESET, and an output terminal connected to the pull-up node PU, and is configured to control the pull-up node PU to output a signal of the constant voltage signal input terminal VSS according to a signal of the RESET signal input terminal RESET.
The input circuit 31, the output circuit 32, the noise reduction circuit 33, and the reset circuit 34 include at least one first thin film transistor and at least one second thin film transistor, and an orthogonal projection of at least one first thin film transistor of the input circuit 31, the output circuit 32, the noise reduction circuit 33, and the reset circuit 34 on the substrate 10 at least partially overlaps an orthogonal projection of at least one second thin film transistor on the substrate 10.
In some embodiments, the input circuit 31 and the output circuit 32 each include at least one second thin film transistor (14,22), and the noise reduction circuit 33 and the reset circuit 34 each include at least one first thin film transistor (13, 21). The second thin film transistors (14,22) with high carrier mobility are adopted in the input circuit 31 and the output circuit 32, the requirement on illumination stability is high, and the influence of illumination on the input circuit 31 and the output circuit 32 is effectively avoided by arranging the second thin film transistors in the second driving circuit layer 12 which is far away from the substrate 10. The noise reduction circuit 33 and the reset circuit 34 may employ first thin film transistors (13,21) having a lower carrier mobility and be disposed in the first drive circuit layer 11, and the first drive circuit layer 11 may be disposed between the substrate 10 and the second drive circuit layer 12.
Wherein an orthographic projection of the at least one second thin film transistor (14,22) in the input circuit 31 and the output circuit 32 on the substrate 10 at least partially overlaps an orthographic projection of the at least one first thin film transistor (13,21) in the noise reduction circuit 33 and the reset circuit 34 on the substrate 10. The area occupied by the grid driving circuit is reduced, and the resolution, the aperture opening ratio and the whole illumination stability of the display panel are improved.
In other embodiments, at least one of the input circuit 31, the output circuit 32, the noise reduction circuit 33, and the reset circuit 34 includes at least one set of first thin film transistors (13,21) and second thin film transistors (14,22) arranged in an overlapping manner.
In some embodiments, the input circuit 31 and the output circuit 32 each include at least one second thin film transistor (14,22), and the noise reduction circuit 33 and the reset circuit 34 each include at least one set of first thin film transistors (13,21) and second thin film transistors (14,22) arranged in an overlapping manner. The orthographic projection of at least one second thin film transistor (14,22) in the input circuit 31 and the output circuit 32 on the substrate 10 at least partially overlaps the orthographic projection of at least one first thin film transistor (13,21) in the noise reduction circuit 33 and the reset circuit 34 on the substrate 10, and the orthographic projection of at least one first thin film transistor (13,21) in the noise reduction circuit 33 on the substrate 10 at least partially overlaps the orthographic projection of at least one second thin film transistor (14,22) in the circuit on the substrate 10; an orthographic projection of at least one first thin film transistor (13,21) in the reset circuit 34 on the substrate 10 at least partially overlaps an orthographic projection of at least one second thin film transistor (14,22) in the circuit on the substrate 10. The noise reduction circuit 33 and the reset circuit 34 include at least one set of overlapped second thin film transistor and first thin film transistor, and the noise reduction circuit 33 and the reset circuit 34 can be arranged in a layered manner, so that the area occupied by the gate drive circuit can be further reduced, and the resolution, the aperture ratio and the overall illumination stability of the display panel can be improved.
In some embodiments, as shown in fig. 3, the INPUT circuit 31 includes a switch unit M1, a first terminal and a control terminal of the switch unit M1 are respectively connected to the signal INPUT terminal INPUT, and a second terminal of the switch unit M1 is connected to the pull-up node PU.
The output circuit 32 includes a switching unit M3 and a capacitor C1;
a first terminal of the switch unit M3 is connected to the first clock signal input terminal CLK, a control terminal of the switch unit M3 is connected to the pull-up node PU, a second terminal of the switch unit M3 is connected to the signal OUTPUT terminal OUTPUT, a first terminal of the capacitor C1 is connected to the pull-up node PU, and a second terminal of the capacitor C1 is connected to the signal OUTPUT terminal OUTPUT.
The noise reduction circuit 33 includes: a switch unit M5, a switch unit M6, a switch unit M8, a switch unit M9, and a switch unit M10;
a first terminal and a control terminal of the switching unit M9 are respectively connected to the second clock signal input terminal GCH, and a second terminal of the switching unit M9 is connected to the first pull-down node PD _ CN; a first terminal of the switch unit M5 is connected to the second clock signal input terminal GCH, a control terminal of the switch unit M5 is connected to the first pull-down node PD _ CN, and a second terminal of the switch unit M5 is connected to the second pull-down node PD; the control ends of the switch unit M8 and the switch unit M6 are connected to the pull-up node PU, the first end of the switch unit M8 is connected to the first pull-down node PD _ CN, and the first end of the switch unit M6 is connected to the second pull-down node PD; the control end of the switch unit M10 is connected to the second pull-down node PD, and the first end of the switch unit M10 is connected to the pull-up node PU; second terminals of the switch unit M6, the switch unit M8 and the switch unit M10 are all connected to a constant voltage signal input terminal VSS.
The reset circuit 34 includes a switch unit M2 and a switch unit M11;
the control end of the switch unit M2 is connected with a RESET signal input end RESET, the first end of the switch unit M2 is connected with a pull-up node PU, and the second end of the switch unit M2 is connected with a constant voltage signal input end VSS; the control terminal of the switching unit M11 is connected to the second pull-down node PD, the first terminal of the switching unit M11 is connected to the signal OUTPUT terminal OUTPUT, and the second terminal of the switching unit M11 is connected to the constant voltage signal input terminal VSS.
In some embodiments, at least one of the switch unit M1, the switch unit M3, the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2, and the switch unit M11 is a first thin film transistor (13,21) and the rest is a second thin film transistor (14,22), and a front projection of at least one switch unit provided as the first thin film transistor (13,21) on the substrate 10 and a front projection of at least one switch unit provided as the second thin film transistor (14,22) on the substrate 10 at least partially overlap.
In some embodiments, the switch unit M1 and the switch unit M3 are both second thin film transistors (14, 22); the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2, and the switch unit M11 are all first thin film transistors (13, 21).
In some embodiments, at least one of the switching unit M5, the switching unit M6, the switching unit M8, the switching unit M9, and the switching unit M10 is a second thin film transistor (14,22) and the rest are first thin film transistors (13, 21); as an example, one of the switch unit M8 and the switch unit M6 may be provided as a first thin film transistor (13,21), and the other may be provided as a second thin film transistor (14,22), and orthographic projections of the switch unit M8 and the switch unit M6 on the substrate 10 at least partially overlap, and the switch unit M5, the switch unit M9, and the switch unit M10 may all be the first thin film transistor or all the second thin film transistors, so as to further reduce the area occupied by the noise reduction circuit 33 in the gate driving circuit.
In some embodiments, one of the switch unit M2 and the switch unit M11 is a second thin film transistor (14,22) and the other is a first thin film transistor (13,21), and an orthographic projection of the switch unit M2 on the substrate 10 at least partially overlaps an orthographic projection of the switch unit M11 on the substrate 10 to further reduce an area occupied by the reset circuit 34 in the gate driving circuit.
In some embodiments, the gate electrode (131,141), the first gate electrode 211, or the second gate electrode 215 may be provided as a single-layer structure or a multi-layer structure. As an example, the gate electrode (131,141), the first gate electrode 211, or the second gate electrode 215 may be a single-layer structure made of molybdenum or copper; the gate (131,141), the first gate 211, or the second gate 215 may also be a double-layer structure made using a MoNb (molybdenum niobium)/Gu stack; the gate (131,141), the first gate 211, or the second gate 215 may also be a triple-layer structure made of MoNb/Gu/MTD or MTD/Gu/MTD (motini). In some embodiments, the gate electrode (131,141), the first gate electrode 211, or the second gate electrode 215 has a thickness of
In some embodiments, the interlayer dielectric layer (132,142), the first interlayer dielectric layer 212, or the second interlayer dielectric layer 214 may be provided as a single layer structure or a multi-layer structure. By way of example, the interlevel dielectric layers (132,142), the first interlevel dielectric layer 212, or the second interlevel dielectric layer 214 may be of SiN/SiO2Or SiN/SiON/SiO2The resulting multilayer structure. In some embodiments, SiN may be disposed on a side close to the substrate 10, and the SiN may be disposed in a single layer or a plurality of layers; SiO 22May be provided on the side remote from the substrate 10; as an example, the SiN may be of a thickness of
The thickness of SiON may be
SiO2May be of a thickness of
In embodiments of the present invention, the active layer (133,143,213) may be provided as a single layer or a multi-layer structure. In some embodiments, the active layer (133,143,213) may include an oxide semiconductor, and the semiconductor oxide may include at least one of IZO (Indium zinc oxide), ITO (Indium tin oxide), IGTO (Indium gallium tin oxide), IGZO (Indium gallium zinc oxide), and ITZO (Indium tin zinc oxide), as examples.
In some embodiments, the active layer of the second thin film transistor comprises a metal oxide semiconductor arranged in a stacked manner, and the active layer of the first thin film transistor is a single layer of metal oxide semiconductor. Referring to fig. 4, fig. 4 is a schematic cross-sectional structural diagram of a gate driving circuit provided with multiple active layers according to an embodiment of the present invention, where the first driving circuit layer 11 may include a first thin film transistor 41, and the first thin film transistor 41 may be a double-gate transistor; the second thin film transistor 42 may be included in the second driving circuit layer, the second thin film transistor 42 includes a gate 421, a third interlayer dielectric layer 422, a first active layer 4231 and a second active layer 4232, which are sequentially disposed on the protective layer 15, and the first active layer 4231 may be made of an oxide semiconductor material with a high carrier mobility, which may have a carrier mobility greater than 20cm2/Vs, as an example, IZO, ITO or IGTO; the second active layer 4232 may be made of an oxide semiconductor material having good stability, and may be made of, for example, an IGZO or Al-ITZO low carrier mobility material. The active layer is prepared by adopting the oxide semiconductor or prepared into a multilayer structure, so that the carrier mobility is further improved, the reduction design of the thin film transistor is realized, the occupied area of a gate drive circuit is reduced, the resolution is improved, and the power consumption is reduced.
The gate driving circuit provided above for the embodiment of the present invention may include a first driving circuit layer 11 and a second driving circuit layer 12 stacked on a substrate 10, where the first driving circuit layer 11 includes at least one first thin film transistor (13,21,41), the second driving circuit layer 12 includes at least one second thin film transistor (14,22,42), an orthographic projection of the at least one first thin film transistor (13,21,41) on the substrate 10 at least partially overlaps an orthographic projection of the at least one second thin film transistor (14,22,42) on the substrate 10, and a carrier mobility of the second thin film transistor (14,22,42) is greater than a carrier mobility of the first thin film transistor (13,21, 41). Through the stacked layer arrangement, on one hand, the occupied area of a gate driving circuit is reduced, narrow frame design is facilitated, the number of pixel units is increased, and the resolution and the aperture opening ratio of the display panel are improved; on the other hand, at least one driving circuit layer can avoid the influence of illumination, thereby improving the overall illumination stability of the gate driving circuit. In addition, the first thin film transistor (13,21,41) and/or the second thin film transistor (14,22,42) are arranged to be of a double-gate structure, the active layer is prepared by adopting an oxide semiconductor with high carrier mobility, or the active layer is arranged to contain a metal oxide semiconductor which is arranged in a laminated manner, so that the carrier mobility of the display panel can be further effectively improved, the reduction design of the thin film transistor can be realized, the occupied area of a gate drive circuit is reduced, the resolution is improved, the driving capability of the whole display panel is improved, and the power consumption is reduced.
Example two
The invention also provides a display device which can comprise the gate driving circuit as described in the first embodiment.
In some embodiments, the Display apparatus may further include an Organic light emitting Display device (OLED device) or a Liquid Crystal Display device (LCD device) disposed in the Display region, and the gate driving circuit may provide a driving signal to the OLED device or the LCD device.
In some embodiments, the display device may be embodied as any product having a display function, such as an image pickup device, a liquid crystal display device, an electroluminescence display device, or the like.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A gate drive circuit, comprising:
a first driving circuit layer and a second driving circuit layer stacked on the substrate;
the first driving circuit layer comprises at least one first thin film transistor, the second driving circuit layer comprises at least one second thin film transistor, the orthographic projection of the at least one first thin film transistor on the substrate at least partially overlaps with the orthographic projection of the at least one second thin film transistor on the substrate, and the carrier mobility of the second thin film transistor is larger than that of the first thin film transistor.
2. A gate driver circuit according to claim 1, wherein the first driver circuit layer is disposed between the substrate and the second driver circuit layer, and a distance from the first thin film transistor to the substrate is smaller than a distance from the second thin film transistor to the substrate.
3. The gate driving circuit of claim 1, wherein the gate driving circuit comprises: the display device comprises an input circuit, an output circuit, a noise reduction circuit and a reset circuit, wherein the input circuit, the output circuit, the noise reduction circuit and the reset circuit comprise at least one first thin film transistor and at least one second thin film transistor, and the orthographic projection of at least one first thin film transistor in the input circuit, the output circuit, the noise reduction circuit and the reset circuit on the substrate at least partially overlaps with the orthographic projection of at least one second thin film transistor on the substrate.
4. A gate drive circuit as claimed in claim 3, wherein the input circuit and the output circuit each comprise at least one of the second thin film transistors, and the noise reduction circuit and the reset circuit each comprise at least one of the first thin film transistors.
5. A gate driver circuit according to claim 3, wherein at least one of the input circuit, the output circuit, the noise reduction circuit, and the reset circuit includes at least one set of the first thin film transistor and the second thin film transistor arranged to overlap.
6. The gate driving circuit of claim 3, wherein the input circuit comprises a switch unit M1, a first terminal and a control terminal of the switch unit M1 are respectively connected to the signal input terminals, and a second terminal of the switch unit M1 is connected to the pull-up node;
the output circuit comprises a switch unit M3 and a capacitor C1; a first terminal of the switch unit M3 is connected to a first clock signal input terminal, a control terminal of the switch unit M3 is connected to the pull-up node, a second terminal of the switch unit M3 is connected to a signal output terminal, a first terminal of the capacitor C1 is connected to the pull-up node, and a second terminal of the capacitor C1 is connected to the signal output terminal;
the noise reduction circuit comprises a switch unit M5, a switch unit M6, a switch unit M8, a switch unit M9 and a switch unit M10; a first terminal and a control terminal of the switch unit M9 are respectively connected to a second clock signal input terminal, and a second terminal of the switch unit M9 is connected to a first pull-down node; a first terminal of the switch unit M5 is connected to the second clock signal input terminal, a control terminal of the switch unit M5 is connected to the first pull-down node, and a second terminal of the switch unit M5 is connected to the second pull-down node; control terminals of the switch unit M8 and the switch unit M6 are connected to the pull-up node, a first terminal of the switch unit M8 is connected to the first pull-down node, and a first terminal of the switch unit M6 is connected to the second pull-down node; a control terminal of the switch unit M10 is connected to the second pull-down node, and a first terminal of the switch unit M10 is connected to the pull-up node; second ends of the switch unit M6, the switch unit M8 and the switch unit M10 are connected with a constant voltage signal input end;
the reset circuit comprises a switch unit M2 and a switch unit M11; a control terminal of the switch unit M2 is connected to a reset signal input terminal, a first terminal of the switch unit M2 is connected to the pull-up node, and a second terminal of the switch unit M2 is connected to the constant voltage signal input terminal; the control end of the switch unit M11 is connected to the second pull-down node, the first end of the switch unit M11 is connected to the signal output end, and the second end of the switch unit M11 is connected to the constant voltage signal input end.
7. A gate drive circuit according to claim 6, wherein at least one of the switch unit M1, the switch unit M3, the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2 and the switch unit M11 is the first thin film transistor and the rest is the second thin film transistor, and a forward projection of at least one switch unit provided as the first thin film transistor on the substrate and a forward projection of at least one switch unit provided as the second thin film transistor on the substrate at least partially overlap.
8. A gate drive circuit as claimed in claim 6, wherein the switch unit M1 and the switch unit M3 are both the second thin film transistor; the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9, the switch unit M10, the switch unit M2, and the switch unit M11 are all the first thin film transistors.
9. A gate drive circuit according to claim 6, wherein at least one of the switch unit M5, the switch unit M6, the switch unit M8, the switch unit M9 and the switch unit M10 is the second thin film transistor and the rest are the first thin film transistor; and/or the presence of a gas in the gas,
one of the switch unit M2 and the switch unit M11 is the second thin film transistor and the other is the first thin film transistor, and an orthographic projection of the switch unit M2 on the substrate at least partially overlaps with an orthographic projection of the switch unit M11 on the substrate.
10. A gate driver circuit according to claim 1, wherein the active layer of the second thin film transistor comprises a stack of metal oxide semiconductors, and the active layer of the first thin film transistor is a single layer of metal oxide semiconductor.
11. A gate drive circuit according to claim 1, wherein at least one of the first thin film transistors and/or at least one of the second thin film transistors is a double gate transistor.
12. A display device comprising the gate driver circuit according to any one of claims 1 to 11.
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