CN113871461B - Superlattice VLSI - Google Patents

Abstract

The invention provides a superlattice ultra-large-scale integrated circuit, which includes: a substrate; a transition layer, which is arranged above the substrate; and a component layer, which is arranged above the transition layer. The component layer is based on supercrystalline Superlattice integrated circuits can be constructed by designing devices based on the special properties of two-dimensional electron gas and two-dimensional hole gas in lattice integrated circuits. Above the transition layer, devices designed based on the special properties of the two-dimensional electron gas and two-dimensional hole gas of the superlattice integrated circuit are used to construct the superlattice integrated circuit, and the design is called a superlattice ultra-large-scale integrated circuit (MDMFSL‑ULSI:Multi ‑Dimension Multi‑Functional Superlattice Ultra‑Large Scale Integrated Circuit) is based on two-dimensional electron gas and two-dimensional hole gas superlattice and quantum well and has the characteristics of ultra-high speed, high reliability, radiation resistance, high and low temperature resistance, and design efficiency High, short manufacturing process cycle and low cost will greatly improve the above shortcomings of traditional silicon and compound integrated circuits.

Description

Superlattice VLSI

Technical field

The present invention relates to the technical field of integrated circuits, and in particular to a superlattice ultra-large-scale integrated circuit.

Background technique

At present, very large-scale integrated circuit components and processes based on silicon materials are approaching the quantum limit. Not only are device performance limited, but the manufacturing process is also very complex and expensive. The rapidly developing big data, artificial intelligence and comprehensive digital intelligence markets are in urgent need of new VLSI circuits with high reliability and acceptable cost. What's more important is that silicon VLSI components have become increasingly difficult to meet the special requirements of artificial intelligence and the space age for ultra-high speed, high and low temperature resistance, and radiation resistance.

Contents of the invention

The invention provides a superlattice ultra-large scale integrated circuit (MDMFSL-ULSI: Multi-DimensionMulti-Functional Superlattice Ultra-Large Scale Integrated Circuit) which is based on two-dimensional electron gas and two-dimensional hole gas superlattice and quantum wells. It has the characteristics of ultra-high speed, high reliability, radiation resistance and high and low temperature resistance, high design efficiency, short manufacturing process cycle and low cost, which will greatly improve the above shortcomings of traditional silicon and compound integrated circuits.

The invention provides a superlattice ultra-large-scale integrated circuit, which includes:

substrate;

a transition layer disposed above the substrate;

The component layer is arranged above the transition layer. The component layer is a device designed based on the special properties of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit to construct the superlattice integrated circuit. Among them, the component layer can be constructed with either a homogeneous superlattice layer, such as intrinsic gallium nitride (GaN), N-type gallium nitride (GaN), P-type gallium nitride (GaN), etc., or a heterogeneous superlattice layer. Lattice layer structure, such as intrinsic gallium aluminum nitride Ga(x)Al(1-x)N, N-type gallium aluminum nitride Ga(x)Al(1-x)N, P-type gallium aluminum nitride Ga( x)Al(1-x)N etc.

In one embodiment, the substrate is silicon, germanium or a compound semiconductor.

In one embodiment, the transition layer uses one of silicon dioxide, silicon nitride, and a compound semiconductor layer.

In one embodiment, the component layer is a superlattice integrated circuit constructed using devices designed based on the special properties of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit.

In one embodiment, devices designed based on the special properties of two-dimensional electron gas and two-dimensional hole gas in superlattice integrated circuits include P-type superlattice field-effect transistors, N-type superlattice field-effect transistors, and NPN-type superlattice field-effect transistors. One or Various combinations.

In one embodiment, a plurality of through holes are evenly distributed on the bottom of the substrate.

The multi-dimensional structure of the superlattice VLSI circuit will isolate each special functional block with a channel insulating layer according to the needs of device performance and use special processes (such as ion implantation and rapid high-temperature thermal annealing) to form multiple carriers (electron or hole) channel.

In one embodiment, the N-type superlattice field effect transistor includes:

A first superlattice intrinsic layer is provided above the transition layer;

A superlattice N-type layer disposed above the first superlattice intrinsic layer;

A second superlattice intrinsic layer is disposed above the superlattice N-type layer;

A first superlattice P-type layer is disposed above the second superlattice intrinsic layer;

A first gate insulating layer disposed above the first superlattice P-type layer;

The first N+ conductive layer penetrates from the upper surface of the first superlattice P-type layer and downward to the first superlattice intrinsic layer in a direction perpendicular to the first superlattice P-type layer. the lower surface;

The first channel insulating layer is annular, penetrating from the upper surface of the first superlattice P-type layer and downward to the first superlattice P-type layer in a direction perpendicular to the first superlattice P-type layer. The lower surface of the lattice intrinsic layer, the first N+ conductive layer is disposed in the first channel insulating layer;

A first ohmic contact layer disposed above the first N+ conductive layer and in contact with the first N+ conductive layer;

a second ohmic contact layer disposed above the first gate insulating layer and in contact with the first gate insulating layer,

A first dielectric protective layer disposed between the first ohmic contact layer and the second ohmic contact layer;

A second dielectric protective layer is provided outside the first ohmic contact layer.

The above device structure is only a simple combination among various combinations of N-type superlattice field effect transistors.

In one embodiment, a P-type superlattice field effect transistor includes:

A third superlattice intrinsic layer is provided above the transition layer;

A superlattice P-type layer disposed above the third superlattice intrinsic layer;

A fourth superlattice intrinsic layer is provided above the superlattice P-type layer;

The first superlattice N-type layer is disposed above the fourth superlattice intrinsic layer;

A second gate insulating layer disposed above the first superlattice N-type layer;

The first P+ conductive layer penetrates from the upper surface of the first superlattice N-type layer downward to the third superlattice intrinsic layer in a direction perpendicular to the first superlattice N-type layer. the lower surface;

The second channel insulating layer has the shape required for device isolation, including: rectangular, ring, and other closed shapes. From the upper surface of the first superlattice N-type layer and downward in a direction perpendicular to the first superlattice N-type layer to the lower surface of the third superlattice intrinsic layer, the The first P+ conductive layer is disposed in the second channel insulating layer;

A third ohmic contact layer is disposed above the first P+ conductive layer and in contact with the first P+ conductive layer;

a fourth ohmic contact layer disposed above the second gate insulating layer and in contact with the second gate insulating layer,

A third dielectric protective layer disposed between the third ohmic contact layer and the fourth ohmic contact layer;

A fourth dielectric protective layer is provided outside the third ohmic contact layer.

The above device structure is only a simple combination among the various combinations of P-type superlattice field effect transistors.

In one embodiment, PNP superlattice bipolar transistors are divided into superlattice planar P-N-P bipolar transistors and superlattice vertical P-N-P bipolar transistors;

Among them, superlattice vertical P-N-P bipolar transistors include:

A superlattice collector P-type layer is provided above the transition layer;

A superlattice base N-type layer is arranged above the superlattice collector P-type layer;

A superlattice emitter P-type layer is arranged above the superlattice base N-type layer;

The second P+ conductive layer and the second N+ conductive layer penetrate from the upper surface of the superlattice emitter P-type layer and downward to the superlattice emitter P-type layer in a direction perpendicular to the superlattice emitter P-type layer. The lower surface of the P-type layer of the grid collector;

The third channel insulating layer has the shape required for device isolation, such as rectangle, ring, etc.; from the upper surface of the superlattice emitter P-type layer to the direction perpendicular to the superlattice emitter P-type layer The direction penetrates downward to the lower surface of the P-type layer of the superlattice collector, and the second P+ conductive layer and the second N+ conductive layer are provided in the third channel insulating layer;

A fifth ohmic contact layer is disposed above the second P+ conductive layer and in contact with the second P+ conductive layer;

a sixth ohmic contact layer disposed above the second N+ conductive layer and in contact with the second N+ conductive layer;

a seventh ohmic contact layer disposed above the superlattice emitter P-type layer and in contact with the superlattice emitter P-type layer,

A fifth dielectric protective layer, disposed between the seventh ohmic contact layer and the fifth ohmic contact layer, and the seventh ohmic contact layer and the sixth ohmic contact layer;

A sixth dielectric protective layer is provided outside the fifth ohmic contact layer and the sixth ohmic contact layer.

A seventh dielectric protective layer, disposed between the superlattice emitter P-type layer and the second N+ conductive layer, the superlattice emitter P-type layer and the second P+ conductive layer;

Among them, superlattice planar P-N-P bipolar transistors include:

Superlattice planar P-N-P bipolar transistors include:

The superlattice emitter P-type region is cylindrical and is arranged above the transition layer;

The superlattice base N-type region 46 is annular, arranged above the transition layer and sleeved outside the superlattice emitter P-type region;

The superlattice collector P-type region is annular, arranged above the transition layer and nested outside the superlattice base N-type region 46;

The fourth channel insulating layer is annular and is arranged outside the P-type region of the superlattice base, and the fourth channel insulating layer is arranged above the transition layer or is arranged on the transition layer. above the transition layer and embedded in the substrate after passing through the transition layer;

The eighth ohmic contact layer is circular, disposed above the P-type region of the superlattice emitter and in contact with the P-type region of the superlattice emitter;

The ninth ohmic contact layer is annular and is disposed above the superlattice base N-type region 46 and in contact with the superlattice base N-type region 46;

The tenth ohmic contact layer is annular, disposed above the P-type region of the superlattice collector and in contact with the P-type region of the superlattice collector;

An eighth dielectric protective layer is annular and is provided between the eighth ohmic contact layer and the ninth ohmic contact layer;

A ninth dielectric protective layer is annular and is provided between the ninth ohmic contact layer and the tenth ohmic contact layer;

The tenth dielectric protection layer is annular and is disposed outside the tenth ohmic contact layer.

In one embodiment, NPN superlattice bipolar transistors are divided into superlattice vertical N-P-N bipolar transistors and superlattice planar N-P-N bipolar transistors;

Among them, superlattice vertical N-P-N bipolar transistors include:

A superlattice collector N-type layer is provided above the transition layer;

A superlattice base P-type layer is arranged above the superlattice collector N-type layer;

A superlattice emitter N-type layer is arranged above the superlattice base P-type layer;

The third P+ conductive layer and the third N+ conductive layer penetrate from the upper surface of the superlattice emitter N-type layer and downward to the superlattice emitter N-type layer in a direction perpendicular to the superlattice emitter N-type layer. The lower surface of the N-type layer of the grid collector;

The fifth channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the superlattice emitter N-type layer to the direction perpendicular to the superlattice emitter N-type layer. The direction penetrates downward to the lower surface of the N-type layer of the superlattice collector, and the third P+ conductive layer and the third N+ conductive layer are provided in the fifth channel insulating layer;

An eleventh ohmic contact layer is disposed above the third P+ conductive layer and in contact with the third P+ conductive layer;

A twelfth ohmic contact layer, disposed above the third N+ conductive layer and in contact with the third N+ conductive layer;

a thirteenth ohmic contact layer, disposed above the superlattice emitter N-type layer and in contact with the superlattice emitter N-type layer,

An eleventh dielectric protective layer is provided between the thirteenth ohmic contact layer and the eleventh ohmic contact layer, and between the thirteenth ohmic contact layer and the twelfth ohmic contact layer;

A twelfth dielectric protective layer is provided outside the eleventh ohmic contact layer and the twelfth ohmic contact layer.

A thirteenth dielectric protective layer, disposed between the superlattice emitter N-type layer and the third N+ conductive layer, the superlattice emitter N-type layer and the third P+ conductive layer;

Among them, superlattice planar N-P-N bipolar transistors include:

The superlattice emitter N-type region is cylindrical and is arranged above the transition layer;

The superlattice base P-type region is annular, arranged above the transition layer and nested outside the superlattice emitter N-type region;

The superlattice collector N-type region is annular, arranged above the transition layer and nested outside the superlattice base P-type region;

The sixth channel insulating layer is annular and is arranged outside the N-type region of the superlattice collector, and the sixth channel insulating layer is arranged above the transition layer or is arranged on the transition layer. above the transition layer and embedded in the substrate after passing through the transition layer;

The fourteenth ohmic contact layer is circular, disposed above the N-type region of the superlattice emitter and in contact with the N-type region of the superlattice emitter;

The fifteenth ohmic contact layer is annular, disposed above the P-type region of the superlattice base and in contact with the P-type region of the superlattice base;

The sixteenth ohmic contact layer is annular, disposed above the N-type region of the superlattice collector and in contact with the N-type region of the superlattice collector;

A fourteenth dielectric protective layer is annular and is provided between the fourteenth ohmic contact layer and the fifteenth ohmic contact layer;

A fifteenth dielectric protective layer is annular and is disposed between the fifteenth ohmic contact layer and the sixteenth ohmic contact layer;

A sixteenth dielectric protective layer is annular and is disposed outside the sixteenth ohmic contact layer.

In one embodiment, the superlattice capacitor and varactor include:

A fifth superlattice intrinsic layer is provided above the transition layer;

The second superlattice P-type layer is disposed above the fifth superlattice intrinsic layer;

A sixth superlattice intrinsic layer is provided above the second superlattice P-type layer;

The first superlattice low-resistance N-type layer is disposed above the sixth superlattice intrinsic layer;

The fourth P+ conductive layer and the fourth N+ conductive layer penetrate from the upper surface of the first superlattice low-resistance N-type layer and downward in a direction perpendicular to the first superlattice low-resistance N-type layer. The lower surface of the fifth superlattice intrinsic layer;

The seventh channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the first superlattice low-resistance N-type layer to perpendicular to the first superlattice low-resistance The direction of the N-type layer penetrates downward to the lower surface of the fifth superlattice intrinsic layer, and the fourth P+ conductive layer and the fourth N+ conductive layer are provided in the seventh channel insulating layer;

A seventeenth ohmic contact layer, disposed above the first superlattice low-resistance N-type layer and in contact with the first superlattice low-resistance N-type layer;

An eighteenth ohmic contact layer, disposed above the fourth N+ conductive layer and in contact with the fourth N+ conductive layer;

A nineteenth ohmic contact layer is disposed above the fourth P+ conductive layer and in contact with the fourth P+ conductive layer;

A seventeenth dielectric protective layer is provided between the seventeenth ohmic contact layer and the eighteenth ohmic contact layer, the seventeenth ohmic contact layer and the nineteenth ohmic contact layer;

An eighteenth dielectric protective layer is provided outside the eighteenth ohmic contact layer and the nineteenth ohmic contact layer.

In one embodiment, the superlattice resistor and varistor include:

A seventh superlattice intrinsic layer is provided above the transition layer;

A third superlattice P-type layer is provided above the seventh superlattice intrinsic layer;

The eighth superlattice intrinsic layer is provided above the third superlattice P-type layer;

The second superlattice low-resistance N-type layer is disposed above the eighth superlattice intrinsic layer;

The fifth P+ conductive layer and the fifth N+ conductive layer penetrate from the upper surface of the second superlattice low-resistance N-type layer and downward to the direction perpendicular to the second superlattice low-resistance N-type layer. The lower surface of the seventh superlattice intrinsic layer;

The eighth channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the second superlattice low-resistance N-type layer to perpendicular to the second superlattice low-resistance The direction of the N-type layer penetrates downward to the lower surface of the seventh superlattice intrinsic layer, and the fifth P+ conductive layer and the fifth N+ conductive layer are provided in the eighth channel insulating layer;

A 20th ohm contact layer, a 21st ohm contact layer and a 22nd ohm contact layer are one group, and there are two groups in total;

A twentieth ohmic contact layer is disposed above the second superlattice low-resistance N-type layer and in contact with the second superlattice low-resistance N-type layer;

A twenty-first ohmic contact layer is disposed above the fifth N+ conductive layer and in contact with the fifth N+ conductive layer;

A twenty-second ohmic contact layer is disposed above the fifth P+ conductive layer and in contact with the fifth P+ conductive layer;

A nineteenth dielectric protective layer is provided between the twentieth ohmic contact layer and the twenty-first ohmic contact layer, the twentieth ohmic contact layer and the twenty-second ohmic contact layer;

The twentieth dielectric protective layer is provided outside the twenty-first ohmic contact layer and the twenty-second ohmic contact layer.

In one embodiment, the superlattice inductor and inductor include:

A ninth superlattice intrinsic layer is provided above the transition layer;

A fourth superlattice P-type layer is provided above the ninth superlattice intrinsic layer;

The tenth superlattice intrinsic layer is provided above the fourth superlattice P-type layer;

The third superlattice low-resistance N-type layer is provided above the tenth superlattice intrinsic layer;

The sixth P+ conductive layer and the sixth N+ conductive layer penetrate from the upper surface of the third superlattice low-resistance N-type layer and downward in a direction perpendicular to the third superlattice low-resistance N-type layer. The lower surface of the ninth superlattice intrinsic layer;

The ninth channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the third superlattice low-resistance N-type layer to perpendicular to the third superlattice low-resistance The direction of the N-type layer penetrates downward to the lower surface of the ninth superlattice intrinsic layer, and the sixth P+ conductive layer and the sixth N+ conductive layer are provided in the ninth channel insulating layer;

A 23rd ohm contact layer, a 24th ohm contact layer and a 25th ohm contact layer are one group, and there are two groups in total;

A twenty-third ohmic contact layer is disposed above the third superlattice low-resistance N-type layer and in contact with the third superlattice low-resistance N-type layer;

A twenty-fourth ohmic contact layer is disposed above the sixth N+ conductive layer and in contact with the sixth N+ conductive layer;

A twenty-fifth ohmic contact layer is disposed above the sixth P+ conductive layer and in contact with the sixth P+ conductive layer;

A twenty-first dielectric protective layer is provided between the twenty-third ohmic contact layer and the twenty-fourth ohmic contact layer, and between the twenty-third ohmic contact layer and the twenty-fourth ohmic contact layer;

A twenty-second dielectric protective layer is provided outside the twenty-fourth ohmic contact layer and the twenty-fifth ohmic contact layer.

In one embodiment, the superlattice flash memory includes: a doped P-channel n-i-p-i superlattice field-effect ferroelectric transistor or a doped N-channel n-i-p-i superlattice field-effect ferroelectric transistor;

Among them, P-channel n-i-p-i superlattice field effect ferroelectric transistors include:

The eleventh superlattice intrinsic layer is provided above the transition layer;

A superlattice low-resistance P-type layer, arranged above the eleventh superlattice intrinsic layer;

A twelfth superlattice intrinsic layer is provided above the superlattice low-resistance P-type layer;

A second superlattice N-type layer is provided above the twelfth superlattice intrinsic layer;

A first ferroelectric thin film layer disposed above the second superlattice N-type layer;

The seventh P+ conductive layer penetrates from the upper surface of the second superlattice N-type layer and downwards in a direction perpendicular to the second superlattice N-type layer to the eleventh superlattice intrinsic the lower surface of the layer;

The tenth channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the second superlattice N-type layer to the direction perpendicular to the second superlattice N-type layer. The direction penetrates downward to the lower surface of the eleventh superlattice intrinsic layer, and the seventh P+ conductive layer is provided in the tenth channel insulating layer;

A twenty-sixth ohmic contact layer is disposed above the first ferroelectric thin film layer and in contact with the first ferroelectric thin film layer,

A twenty-seventh ohmic contact layer is disposed above the seventh P+ conductive layer and in contact with the seventh P+ conductive layer;

A twenty-third dielectric protective layer is provided between the twenty-sixth ohmic contact layer and the twenty-seventh ohmic contact layer;

A twenty-fourth dielectric protective layer is provided outside the twenty-seventh ohmic contact layer;

Among them, N-channel n-i-p-i superlattice field effect ferroelectric transistors include:

The thirteenth superlattice intrinsic layer is provided above the transition layer;

A superlattice low-resistance N-type layer, arranged above the thirteenth superlattice intrinsic layer;

A fourteenth superlattice intrinsic layer, arranged above the superlattice low-resistance N-type layer;

The fifth superlattice P-type layer is provided above the fourteenth superlattice intrinsic layer;

A second ferroelectric thin film layer is disposed above the fifth superlattice P-type layer;

The seventh N+ conductive layer penetrates from the upper surface of the fifth superlattice P-type layer and downwards in a direction perpendicular to the fifth superlattice P-type layer to the thirteenth superlattice intrinsic the lower surface of the layer;

The eleventh channel insulating layer has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the fifth superlattice P-type layer to perpendicular to the fifth superlattice P-type layer. The direction penetrates downward to the lower surface of the thirteenth superlattice intrinsic layer, and the seventh N+ conductive layer is provided in the eleventh channel insulating layer;

A twenty-eighth ohmic contact layer, disposed above the second ferroelectric thin film layer and in contact with the second ferroelectric thin film layer,

The twenty-ninth ohmic contact layer is disposed above the seventh N+ conductive layer and in contact with the seventh N+ conductive layer;

A twenty-fifth dielectric protective layer is provided between the twenty-eighth ohmic contact layer and the twenty-ninth ohmic contact layer;

A twenty-sixth dielectric protective layer is provided outside the twenty-ninth ohmic contact layer.

This superlattice VLSI circuit has the following advantages:

1. Ultra-high speed: 10 to hundreds of times faster than conventional large-scale integrated circuits. Up to the terahertz (THz) range.

2. Can make full use of various field effect transistors, bipolar transistors (vertical and planar) and special functional devices, such as: superlattice flash memory, superlattice capacitors and varactor, superlattice resistors and rheostat and super Integrated circuits with different designs such as lattice inductors and inductors.

3. High reliability: High and low temperature resistance and radiation resistance are much better than traditional silicon and compound integrated circuits.

4. Design flexibility: Utilizing the special properties and special devices of the two-dimensional electron gas and two-dimensional hole gas of superlattice integrated circuits, various integrated circuits can be designed and manufactured, such as linear integrated circuits, analog integrated circuits, and linear and analog hybrids. Integrated circuits, central processing units (CPUs), etc.

5. Simplified process, short production cycle, and reasonable cost: Because the special properties of the two-dimensional electron gas and two-dimensional hole gas of superlattice integrated circuits are used to design integrated circuit components required for industrial applications, the process steps can be greatly simplified. , for example, the number of photolithography templates and corresponding process steps can be reduced by 30%, so that the production cycle and cost can be greatly optimized.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and examples.

Description of drawings

The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention. In the attached picture:

Figure 1 is a schematic diagram of a superlattice VLSI circuit in an embodiment of the present invention;

Figure 2 is a schematic cross-sectional view of an N-type superlattice field effect transistor in an embodiment of the present invention;

Figure 3 is a schematic cross-sectional view of a P-type superlattice field effect transistor in an embodiment of the present invention;

Figure 4 is a schematic cross-sectional view of a superlattice vertical P-N-P bipolar transistor in an embodiment of the present invention;

Figure 5 is a schematic cross-sectional view of a superlattice planar P-N-P bipolar transistor in an embodiment of the present invention;

Figure 6 is a top view of a superlattice planar P-N-P bipolar transistor in an embodiment of the present invention;

Figure 7 is a schematic cross-sectional view of a superlattice vertical N-P-N bipolar transistor in an embodiment of the present invention;

Figure 8 is a schematic cross-sectional view of a superlattice planar N-P-N bipolar transistor in an embodiment of the present invention;

Figure 9 is a top view of a superlattice planar N-P-N bipolar transistor in an embodiment of the present invention;

Figure 10 is a schematic cross-sectional view of a superlattice capacitor and a varactor in an embodiment of the present invention;

Figure 11 is a schematic cross-sectional view of a superlattice resistor and a varistor in an embodiment of the present invention;

Figure 12 is a top view of a superlattice resistor and a varistor in an embodiment of the present invention;

Figure 13 is a schematic cross-sectional view of a superlattice inductor and transformer in an embodiment of the present invention;

Figure 14 is a top view of a superlattice inductor and transformer in an embodiment of the present invention;

Figure 15 is a schematic cross-sectional view of a P-channel n-i-p-i superlattice field effect ferroelectric transistor in an embodiment of the present invention;

Figure 16 is a schematic cross-sectional view of an N-channel n-i-p-i superlattice field effect ferroelectric transistor in an embodiment of the present invention;

Figure 17 is a schematic diagram of an autonomous cooling insulation layer in an embodiment of the present invention.

Figure 18 is a schematic diagram of an isolation insulating layer in an embodiment of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

Embodiments of the present invention provide a superlattice VLSI circuit, as shown in Figure 1, including:

substrate1;

Transition layer 2, arranged above the substrate 1;

The component layer 3 is provided above the transition layer 2. The component layer 3 is a device designed based on the special properties of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit to construct the superlattice integrated circuit.

The working principle and beneficial effects of the above-mentioned superlattice VLSI circuit:

Above the transition layer, devices designed based on the special properties of the two-dimensional electron gas and two-dimensional hole gas of the superlattice integrated circuit are used to construct a superlattice integrated circuit, and the design is a superlattice ultra-large-scale integrated circuit (MDMFSL-ULSI: Multi -Dimension Multi-Functional Superlattice Ultra-Large Scale Integrated Circuit) is based on two-dimensional electron gas and two-dimensional hole gas superlattice and quantum well and has the characteristics of high speed, high reliability, radiation resistance, high and low temperature resistance, and high design efficiency , the manufacturing process cycle is short and the cost is low, which will greatly improve the above shortcomings of traditional silicon and compound integrated circuits.

In one embodiment, the substrate is silicon or germanium or a compound semiconductor.

In one embodiment, the transition layer uses one of silicon dioxide, silicon nitride, and a compound semiconductor layer.

In order to realize the component layer to form a superlattice VLSI circuit, in one embodiment, the device designed based on the special properties of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit includes P-type superlattice field effect Transistors, N-type superlattice field effect transistors, NPN-type superlattice bipolar transistors, PNP-type superlattice bipolar transistors, superlattice flash memories, superlattice capacitors and varactors, superlattice resistors and varistors, and Superlattice inductors are combined with one or more types of transformers.

In order to dissipate heat more quickly, in one embodiment, a plurality of through holes are evenly distributed on the bottom of the substrate. Through the densely distributed small holes, the heat generated by the circuit operation is dissipated faster.

In one embodiment, as shown in Figure 2, the N-type superlattice field effect transistor includes:

The first superlattice intrinsic layer 11 is provided above the transition layer 2;

Superlattice N-type layer 12 is provided above the first superlattice intrinsic layer 11;

The second superlattice intrinsic layer 13 is provided above the superlattice N-type layer 12;

The first superlattice P-type layer 14 is provided above the second superlattice intrinsic layer 13;

The first gate insulating layer 15 is provided above the first superlattice P-type layer 14;

The first N+ conductive layer 20 penetrates from the upper surface of the first superlattice P-type layer 14 downward to the first superlattice in a direction perpendicular to the first superlattice P-type layer 14 The lower surface of the intrinsic layer 11;

The first channel insulating layer 19 has a shape required for device isolation, such as rectangular, annular, etc., extending from the upper surface of the first superlattice P-type layer 14 to perpendicular to the first superlattice P-type layer 14 . The direction of layer 14 penetrates downward to the lower surface of the first superlattice intrinsic layer 11, and the first N+ conductive layer 20 is disposed inside the first channel insulating layer 19;

The first ohmic contact layer 18 is disposed above the first N+ conductive layer 20 and in contact with the first N+ conductive layer 20;

The second ohmic contact layer 17 is disposed above the first gate insulating layer 15 and in contact with the first gate insulating layer 15,

A first dielectric protective layer 16 is provided between the first ohmic contact layer 18 and the second ohmic contact layer 17;

The second dielectric protective layer 21 is provided outside the first ohmic contact layer 18 .

Wherein, the first N+ conductive layer can be arranged in the shape of an annular strip or can be arranged in two or more independent N+ conductive layers of other shapes; when the first N+ conductive layer is in the shape of an annular strip, the first ohmic contact layer It can be set in an annular strip shape simultaneously, or it can be set as two or more independent N+ conductive layers of other shapes.

The principles and beneficial effects of the above-mentioned N-type superlattice field effect transistor are:

The N-type superlattice field effect transistor consists of a doped superlattice intrinsic layer (first superlattice intrinsic layer), a doped superlattice N-type layer (superlattice N-type layer), and a supercrystalline It consists of the intrinsic layer of the lattice (the second superlattice intrinsic layer), the P-type layer of the doped superlattice (the first superlattice P-type layer), the first N+ conductive layer, etc. In order to meet the performance requirements of integrated circuits, more layers of repeating structures can be designed, such as p-i-n-i-p-i-n-i-p-i. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different forbidden band widths to form special quantum wells to improve device performance. The P+ conductive layer is formed using low-energy ion implantation technology, and the ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, titanium-aluminum alloy can generally be used. ,wait. The gate insulating layer can be silicon nitride or the like. The devices need to be isolated by an insulating layer (first channel insulating layer). The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figure 3, the P-type superlattice field effect transistor includes:

The third superlattice intrinsic layer 22 is provided above the transition layer 2;

Superlattice P-type layer 23 is provided above the third superlattice intrinsic layer 22;

The fourth superlattice intrinsic layer 24 is provided above the superlattice P-type layer 23;

The first superlattice N-type layer 25 is provided above the fourth superlattice intrinsic layer 24;

The second gate insulating layer 26 is provided above the first superlattice N-type layer 25;

The first P+ conductive layer 27 penetrates from the upper surface of the first superlattice N-type layer 25 downward to the third superlattice in a direction perpendicular to the first superlattice N-type layer 25 the lower surface of intrinsic layer 22;

The second channel insulating layer 28 is rectangular or annular, penetrating downward from the upper surface of the first superlattice N-type layer 25 to the direction perpendicular to the first superlattice N-type layer 25 . On the lower surface of the third superlattice intrinsic layer 22, the first P+ conductive layer 27 is provided in the second channel insulating layer 28;

The third ohmic contact layer 30 is disposed above the first P+ conductive layer 27 and in contact with the first P+ conductive layer 27;

The fourth ohmic contact layer 32 is disposed above the second gate insulating layer 26 and in contact with the second gate insulating layer 26,

A third dielectric protective layer 31 is provided between the third ohmic contact layer 30 and the fourth ohmic contact layer 32;

The fourth dielectric protection layer 29 is provided outside the third ohmic contact layer 30 .

The principles and beneficial effects of the above-mentioned P-type superlattice field effect transistor are:

It consists of a doped superlattice intrinsic layer (the third superlattice intrinsic layer), a doped superlattice P-type layer (superlattice P-type layer), and a superlattice intrinsic layer (the fourth superlattice intrinsic layer). It consists of the lattice intrinsic layer), the doped superlattice N-type layer (the first superlattice N-type layer), the first P+ conductive layer, etc. In order to meet the performance requirements of integrated circuits, more layers of repeating structures can be designed, such as n-i-p-i--n-i-p-i-n-i. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve devices performance. The P+ conductive layer is formed using low-energy ion implantation technology, and the ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, titanium-aluminum alloy can generally be used. wait. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process, ion sputtering deposition of insulating material, and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

PNP superlattice bipolar transistors are divided into superlattice planar P-N-P bipolar transistors and superlattice vertical P-N-P bipolar transistors. NPN superlattice bipolar transistors are divided into superlattice vertical N-P-N bipolar transistors and superlattice vertical N-P-N bipolar transistors. Superlattice planar N-P-N bipolar transistor.

As shown in Figure 4, superlattice vertical P-N-P bipolar transistors include:

Superlattice collector P-type layer 33 is provided above the transition layer 2;

The superlattice base N-type layer 34 is provided above the superlattice collector P-type layer 33;

The superlattice emitter P-type layer 35 is provided above the superlattice base N-type layer 34;

The second P+ conductive layer 37 and the second N+ conductive layer 36 penetrate from the upper surface of the superlattice emitter P-type layer 35 and downward in a direction perpendicular to the superlattice emitter P-type layer 35. The lower surface of the superlattice collector P-type layer 33;

The third channel insulating layer 38 is rectangular or annular, penetrating from the upper surface of the superlattice emitter P-type layer 35 downward to the direction perpendicular to the superlattice emitter P-type layer 35 . On the lower surface of the superlattice collector P-type layer 33, the second P+ conductive layer 37 and the second N+ conductive layer 36 are provided in the third channel insulating layer 38;

The fifth ohmic contact layer 39 is disposed above the second P+ conductive layer 37 and in contact with the second P+ conductive layer 3;

The sixth ohmic contact layer 40 is disposed above the second N+ conductive layer 36 and in contact with the second N+ conductive layer 36;

The seventh ohmic contact layer 41 is disposed above the superlattice emitter P-type layer 35 and in contact with the superlattice emitter P-type layer 35,

The fifth dielectric protective layer 42 is disposed between the seventh ohmic contact layer 41 and the fifth ohmic contact layer 39, and the seventh ohmic contact layer 41 and the sixth ohmic contact layer 40;

The sixth dielectric protective layer 43 is provided outside the fifth ohmic contact layer 39 and the sixth ohmic contact layer 40 .

The seventh dielectric protective layer 44 is provided on the superlattice emitter P-type layer 35 and the second N+ conductive layer 36, the superlattice emitter P-type layer 35 and the second P+ conductive layer. between 37.

The superlattice vertical P-N-P bipolar transistor consists of a superlattice-doped collector P-type layer (superlattice collector P-type layer) and a superlattice-doped base N-type layer (superlattice base N-type layer). Type layer), a doped superlattice emitter P-type layer (superlattice emitter P-type layer), a second P+ conductive layer and a second N+ conductive layer. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as p-i-n-i-p. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve device performance. N+ and P+ conductive layers are formed using low-energy ion implantation technology. The ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, it is generally available. Titanium aluminum alloy, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figures 5 and 6, superlattice planar P-N-P bipolar transistors include:

The superlattice emitter P-type region 45 is cylindrical and is arranged above the transition layer;

The superlattice base N-type region 46 is annular, arranged above the transition layer and sleeved outside the superlattice emitter P-type region 45;

The superlattice collector P-type region 47 is annular, arranged above the transition layer and sleeved outside the superlattice base N-type region 46;

The fourth channel insulating layer 48 is annular and is arranged outside the P-type region of the superlattice base, and the fourth channel insulating layer 48 is arranged above the transition layer or on the embedded in the substrate above and through the transition layer;

The eighth ohmic contact layer 49 is circular, disposed above the superlattice emitter P-type region 45 and in contact with the superlattice emitter P-type region 45;

The ninth ohmic contact layer 51 is annular and is disposed above the superlattice base N-type region 46 and in contact with the superlattice base N-type region 46;

The tenth ohmic contact layer 53 is annular and is disposed above the superlattice collector P-type region 47 and in contact with the superlattice collector P-type region 47;

The eighth dielectric protective layer 50 is annular and is disposed between the eighth ohmic contact layer 49 and the ninth ohmic contact layer 51;

The ninth dielectric protective layer 52 is annular and is disposed between the ninth ohmic contact layer 51 and the tenth ohmic contact layer 53;

The tenth dielectric protection layer 54 is annular and is disposed outside the tenth ohmic contact layer 53 .

The superlattice planar P-N-P bipolar transistor consists of a superlattice-doped collector P-type region (superlattice collector P-type region) and a superlattice-doped base N-type region (superlattice base N-type region). Type region 46), P-type region doped with superlattice emitter (superlattice emitter P-type region), P-type and N-type ohmic contact layers, etc. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as p-i-n-i-p. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different forbidden band widths to form special quantum wells to improve device performance. Low-energy ion implantation technology is used to form the superlattice collector P-type region, the doped superlattice base N-type region 46, the doped superlattice emitter P-type region, and the like. The ohmic electrode is formed by plasma sputtering technology, but the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, titanium-aluminum alloy can generally be used, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figure 7, superlattice vertical N-P-N bipolar transistors include:

Superlattice collector N-type layer 65 is provided above the transition layer 2;

The superlattice base P-type layer 66 is disposed above the superlattice collector N-type layer 65;

The superlattice emitter N-type layer 67 is provided above the superlattice base P-type layer 66;

The third P+ conductive layer 68 and the third N+ conductive layer 69 penetrate from the upper surface of the superlattice emitter N-type layer 67 and downward in a direction perpendicular to the superlattice emitter N-type layer 67. The lower surface of the superlattice collector N-type layer 65;

The fifth channel insulating layer 70 is annular, penetrating from the upper surface of the superlattice emitter N-type layer 67 and downward to the superlattice emitter N-type layer 67 in a direction perpendicular to the superlattice emitter N-type layer 67 . On the lower surface of the lattice collector N-type layer 65, the third P+ conductive layer 68 and the third N+ conductive layer 69 are provided in the fifth channel insulating layer 70;

The eleventh ohmic contact layer 72 is disposed above the third P+ conductive layer 68 and in contact with the third P+ conductive layer 68;

A twelfth ohmic contact layer 71 is disposed above the third N+ conductive layer 69 and in contact with the third N+ conductive layer 69;

The thirteenth ohmic contact layer 73 is disposed above the superlattice emitter N-type layer 67 and in contact with the superlattice emitter N-type layer 67,

An eleventh dielectric protective layer 74 is provided between the thirteenth ohmic contact layer 73 and the eleventh ohmic contact layer 72, and between the thirteenth ohmic contact layer 73 and the twelfth ohmic contact layer 71;

A twelfth dielectric protective layer 75 is provided outside the eleventh ohmic contact layer 72 and the twelfth ohmic contact layer 71 .

The thirteenth dielectric protective layer 76 is provided on the superlattice emitter N-type layer 67 and the third N+ conductive layer 69, the superlattice emitter N-type layer 67 and the third P+ conductive layer. between layers 68.

The superlattice vertical N-P-N bipolar transistor consists of a superlattice-doped collector N-type layer (superlattice collector N-type layer) and a superlattice-doped base P-type layer (superlattice base P-type layer). It is composed of a doped superlattice emitter N-type layer (superlattice emitter N-type layer), a third P+ conductive layer and a third N+ conductive layer. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as n-i-p-i-n. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, uses different bandgaps to form special quantum wells to improve device performance. N+ and P+ conductive layers are formed using low-energy ion implantation technology. The ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, it is generally available. Titanium aluminum alloy, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing.

The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figures 8 and 9, superlattice planar N-P-N bipolar transistors include:

The superlattice emitter N-type region 55 is cylindrical and is arranged above the transition layer 2;

The superlattice base P-type region 56 is annular, arranged above the transition layer 2 and nested outside the superlattice emitter N-type region 55;

The superlattice collector N-type region 57 is annular, arranged above the transition layer 2 and nested outside the superlattice base P-type region 56;

The sixth channel insulating layer 58 is annular and is arranged outside the superlattice collector N-type region 57, and the sixth channel insulating layer 58 is arranged above the transition layer 2 or Embedding in the substrate above and through the transition layer 2;

The fourteenth ohmic contact layer 59 is circular, disposed above the superlattice emitter N-type region 55 and in contact with the superlattice emitter N-type region 55;

The fifteenth ohmic contact layer 61 is annular and is disposed above the superlattice base P-type region 56 and in contact with the superlattice base P-type region 56;

The sixteenth ohmic contact layer 63 is annular and is disposed above the superlattice collector N-type region 57 and in contact with the superlattice collector N-type region 57;

The fourteenth dielectric protective layer 60 is annular and is disposed between the fourteenth ohmic contact layer 59 and the fifteenth ohmic contact layer 61;

The fifteenth dielectric protective layer 62 is annular and is disposed between the fifteenth ohmic contact layer 61 and the sixteenth ohmic contact layer 63;

The sixteenth dielectric protection layer 64 is annular and is disposed outside the sixteenth ohmic contact layer 63 .

The superlattice planar N-P-N bipolar transistor consists of a superlattice-doped collector N-type region (superlattice collector N-type region) and a superlattice base P-type region (superlattice base P-type region). Composed of doped superlattice emitter N-type region (superlattice emitter N-type region), ohmic contact layer, etc. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as n-i-p-i-n. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve devices performance. Low-energy ion implantation technology is used to form the superlattice collector N-type region, the doped superlattice base P-type region, the doped superlattice emitter N-type region, etc. The ohmic electrode is formed by plasma sputtering technology, but the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, titanium-aluminum alloy can generally be used, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figure 10, the superlattice capacitor and varactor include:

The fifth superlattice intrinsic layer 77 is provided above the transition layer 2;

The second superlattice P-type layer 78 is provided above the fifth superlattice intrinsic layer 77;

The sixth superlattice intrinsic layer 79 is provided above the second superlattice P-type layer 78;

The first superlattice low-resistance N-type layer 80 is provided above the sixth superlattice intrinsic layer 79;

The fourth P+ conductive layer 81 and the fourth N+ conductive layer 82 extend from the upper surface of the first superlattice low-resistance N-type layer 80 to the direction perpendicular to the first superlattice low-resistance N-type layer 80 . Penetrating downward to the lower surface of the fifth superlattice intrinsic layer 77;

The seventh channel insulating layer 83 is annular and penetrates downward from the upper surface of the first superlattice low-resistance N-type layer 80 in a direction perpendicular to the first superlattice low-resistance N-type layer 80 To the lower surface of the fifth superlattice intrinsic layer 77, the fourth P+ conductive layer 81 and the fourth N+ conductive layer 82 are provided in the seventh channel insulating layer 83;

The seventeenth ohmic contact layer 84 is disposed above the first superlattice low-resistance N-type layer 80 and in contact with the first superlattice low-resistance N-type layer 80;

The eighteenth ohmic contact layer 85 is disposed above the fourth N+ conductive layer 82 and in contact with the fourth N+ conductive layer 82;

The nineteenth ohmic contact layer 86 is disposed above the fourth P+ conductive layer 81 and in contact with the fourth P+ conductive layer 81;

The seventeenth dielectric protective layer 87 is provided between the seventeenth ohmic contact layer 84 and the eighteenth ohmic contact layer 85, and the seventeenth ohmic contact layer 84 and the nineteenth ohmic contact layer 86;

The eighteenth dielectric protection layer 88 is provided outside the eighteenth ohmic contact layer 85 and the nineteenth ohmic contact layer 86 .

Superlattice n-i-p-i diodes and PN junction capacitance varactors (superlattice capacitors and varactors) are composed of a superlattice intrinsic layer (the fifth superlattice intrinsic layer) and a base P-type layer doped with the superlattice ( Second superlattice P-type layer), superlattice intrinsic layer (sixth superlattice intrinsic layer), doped superlattice N-type layer (first superlattice low-resistance N-type layer), It is composed of four P+ conductive layers and a fourth N+ conductive layer. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as n-i-p-i-n. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve devices performance. N+ and P+ conductive layers are formed using low-energy ion implantation technology. The ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, it is generally available. Titanium aluminum alloy, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figure 11, the superlattice resistor and varistor include:

The seventh superlattice intrinsic layer 89 is provided above the transition layer 2;

The third superlattice P-type layer 90 is provided above the seventh superlattice intrinsic layer 89;

The eighth superlattice intrinsic layer 91 is provided above the third superlattice P-type layer 90;

The second superlattice low-resistance N-type layer 92 is provided above the eighth superlattice intrinsic layer 91;

The fifth P+ conductive layer 93 and the fifth N+ conductive layer 94 extend from the upper surface of the second superlattice low-resistance N-type layer 92 toward the direction perpendicular to the second superlattice low-resistance N-type layer 92 The direction penetrates downward to the lower surface of the seventh superlattice intrinsic layer 89;

The eighth channel insulating layer 95 is rectangular or annular, extending from the upper surface of the second superlattice low-resistance N-type layer 92 in a direction perpendicular to the second superlattice low-resistance N-type layer 92 . Penetrating downward to the lower surface of the seventh superlattice intrinsic layer 89, the fifth P+ conductive layer 93 and the fifth N+ conductive layer 94 are provided in the eighth channel insulating layer 95;

A 20th ohm contact layer 96, a 21st ohm contact layer 97 and a 22nd ohm contact layer 98 are one group, and there are two groups in total;

The twentieth ohmic contact layer 96 is disposed above the second superlattice low-resistance N-type layer 92 and in contact with the second superlattice low-resistance N-type layer 92;

The twenty-first ohmic contact layer 97 is disposed above the fifth N+ conductive layer 94 and in contact with the fifth N+ conductive layer 94;

The twenty-second ohmic contact layer 98 is disposed above the fifth P+ conductive layer 93 and in contact with the fifth P+ conductive layer 93;

The nineteenth dielectric protective layer 99 is provided between the twentieth ohmic contact layer 96 and the twenty-first ohmic contact layer 97, the twentieth ohmic contact layer 96 and the twenty-second ohmic contact layer 98;

The twentieth dielectric protective layer 100 is provided outside the twenty-first ohmic contact layer 97 and the twenty-second ohmic contact layer 98 .

As shown in FIG. 12 , in one embodiment, the superlattice resistor and varistor includes two groups of 20th ohm contact layer 96 , 21st ohm contact layer 97 and 22nd ohm contact layer 98 . The eighth channel insulating layer 95 is annular with an I-shaped vacancy; a set of 20th ohm contact layer 96, 21st ohm contact layer 97 and 22nd ohm contact layer are respectively provided at both ends of the I-shaped vacancy. Contact layer 98.

Superlattice n-i-p-i resistors and varistors (superlattice resistors and varistors) are composed of a superlattice intrinsic layer (the seventh superlattice intrinsic layer) and a base P-type layer of doped superlattice (the third superlattice P-type layer), superlattice intrinsic layer (eighth superlattice intrinsic layer), doped superlattice N-type layer (second superlattice low-resistance N-type layer), fifth P+ conductive layer and The fifth N+ conductive layer is composed of other components. In order to meet the performance requirements of bipolar transistor integrated circuits, more layers of structures can be designed, such as n-i-p-i-n. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve devices performance. N+ and P+ conductive layers are formed using low-energy ion implantation technology. The ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, it is generally available. Titanium aluminum alloy, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

As shown in Figure 13, the superlattice inductor and transformer include:

The ninth superlattice intrinsic layer 101 is provided above the transition layer 2;

The fourth superlattice P-type layer 102 is provided above the ninth superlattice intrinsic layer 101;

The tenth superlattice intrinsic layer 103 is provided above the fourth superlattice P-type layer 102;

The third superlattice low-resistance N-type layer 104 is provided above the tenth superlattice intrinsic layer 103;

The sixth P+ conductive layer 105 and the sixth N+ conductive layer 106 extend from the upper surface of the third superlattice low-resistance N-type layer 104 toward the direction perpendicular to the third superlattice low-resistance N-type layer 104 The direction penetrates downward to the lower surface of the ninth superlattice intrinsic layer 101;

The ninth channel insulating layer 107 is rectangular or annular, extending from the upper surface of the third superlattice low-resistance N-type layer 104 to a direction perpendicular to the third superlattice low-resistance N-type layer 104 . Penetrating downward to the lower surface of the ninth superlattice intrinsic layer 101, the sixth P+ conductive layer 105 and the sixth N+ conductive layer 106 are provided in the ninth channel insulating layer 107;

A twenty-third ohm contact layer 108, a twenty-fourth ohm contact layer 109 and a twenty-fifth ohm contact layer 110 are one group, and there are two groups in total;

The twenty-third ohmic contact layer 108 is disposed above the third superlattice low-resistance N-type layer 104 and in contact with the third superlattice low-resistance N-type layer 104;

The twenty-fourth ohmic contact layer 109 is disposed above the sixth N+ conductive layer 106 and in contact with the sixth N+ conductive layer 106;

The twenty-fifth ohmic contact layer 110 is disposed above the sixth P+ conductive layer 105 and in contact with the sixth P+ conductive layer 105;

The twenty-first dielectric protective layer 111 is provided between the twenty-third ohmic contact layer 108 and the twenty-fourth ohmic contact layer 109, the twenty-third ohmic contact layer 108 and the twenty-fourth ohmic contact layer 109. between;

The twenty-second dielectric protective layer 112 is provided outside the twenty-fourth ohmic contact layer 109 and the twenty-fifth ohmic contact layer 110 .

As shown in FIG. 14 , in one embodiment, the superlattice inductor and inductor include two sets of twenty-third ohm contact layer 108 , twenty-fourth ohm contact layer 109 , and twenty-fifth ohm contact layer 110 . The ninth channel insulating layer 107 is annular with an S-shaped vacancy; a set of 23rd ohm contact layer 108, 24th ohm contact layer 109 and 25th ohm contact layer are respectively provided at both ends of the S-shaped vacancy. Ohmic contact layer 110 .

Superlattice n-i-p-i inductors and inductors (superlattice inductors and inductors) are composed of a superlattice intrinsic layer (the ninth superlattice intrinsic layer) and a base P-type layer doped with the superlattice (the ninth superlattice intrinsic layer). The fourth superlattice P-type layer), the superlattice intrinsic layer (the tenth superlattice intrinsic layer), the doped superlattice N-type layer (the third superlattice low-resistance N-type layer), the sixth It is composed of a P+ conductive layer and a sixth N+ conductive layer. In order to meet the performance requirements of integrated circuits, more layers of structures can be designed, such as n-i-p-i-n. . . . . . , not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), gallium arsonide (GaAs), but also heterogeneous superlattice layers, such as gallium nitride Ga(x)As(1 -x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve devices performance. N+ and P+ conductive layers are formed using low-energy ion implantation technology. The ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, it is generally available. Titanium aluminum alloy, etc. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

n-i-p-i superlattice flash memory (superlattice flash memory) includes doped P-channel n-i-p-i superlattice field-effect ferroelectric transistors or doped N-channel n-i-p-i superlattice field-effect ferroelectric transistors.

As shown in Figure 15, the P-channel n-i-p-i superlattice field effect ferroelectric transistor includes:

The eleventh superlattice intrinsic layer 113 is provided above the transition layer 2;

Superlattice low-resistance P-type layer 114 is provided above the eleventh superlattice intrinsic layer 113;

A twelfth superlattice intrinsic layer 115 is provided above the superlattice low-resistance P-type layer 114;

The second superlattice N-type layer 116 is provided above the twelfth superlattice intrinsic layer 115;

The first ferroelectric thin film layer 117 is provided above the second superlattice N-type layer 116;

The seventh P+ conductive layer 118 penetrates from the upper surface of the second superlattice N-type layer 116 downward to the eleventh superlattice N-type layer 116 in a direction perpendicular to the second superlattice N-type layer 116 The lower surface of the lattice intrinsic layer 113;

The tenth channel insulating layer 119 is rectangular or annular, penetrating downward from the upper surface of the second superlattice N-type layer 116 to the direction perpendicular to the second superlattice N-type layer 116 . On the lower surface of the eleventh superlattice intrinsic layer 113, the seventh P+ conductive layer 118 is provided in the tenth channel insulating layer 119;

The twenty-sixth ohmic contact layer 120 is disposed above the first ferroelectric thin film layer 117 and in contact with the first ferroelectric thin film layer 117,

The twenty-seventh ohmic contact layer 121 is disposed above the seventh P+ conductive layer 118 and in contact with the seventh P+ conductive layer 118;

The twenty-third dielectric protective layer 123 is provided between the twenty-sixth ohmic contact layer 120 and the twenty-seventh ohmic contact layer 121;

The twenty-fourth dielectric protection layer 124 is provided outside the twenty-seventh ohmic contact layer 121 .

Doped P-channel n-i-p-i superlattice field-effect ferroelectric transistor (P-channel n-i-p-i superlattice field-effect ferroelectric transistor) consists of a ferroelectric thin film layer and a doped superlattice intrinsic layer (eleventh superlattice intrinsic layer) layer), doped superlattice P-type layer (superlattice low-resistance P-type layer), superlattice intrinsic layer (twelfth superlattice intrinsic layer), doped superlattice N-type layer layer (the second superlattice N-type layer), the seventh P+ conductive layer, etc. In order to meet the performance requirements of integrated circuits, superlattice thin film layers of different thicknesses can be designed. Not only can homogeneous superlattice layers be used, such as silicon, gallium nitride (GaN), and gallium arsonide (GaAs), but also heterogeneous superlattice layers can be used, such as gallium arsonide nitride Ga(x)As(1- x)N, gallium aluminum nitride Ga(x)Al(1-x)N, gallium nitride phosphide Ga(x)Ps(1-x)N, etc., use different bandgap widths to form special quantum wells to improve device performance . The P+ conductive layer is formed using low-energy ion implantation technology, and the ohmic electrode is formed using plasma sputtering technology. However, the plasma sputtering material will depend on the material of the superlattice semiconductor layer. For example, for gallium nitride materials, titanium-aluminum alloy can generally be used. ,wait. The gate insulating layer can be silicon nitride or the like. Devices need to be separated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process followed by ion sputtering of insulating material and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation to form a PN junction type channel insulating layer. If necessary, multiple isolation methods can be used on the same superlattice integrated circuit to achieve maximum performance optimization.

Similarly, doped N-channel n-i-p-i superlattice field-effect ferroelectric transistors can also be designed and manufactured. The principle is very similar, except that when a voltage in the same direction is applied to the ferroelectric film, such as when a negative voltage is applied, the doped P-channel n-i-p-i superlattice field-effect ferroelectric transistor will be in the on state, while the doped N-channel n-i-p-i super lattice field effect ferroelectric transistor will be in the on state. The lattice field effect ferroelectric transistor will be in the off-on state;

As shown in Figure 16, the N-channel n-i-p-i superlattice field effect ferroelectric transistor includes:

The thirteenth superlattice intrinsic layer 125 is provided above the transition layer 2;

The superlattice low-resistance N-type layer 126 is provided above the thirteenth superlattice intrinsic layer 125;

The fourteenth superlattice intrinsic layer 127 is provided above the superlattice low-resistance N-type layer 126;

The fifth superlattice P-type layer 128 is provided above the fourteenth superlattice intrinsic layer 127;

The second ferroelectric thin film layer 129 is provided above the fifth superlattice P-type layer 128;

The seventh N+ conductive layer 130 penetrates from the upper surface of the fifth superlattice P-type layer 128 downward to the thirteenth superlattice P-type layer 128 in a direction perpendicular to the fifth superlattice P-type layer 128 The lower surface of the lattice intrinsic layer 125;

The eleventh channel insulating layer 131 penetrates from the upper surface of the fifth superlattice P-type layer 128 downward to the thirteenth channel in a direction perpendicular to the fifth superlattice P-type layer 128 On the lower surface of the superlattice intrinsic layer 125, the seventh N+ conductive layer 130 is provided in the eleventh channel insulating layer 131;

The twenty-eighth ohmic contact layer 132 is disposed above the second ferroelectric thin film layer 129 and in contact with the second ferroelectric thin film layer 129,

The twenty-ninth ohmic contact layer 133 is disposed above the seventh N+ conductive layer 130 and in contact with the seventh N+ conductive layer 130;

The twenty-fifth dielectric protective layer 134 is provided between the twenty-eighth ohmic contact layer 132 and the twenty-ninth ohmic contact layer 133;

The twenty-sixth dielectric protection layer 135 is provided outside the twenty-ninth ohmic contact layer 133 .

The above-mentioned first to eleventh channel insulating layers are autonomous cooling insulating layers.

As shown in Figure 17, the autonomous cooling insulation layer 202 includes:

The cooling substance containing cavity 201 is provided in the autonomous cooling insulation layer 202,

The first capillary tube 203 is provided in the autonomous cooling insulation layer 202, with one end connected to the cooling substance containing cavity 201, and the other end connected to the upper surface of the autonomous cooling insulation layer 202;

A second capillary tube 205 is also provided in the dielectric protective layer 204 above the self-cooling insulating layer 202. The second capillary tube 205 is connected to the first capillary tube 203 of the self-cooling insulating layer 202 and the second capillary tube 205 The upper surface portion close to the dielectric protective layer 204 is set in a curved shape so that the outlet of the second capillary tube 205 on the upper surface is at a certain angle (can be 15 degrees), so that the cooling material undergoes a phase change when the temperature rises. When, it flows out from the outlet of the second capillary pipe 205 and flows onto the ohmic contact layer. Thereby cooling down.

By setting up an autonomous cooling insulating layer, when the component generates heat when burned out after a short circuit, the cooling material in the autonomous cooling insulating layer undergoes a phase change when heated, thereby absorbing heat. When the phase change occurs further, the volume of the cooling material increases, and the cooling material in the self-cooling insulating layer increases from the capillary tube. It is sprayed out on the road and sprayed onto the burned components, thereby further cooling the burned components; this can prevent damage to nearby intact components, thereby reducing losses.

The above-mentioned first to eleventh channel insulating layers are isolation insulating layers:

As shown in FIG. 18 , a cavity 212 is provided inside the insulating layer 211 , and a cooling substance is provided in the cavity 212 .

By setting up an isolation insulating layer, when the component generates heat when burned out after a short circuit, the outer insulating layer of the isolation insulating layer burns out and releases a cooling substance. The cooling substance undergoes a phase change when heated, thereby absorbing heat and further cooling when the phase change occurs. The volume of the material increases, thereby isolating the burned components from the intact external components; this prevents damage to nearby intact components, thereby reducing losses.

As shown in Figure 18, in one embodiment, at least one connector 213 is provided in the cavity 212. One end of the connector 213 is connected to the left side wall of the cavity 212, and the other end is connected to the right side of the cavity 212. Side wall connection; the diameter of the middle part of the connecting body 213 is smaller than the diameter of both ends.

By arranging the connector, the space in the cavity is supported, making the cavity structure stronger; by arranging the middle diameter to be smaller than the two ends, when the cooling material expands due to heat, the fracture position of the connector is located in the middle. Pull the intact components next to them to avoid component damage caused by pulling.

Furthermore, the cooling material is doped with fluorescent material. When the circuit burns out, the image of the fluorescent material in the insulating layer can be inspected to more quickly determine the location and extent of circuit damage.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. In this way, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims (5)

1. A superlattice ultra-large scale integrated circuit, comprising:

a substrate;

a transition layer disposed over the substrate;

the component layer is arranged above the transition layer and is a superlattice integrated circuit constructed by a device containing two-dimensional electron gas and two-dimensional hole gas;

The device comprises: superlattice resistance and varistors;

from a cross-sectional perspective, the superlattice resistor and varistor comprises:

a seventh superlattice intrinsic layer disposed above the transition layer;

a third superlattice P-type layer disposed over the seventh superlattice intrinsic layer;

an eighth superlattice intrinsic layer disposed above the third superlattice P-type layer;

the second superlattice low-resistance N-type layer is arranged above the eighth superlattice intrinsic layer;

the fifth P+ conductive layer and the fifth N+ conductive layer penetrate downwards from the upper surface of the second superlattice low-resistance N-type layer to the lower surface of the seventh superlattice intrinsic layer in a direction perpendicular to the second superlattice low-resistance N-type layer;

an eighth channel insulating layer penetrating from the upper surface of the second superlattice low-resistance N-type layer and downwards to the lower surface of the seventh superlattice intrinsic layer in a direction perpendicular to the second superlattice low-resistance N-type layer, wherein the fifth p+ conductive layer and the fifth n+ conductive layer are arranged in the eighth channel insulating layer;

a twenty-first ohmic contact layer, a twenty-second ohmic contact layer, and a twenty-first ohmic contact layer;

The twenty-first ohmic contact layer is arranged above the first superlattice low-resistance N-type layer and is in contact with the first superlattice low-resistance N-type layer;

a twenty-first ohmic contact layer disposed over and in contact with the fifth n+ conductive layer;

a twenty-second ohmic contact layer disposed over and in contact with the fifth p+ conductive layer;

a nineteenth dielectric protective layer disposed between the twenty-first ohmic contact layer and the twenty-first ohmic contact layer, and the twenty-second ohmic contact layer;

a twenty-first ohmic contact layer and a twenty-second ohmic contact layer are arranged on the outer sides of the twenty-first and twenty-second dielectric protective layers;

from the perspective of overlooking and perspective, the eighth channel insulating layer is annular with an I-shaped vacancy; and a twenty-first ohmic contact layer, a twenty-second ohmic contact layer and a twenty-first ohmic contact layer are respectively arranged at two ends of the I-shaped gap.

2. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein said substrate is silicon, germanium or a compound semiconductor.

3. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein said transition layer is one of a silicon dioxide, silicon nitride, and compound semiconductor layer.

4. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein the plurality of through holes are uniformly distributed in the bottom of the substrate.

5. The superlattice very large scale integrated circuit as recited in claim 1, wherein said third superlattice P-type layer and said second superlattice low-resistance N-type layer are either homogeneous semiconductor superlattice layers or heterogeneous semiconductor superlattice layers.