CN113870919B - Memory device and operation method thereof - Google Patents

Abstract

The invention provides a memory device and an operation method thereof. The memory device includes an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between the main input/output line pair and the local input/output line pair. The local input/output line pair is coupled to the plurality of bit line pairs through the bit line sense amplifying circuit. The memory device performs a two-stage operation to input or output data of a selected bit line pair of the bit line pairs, wherein the selected bit line pair is turned on with the local input output line pair only in one of the two-stage operation, and the data of the selected bit line pair latched in the input output data latch circuit is transferred to the main input output line pair in the other of the two-stage operation.

Description

Memory device and operation method thereof

Technical Field

The present invention relates to a memory device, and more particularly to a memory device capable of improving access speed and an operating method thereof.

Background Art

The operating speed of dynamic random access memory (DRAM) is limited by its own access mechanism. Therefore, how to improve the access speed of DRAM has always been an important research topic, especially for DRAM with error correction code (ECC) circuit. Although the ECC circuit can improve the reliability of data, it will increase the column-to-column delay (tCCD) of the DRAM. Therefore, how to propose a memory device with high reliability and high speed has become an important issue in the development of current memory technology.

Summary of the invention

The present invention provides a memory device and an operation method thereof, which has a pipeline structure and can shorten the operation cycle of the memory device.

An embodiment of the present invention provides a memory device, including an input/output data latch circuit and a bit line sense amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a regional input/output line pair. The regional input/output line pair is coupled to a plurality of bit line pairs through a bit line sense amplifier circuit. When the memory device performs a read operation or a write operation, the memory device performs a two-phase operation to input or output data of a selected bit line pair among the bit line pairs, wherein the selected bit line pair is connected to the regional input/output line pair only in one phase of the two-phase operation, and, in another phase of the two-phase operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair.

An embodiment of the present invention provides an operation method of a memory device, comprising the following steps: In a first phase operation, data of a selected bit line pair stored in a sense amplifier data latch is latched into an input-output data latch circuit. In a second phase operation, the data of the selected bit line pair latched in the input-output data latch circuit is transmitted to a main input-output line pair to perform a read operation.

Based on the above, the present invention provides a memory device and an operation method thereof. An input/output data latch circuit is provided between a main input/output line pair and a local input/output line pair to latch data to be written or read. By temporarily storing target data between the main input/output line pair and the local input/output line pair, the access operation can be divided into a first-stage operation and a second-stage operation, so that the access operation has a pipeline architecture.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present invention;

FIG. 2A is a timing diagram of a read operation according to an embodiment of the present invention;

FIG. 2B is a timing diagram of a write operation according to an embodiment of the present invention;

FIG3 is a timing diagram of a read-while-write (RWW) operation according to an embodiment of the present invention;

FIG4 is a circuit diagram of a memory device according to another embodiment of the present invention;

FIG5 is a timing diagram of a masked-write operation according to an embodiment of the present invention;

6 is a timing diagram of a write mask operation according to an embodiment of the present invention;

FIG7 is a flow chart of an operating method of a memory device according to an embodiment of the present invention;

FIG. 8 is a flowchart of an operating method of a memory device according to another embodiment of the present invention.

Description of Reference Numerals

100: memory device

110: Input and output data latch circuit

120: Main sensing and driving circuit

210:ECC Circuit

301, 302, 401, 402: Read-Modify-Write Operations

310: Error checking and corrective steps

320: Data transmission step

330: Generate verification data step

BLSA: Bit Line Sense Amplifier

BL1, BL2: bit line pair

BLT1, BLT2: bit lines

BLB1, BLB2: complementary bit lines

CSL1, CSL2: column selection signal

DR_EN: drive enable signal

LIO: Area Input and Output Line Pair

LIOT: Area Input Output Line

LIOB: complementary area input output line

MA: Storage Cell Array

MIO: Main input and output line pair

MIOT: Main input and output line

MIOB: Complementary Main Input Output Line

MC1, MC2: storage unit

MWR1: First write mask instruction

MWR2: Second write mask instruction

m: integer

RD: Read data

RDIN: Read input signal

RDOUT: read output signal

RDL: Read data latch circuit

READ: Read operation

RWW: Read and write synchronous operation

SADL: Sense Amplified Data Latch

SA_EN: sensing enable signal

ST1: First stage operation

ST2: Second stage operation

TC: Switch

T0: Time

tCCD: time interval

tCOR, tCOW, T: time length

WD: Write data

WDL: Write data latch circuit

WDIN: write input signal

WDOUT: write output signal

WL: Word Line

WRITE: write operation

S710, S720, S810, S820: Steps of the method for operating the memory device

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

In the following embodiments, a dynamic random access memory (DRAM) is used as an example to illustrate the memory device and the operation method thereof of the present invention. However, the present invention is not limited to the type of the memory device.

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 1 , the memory device 100 at least includes an input/output data latch circuit 110, a bit line sensing amplifier circuit BLSA, and a memory cell array MA. The memory cell array MA is composed of a plurality of memory cells arranged in an array. These memory cells are connected to a plurality of word lines and a plurality of bit line pairs. To simplify the description, the memory cell array MA of FIG. 1 only shows two memory cells MC1 and MC2 on the word line WL as an example. The memory cell MC1 is coupled to the bit line pair BL1. The bit line pair BL1 includes a bit line BLT1 and a complementary bit line BLB1. The memory cell MC2 is coupled to the bit line pair BL2. The bit line pair BL2 includes a bit line BLT2 and a complementary bit line BLB2.

The input/output data latch circuit 110 is coupled between the main input/output line pair MIO and the regional input/output line pair LIO. The main input/output line pair MIO includes a main input/output line MIOT and a complementary main input/output line MIOB. The regional input/output line pair LIO includes a regional input/output line LIOT and a complementary regional input/output line LIOB. The input/output data latch circuit 110 is used to latch data to be written into the memory cell array MA or data of the memory cell array MA output from the regional input/output line pair LIO.

The regional input-output line pair LIO is coupled to a plurality of bit line pairs, such as bit line pairs BL1 and BL2, through a bit line sense amplifier circuit BLSA. The column selection signal CSLn controls the switch TC to connect the regional input-output line pair LIO and the bit line pair BLn, where n is an integer. The bit line sense amplifier circuit BLSA is used to sense and amplify the potential signal on the bit line pair. The bit line sense amplifier circuit BLSA also includes a plurality of sense amplifier data latches SADL. These sense amplifier data latches SADL are connected between these bit line pairs and are used to store the data of these bit line pairs.

The main sensing and driving circuit 120 is coupled to the main input and output line pair MIO and is controlled by the driving enable signal DR_EN and the sensing enable signal SA_EN. When the driving enable signal DR_EN enables the main sensing and driving circuit 120, the memory device 100 performs a write operation on the memory cell array MA. The main input and output line pair MIO receives the write data from the main sensing and driving circuit 120, and the local input and output line pair LIO receives the write data from the main input and output line pair MIO through the input and output data latch circuit 110, and then transmits the write data to the sense amplifier data latch SADL on the corresponding bit line pair. When the sensing enable signal SA_EN enables the main sensing and driving circuit 120, the memory device 100 performs a read operation on the memory cell array MA. The read data stored in the sense amplifier data latch SADL is transmitted to the input and output data latch circuit 110 through the local input and output line pair LIO and is latched in the input and output data latch circuit 110. Next, the input/output data latch circuit 110 transmits the read data to the main input/output line pair MIO. Finally, the main sensing and driving circuit 120 senses the read data of the main input/output line pair MIO.

In short, in the present embodiment, when the memory device 100 performs a read operation or a write operation, the memory device 100 performs a two-phase operation to input or output data of a selected bit line pair among the bit line pairs. For example, the memory cell to be accessed is the memory cell MC1, so the selected bit line pair is the bit line pair BL1. The selected bit line pair BL1 is connected to the regional input-output line pair LIO only in one phase operation of the two-phase operation. In another phase operation of the two-phase operation, the data of the selected bit line pair BL1 latched in the input-output data latch circuit 110 is transmitted to the main input-output line pair MIO.

More specifically, the above-mentioned two-phase operation includes a first phase operation and a second phase operation. When the memory device 100 is to perform a read operation on the memory cell MC1, in the first phase operation, the data of the selected bit line pair BL1 is latched from the corresponding sense amplifier data latch SADL to the input-output data latch circuit 110, and in the second phase operation, the data latched in the input-output data latch circuit 110 is transmitted to the main input-output line pair MIO. When the memory device 100 is to perform a write operation on the memory cell MC1, in the first phase operation, the write data is latched from the main input-output line pair MIO to the input-output data latch circuit 110, and in the second phase operation, the write data latched in the input-output data latch circuit 110 is transmitted to the sense amplifier data latch SADL corresponding to the selected bit line pair BL1.

The implementation details are further described below.

FIG. 2A is a timing diagram of a read operation according to an embodiment of the present invention, and FIG. 2B is a timing diagram of a write operation according to an embodiment of the present invention. Please refer to FIG. 1 to FIG. 2B together. In this embodiment, the input-output data latch circuit 110 includes a read data latch circuit RDL and a write data latch circuit WDL. The read data latch circuit RDL is coupled between the main input-output line pair MIO and the regional input-output line pair LIO, and is controlled by the read input signal RDIN and the read output signal RDOUT. The write data latch circuit WDL is coupled between the main input-output line pair MIO and the regional input-output line pair LIO, and is controlled by the write input signal WDIN and the write output signal WDOUT.

2A , when the memory device 100 performs a read operation READ, each read operation READ is divided into two phases: a first phase operation ST1 and a second phase operation ST2. In the first phase operation ST1, the column selection signal CSL1 selects and connects the bit line pair BL1 and the regional input-output line pair LIO. The sense amplifier data latch SADL located between the bit line BLT1 and the complementary bit line BLB1 transmits the read data RD to the regional input-output line pair LIO. In addition, the read input signal RDIN allows the read data latch circuit RDL to receive and latch the read data RD from the regional input-output line pair LIO. In the second phase operation ST2, the read output signal RDOUT allows the read data RD latched in the read data latch circuit RDL to be transmitted to the main input-output line pair MIO, and the sense enable signal SA_EN allows the main sensing and driving circuit 120 to sense the read data RD on the main input-output line pair MIO.

It is particularly noted that in the second phase operation ST2 of the read operation READ, the column selection signal CSL1 is already in a disabled state, and the bit line pair BL1 disconnects the regional input-output line pair LIO. In the read operation READ of this embodiment, the time length of the first phase operation ST1 is the same as that of the second phase operation ST2, and the time length is tCOR, and the time length tCOR is the same as the column selection cycle of the memory device 100. The column selection cycle is the pulse cycle during which each column is activated.

Referring to FIG. 2B , when the memory device 100 performs a write operation WRITE, each write operation WRITE is also divided into two phases: a first phase operation ST1 and a second phase operation ST2. In the first phase operation ST1, the drive enable signal DR_EN is in an enabled state, and the main sensing and driving circuit 120 transmits the write data WD to the main input-output line pair MIO. The write input signal WDIN allows the write data latch circuit WDL to receive the write data WD from the main input-output line pair MIO and latch it. In the second phase operation ST2, the write output signal WDOUT allows the write data latch circuit WDL to output the latched write data WD to the regional input-output line pair LIO. In addition, the column select signal CSL1 enables the bit line pair BL1 to connect to the regional input-output line pair LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL1. Finally, the write data WD is written to the memory cell MC1.

It is particularly noted that in the first phase operation ST1 of the write operation WRITE, the column selection signal CSL1 is in a disabled state, and the bit line pair BL1 has not yet been connected to the local input/output line pair LIO. In the write operation WRITE of the present embodiment, the time length of the first phase operation ST1 is the same as that of the second phase operation ST2, and the time length is tCOW, and the time length tCOW is the same as the column selection cycle of the memory device 100.

In this embodiment, regardless of whether it is a two-stage operation of a write operation WRITE or a read operation READ, the time length of each stage operation is the same. The time of the first stage operation ST1 and the second stage operation ST2 of the read operation READ are both tCOR. The time of the first stage operation ST1 and the second stage operation ST2 of the write operation WRITE are both tCOW. In addition, the time length of the two-stage operation of this embodiment is the same in the write operation WRITE and in the read operation READ. The time length tCOR of the read operation READ is the same as the time length tCOW of the write operation WRITE. Here, the time length of each stage operation is one column selection cycle.

Since the input/output data latch circuit 110 latches the write data WD and the read data RD, the memory device 100 can use a two-stage operation whether executing a write operation WRITE or a read operation READ, so that the memory device 100 has a pipeline architecture and can execute multiple instructions in parallel.

FIG. 3 is a timing diagram of a read-while-write (RWW) operation according to an embodiment of the present invention. Referring to FIG. 3 , when the memory device 100 performs a read-while-write (RWW) operation, each read-while-write (RWW) operation is divided into two phases: a first phase operation ST1 and a second phase operation ST2. In the first phase operation ST1, the drive enable signal DR_EN is in an enabled state, and the main sensing and driving circuit 120 transmits the write data WD to the main input-output line pair MIO. The write input signal WDIN enables the write data latch circuit WDL to receive the write data WD from the main input-output line pair MIO and latch the write data WD. At the same time, the read input signal RDIN enables the read data latch circuit RDL to receive and latch the read data RD from the regional input-output line pair LIO. In the first phase operation ST1, the column select signal CSL1 selects the bit line pair BL1 to connect the regional input-output line pair LIO. The read data RD is transmitted from the sense amplifier data latch SADL connected to the bit line pair BL1 to the read data latch circuit RDL.

In short, in the first phase operation ST1 , the memory device 100 may perform in parallel the input of the write data WD to the write data latch circuit WDL and the input of the read data RD of the memory cell MC1 to the read data latch circuit RDL.

In the second phase operation ST2, the write output signal WDOUT controls the write data latch circuit WDL to output the latched write data WD to the regional input-output line pair LIO. At the same time, the read output signal RDOUT controls the read data latch circuit RDL to output the read data RD to the main input-output line pair MIO, so that the main sensing and driving circuit 120 senses the read data RD from the memory cell MC1. In addition, the column selection signal CSL2 selects the bit line pair BL2 to connect the regional input-output line pair LIO. The write data WD is transmitted to the sense amplifier data latch SADL corresponding to the bit line pair BL2. The write data WD will be written to the memory cell MC2.

In short, in the second phase operation ST2, the memory device 100 can output the write data WD from the write data latch circuit WDL and output the read data RD of the memory cell MC1 from the read data latch circuit RDL in parallel. In the second phase operation ST2, the memory device 100 can sense the read data of the memory cell MC1 while writing the write data WD to the memory cell MC2.

In this embodiment, the time length of the first phase operation ST1 of the read-write synchronization operation RWW is the same as the time length of the second phase operation ST2, and can be one column selection cycle. For example, the time length of the read-write synchronization operation RWW can be equal to twice the time length tCOR (2*tCOR) or twice the time length tCOW (2*tCOW).

FIG. 4 is a circuit diagram of a memory device according to another embodiment of the present invention. Referring to FIG. 4 , the memory device 200 is similar to the memory device 100 and can implement various embodiments described above. The difference between the memory device 200 and the memory device 100 is that the memory device 200 further includes an error correction (ECC) circuit 210. The ECC circuit 210 is used to perform error checking and correction on data from the selected bit line pair.

FIG. 5 is a timing diagram of a write masking operation according to an embodiment of the present invention. The memory device 200 can implement the embodiment of FIG. 5 , and please refer to FIG. 5 in conjunction with FIG. 4 . The memory device 200 receives the first write masking instruction MWR1 and the second write masking instruction MWR2 in sequence, and performs a read-modify-write operation 301 and a read-modify-write operation 302 accordingly. During the execution of the read-modify-write operation 301 or 302 , after the read operation READ is executed, the ECC circuit 210 performs an error check and correction step 310 on the read data. In addition, before the write operation WRITE is executed, the memory device 200 also needs to perform a data transmission step 320 and a parity generation step 330 . The implementation details of the read operation READ and the write operation WRITE can refer to the description of the above embodiment. After a time T0 has passed since the write masking instruction (MWR1 or MWR2) was received, the memory device 200 will start to perform the data transmission step 320 and the parity generation step 330 . In the step 330 of generating verification data, for example, the step includes combining the write data with the read data to generate verification data.

In the present embodiment, the cycle lengths of the read operation READ and the write operation WRITE are the same, which is the time length T. Here, the time length T is equal to two column selection cycles, such as 2*tCOR or 2*tCOW. For the read operation READ and the write operation WRITE, the time length of each phase operation of the two-stage operation can be equal to one column selection cycle. When the memory device 200 performs the read-modify-write operation 301 or 302 on the selected bit line, the start time of the read operation READ applied to the selected bit line pair is at least 2 times the time length T earlier than the start time of the write operation WRITE applied to the selected bit line pair, that is, the memory device 200 will start the write operation WRITE after at least 4 column selection cycles after the start of the read operation READ. In other words, in the read-modify-write operation of the present embodiment, the start time point of the read operation READ is m*T earlier than the start time point of the write operation WRITE, where m is an integer greater than or equal to 2.

It is worth mentioning that the time interval tCCD between the first write mask instruction MWR1 and the second write mask instruction MWR2 can be shortened to n*T, where n is an integer greater than or equal to 1. In other words, the delay time from the minimum column address to the column address of the present embodiment can be shortened to at least two column selection cycles, thereby improving the operating speed of the memory device 200.

FIG6 is a timing diagram of a write mask operation according to an embodiment of the present invention. The memory device 200 can implement the embodiment of FIG6 , please refer to FIG6 in conjunction with FIG4 . The memory device 200 receives the first write mask instruction MWR1 and the second write mask instruction MWR2 in sequence, and performs a read-modify-write operation 401 and a read-modify-write operation 402 accordingly. During the execution of the read-modify-write operation 401 or 402, after the read operation READ is executed, the ECC circuit 210 performs an error check and correction step 310 on the read data. Similar to the process of the embodiment of FIG5 , the memory device 200 performs a data transmission step 320 and a verification data generation step 330 before the data is written back to the storage unit.

In this embodiment, the memory device 200 has a read-write synchronization function. The memory device 200 can perform a read-write synchronization operation RWW after step 330. When the memory device 200 performs the action of writing data back to the storage unit in the read-modify-write operation 401, it can also perform the action of reading data from the storage unit in the read-modify-write operation 402. In this way, the access speed of the memory device 200 can be accelerated. The implementation details of the read-write synchronization operation RWW, the read operation READ and the write operation WRITE can refer to the above-mentioned embodiments.

In this embodiment, the cycle lengths of the read-write synchronization operation RWW, the read operation READ, and the write operation WRITE are the same, which is a time length T. Here, the time length T is equal to two column selection cycles, such as 2*tCOR or 2*tCOW. When the memory device 200 performs a read-modify-write operation 401 or 402 on a selected bit line, the start time point of the read operation READ is m*T earlier than the read-write synchronization operation RWW or the write operation WRITE, where m is an integer greater than or equal to 2.

It is worth mentioning that the time interval tCCD between the first write mask instruction MWR1 and the second write mask instruction MWR2 is also shortened to m*T. That is, the delay time from the minimum column address to the column address in this embodiment can be shortened to at least 4 column selection cycles.

FIG7 is a flow chart of an operation method of a memory device according to an embodiment of the present invention. Referring to FIG7 , the operation method of FIG7 is applicable to the read operation READ of the embodiments of FIG1 to FIG6 . The operation method of FIG7 is described below with reference to the component symbols of the above embodiments.

In step S710, in the first phase operation ST1, the data of the selected bit line pair stored in the sense amplifier data latch SADL is latched to the input-output data latch circuit 110. In step S720, in the second phase operation ST2, the data of the selected bit line pair latched in the input-output data latch circuit 110 is transmitted to the main input-output line pair MIO to perform the read operation READ.

FIG8 is a flow chart of an operation method of a memory device according to another embodiment of the present invention. Referring to FIG8 , the operation method of FIG7 is applicable to the write operation WRITE of the embodiments of FIG1 to FIG6 . The operation method of FIG8 is described below with reference to the component symbols of the above embodiments.

In step S810, in the first phase operation ST1, the write data of the master input-output line pair MIO is latched to the input-output data latch circuit 110. In step S820, in the second phase operation ST2, the write data latched in the input-output data latch circuit 110 is transferred to the sense amplifier data latch SADL corresponding to the selected bit line pair to perform a write operation.

Each step of FIG. 7 and FIG. 8 has been described in detail in the embodiments of FIG. 1 to FIG. 6 . Those skilled in the art can obtain sufficient suggestions and instructions from the above descriptions, and will not be repeated here.

In summary, the memory device of the present invention divides the access operation into two stages by using the input/output data latch circuit disposed between the main input/output line pair and the local input/output line pair: data is transmitted from the sense amplifier data latch on the bit line pair to the input/output data latch circuit and data latched in the input/output data latch circuit is transmitted to the main input/output line pair. Therefore, the memory device can have a pipeline architecture and execute multiple instructions in parallel. This improves the access speed of the memory device. The embodiment of the present invention also provides an operation method applicable to the above-mentioned memory device.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (12)

1. A memory device, comprising: An input/output data latch circuit is coupled between the main input/output line pair and the local input/output line pair; and A bit line sensing amplifier circuit, wherein the regional input-output line pair is coupled to a plurality of bit line pairs through the bit line sensing amplifier circuit, When the memory device performs a read operation or a write operation, the memory device performs a two-phase operation to input or output data of a selected bit line pair in the bit line pair. wherein the selected bit line pair is connected to the regional input/output line only in one phase of the two-phase operation, and, in another phase of the two-phase operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair, When the memory device performs a read-write synchronization operation, the read-write synchronization cycle includes two column selection cycles, and the input-output data latch circuit includes a read data latch circuit and a write data latch circuit. wherein, in the first column selection cycle in the read-write synchronization cycle, the read data latch circuit receives data of the first bit line pair from the first sense amplifier data latch, and the write data latch circuit receives write data from the main input-output line pair, and In the second column selection cycle in the read-write synchronization cycle, the write data latch circuit provides the write data to the second sense amplifier data latch, and the read data latch circuit transmits the data of the first bit line pair to the main input-output line pair, The first bit line pair and the second bit line pair are two of the bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch store data of the first bit line pair and the second bit line pair respectively. 2. The memory device according to claim 1, wherein the bit line sense amplifier circuit comprises: a plurality of sense amplifier data latches for storing data of the bit line pairs; The two-stage operation includes a first-stage operation and a second-stage operation. wherein when the memory device performs the read operation, in the first phase operation, the data of the selected bit line pair is latched from the corresponding sense amplifier data latch to the input-output data latch circuit, and in the second phase operation, the data latched in the input-output data latch circuit is transmitted to the main input-output line pair, Wherein, when the memory device performs the write operation, in the first phase operation, the write data is latched from the main input-output line pair to the input-output data latch circuit, and in the second phase operation, the write data latched in the input-output data latch circuit is transmitted to the sense amplifier data latch corresponding to the selected bit line pair. 3. The memory device according to claim 2, wherein the input-output data latch circuit comprises: a read data latch circuit coupled between the main input-output line pair and the local input-output line pair, wherein when the memory device performs the read operation, in the first phase operation, the read data latch circuit receives data of the selected bit line pair, and in the second phase operation, the data latched in the read data latch circuit is transmitted to the main input-output line pair; and A write data latch circuit is coupled between the main input/output line pair and the local input/output line pair, wherein when the memory device performs the write operation, in the first phase operation, the write data latch circuit receives the write data, and in the second phase operation, the write data latched in the write data latch circuit is transmitted to the sense amplifier data latch corresponding to the selected bit line pair. 4. The memory device according to claim 1, further comprising: an error correction circuit for performing error checking and correction on the data from the selected bit line pair, Wherein, the memory device performs the read-write synchronization operation during a read-modify-write operation, wherein the start time of the read operation applied to the selected bit line pair is at least two read-write synchronization cycles earlier than the start time of the read-write synchronization operation or the write operation applied to the selected bit line pair. 5 . The memory device according to claim 4 , wherein the delay time from column address to column address is at least one of the read-write synchronization cycles and is an integer multiple of the read-write synchronization cycle. 6. The memory device according to claim 1, further comprising: an error correction circuit for performing error checking and correction on the data from the selected bit line pair, The cycle lengths of the read operation and the write operation are both equal to two column selection cycles, and the duration of each phase operation of the two-phase operation is equal to one column selection cycle. When the memory device performs a read-modify-write operation on the selected bit lines, the start time of the read operation applied to the selected bit line pair is at least 4 column selection cycles earlier than the start time of the write operation applied to the selected bit line pair. 7 . The memory device according to claim 6 , wherein a delay time from column address to column address is at least the two column selection cycles and is an integer multiple of the two column selection cycles. 8 . The memory device according to claim 1 , wherein the duration of each phase of the two-phase operation is the same. 9 . The memory device of claim 8 , wherein a time length of the two-phase operation in the write operation is the same as that in the read operation. 10. A method for operating a memory device, comprising: In the first phase of operation, the data of the selected bit line pair stored in the sense amplifier data latch is latched into the input-output data latch circuit; and In the second phase operation, the data of the selected bit line pair latched in the input-output data latch circuit is transferred to the main input-output line pair to perform a read operation. The read-write synchronization cycle of the read-write synchronization operation includes two column selection cycles. The operation method further includes: In the first column selection cycle in the read/write synchronization cycle, the read data latch circuit in the input/output data latch circuit receives the data of the first bit line pair from the first sense amplifier data latch, and the write data latch circuit in the input/output data latch circuit receives the write data from the main input/output line pair; and In the second column selection cycle in the read-write synchronization cycle, the write data latch circuit provides the write data to the second sense amplifier data latch, and the read data latch circuit transmits the data of the first bit line pair to the main input-output line pair. The first bit line pair and the second bit line pair are two of the bit line pairs, and the first sense amplifier data latch and the second sense amplifier data latch store data of the first bit line pair and the second bit line pair respectively. 11. The operating method according to claim 10, further comprising: In the first phase of operation, the write data of the main input/output line pair is latched into the input/output data latch circuit; and In the second phase operation, the write data latched in the input-output data latch circuit is transferred to the sense amplifier data latch corresponding to the selected bit line pair to perform a write operation. 12. The operating method according to claim 11, wherein the step of performing the reading operation and the writing operation further comprises: When the memory device performs the read operation, in the first phase operation, the data of the selected bit line pair is received by the read data latch circuit in the input-output data latch circuit, and in the second phase operation, the data latched in the read data latch circuit is transmitted to the main input-output line pair; and When the memory device performs the write operation, in the first phase operation, the write data is received by the write data latch circuit in the input-output data latch circuit, and in the second phase operation, the write data latched in the write data latch circuit is transmitted to the sense amplifier data latch corresponding to the selected bit line pair.