CN113866584A - A power cycle test circuit and test method of a power semiconductor device - Google Patents
A power cycle test circuit and test method of a power semiconductor device Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 146
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000010998 test method Methods 0.000 title claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 44
- 230000005669 field effect Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 3
- 101100117775 Arabidopsis thaliana DUT gene Proteins 0.000 description 7
- 101150091805 DUT1 gene Proteins 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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Abstract
本发明公开了一种功率半导体器件功率循环测试电路和测试方法，包括至少一条测试支路、栅极电源模块，每条测试支路结构相同；所述加热电流源的输出端接所述电流旁路模块，所述电流旁路模块的正极输出接所述二极管的正极，所述二极管的负极通过被测半导体器件后接所述电流旁路模块的负极；所述栅极电源模块接被测半导体器件的栅极；所述测试电流源的负极接所述被测半导体器件的一端，正极接所述二极管的正极，所述二极管的负极接所述被测半导体器件的另一端。本发明通过增设二极管，防止电流分流，可以在不增加开关器件的情况下，配合电流旁路模块，实现加热电流和测试电流的切换，从而避免因功率器件开通、关断带来的切换速率不够快的问题。
The invention discloses a power cycle test circuit and a test method of a power semiconductor device, comprising at least one test branch and a gate power supply module, and each test branch has the same structure; the output end of the heating current source is connected to the current bypass circuit module, the positive output of the current bypass module is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the negative electrode of the current bypass module after passing through the tested semiconductor device; the gate power supply module is connected to the tested semiconductor device The gate of the device; the negative electrode of the test current source is connected to one end of the tested semiconductor device, the positive electrode is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the other end of the tested semiconductor device. In the present invention, by adding diodes to prevent current shunting, it can cooperate with a current bypass module to realize the switching of heating current and test current without adding switching devices, thereby avoiding insufficient switching rate caused by turning on and off of power devices. quick question.
Description
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a power semiconductor device power cycle testing circuit and a testing method.
Background
The power cycle test equipment can test the reliability of more and more power electronic devices in the application of automobile and traffic industries including hybrid electric vehicles, electric vehicles and trains, and can also test the reliability of more and more power electronic devices in the application of renewable energy sources such as power generation and frequency converters, wind turbines and the like. The power cycle test and the thermal characteristic test are used for the power electronic device to simulate and measure the performance of the power electronic device in the service life. In the power circulation, the testing device actively heats to the highest target temperature through the current flowing through the semiconductor, then the heating current is turned off, the tested device is actively cooled to the lowest temperature, the parameters of the tested device such as forward voltage, junction temperature, shell temperature, thermal resistance, transient thermal impedance, grid leakage current and the like are monitored and calculated during the testing period, and the failure reason is found in real time.
The chinese patent application with publication number CN108646163A discloses a power cycle test system for semiconductor devices, which can heat devices of other tested branches by effectively utilizing the cooling time of one tested branch, so that the number of semiconductor devices to be tested is large, and the test efficiency of the power cycle test system can be greatly improved. Meanwhile, the provided power cycle test system is provided with a plurality of parallel test branches, so that a user can switch various test functions according to actual requirements, and devices of different manufacturers or models can be subjected to comparison test under the same test condition.
However, the above invention patent test cannot realize independent control between the test branches by the way of alternately switching the two test branches. The diode is not added in the switching of the direct current power supply and the measuring power supply, and the condition of inaccurate test caused by current shunt exists. Each test branch is connected in parallel through a high-power IGBT (insulated gate bipolar transistor) module, and a driving circuit, cost, size and the like need to be added.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the problem that current shunting causes inaccurate test when a direct current power supply and a measurement power supply in a test circuit are switched is solved.
In order to solve the technical problems, the invention provides the following technical scheme:
a power semiconductor device power cycle test circuit comprises at least one test branch and a grid power supply module, wherein each test branch has the same structure;
each test branch comprises a heating current source, a current bypass module, a diode, a test current source, a diode and a plurality of tested semiconductor devices connected in series;
the output end of the heating current source is connected with the current bypass module, the anode output of the current bypass module is connected with the anode of the diode, and the cathode of the diode is connected with the cathode of the current bypass module after passing through the tested semiconductor device; the grid power supply module is connected with a grid of the tested semiconductor device;
the negative pole of the test current source is connected with one end of the tested semiconductor device, the positive pole of the test current source is connected with the positive pole of the diode, and the negative pole of the diode is connected with the other end of the tested semiconductor device.
The advantages are that: according to the invention, the diode is added in the first test branch, the current shunt is prevented by utilizing the unidirectional conductive characteristic of the diode, the switching between the heating current and the test current can be realized by matching with the current bypass module under the condition of not adding a switch device, and thus the problem of low switching speed caused by the switching on and off of a power device is avoided.
Preferably, the current bypass module comprises a plurality of field effect transistors connected in parallel, one end of each field effect transistor connected in parallel is connected with the output anode of the heating current source, and the other end of each field effect transistor connected in parallel is connected with the output cathode of the heating current source.
Preferably, the semiconductor device under test includes several DUTs connected in series.
Preferably, the semiconductor device testing device further comprises a data acquisition module, wherein the data acquisition module is arranged on a branch circuit where the tested semiconductor device is located.
Preferably, the data acquisition module is provided with a multi-channel high-speed high-precision differential signal acquisition port.
Preferably, the grid power supply module has multiple independent adjustable positive and negative voltages, and is respectively connected with the grids of the tested semiconductor devices.
Preferably, the number of the test branches is three, specifically, the test branches include a first test branch, a second test branch and a third test branch.
Preferably, the first test branch, the second test branch and the third test branch all use independent heating current sources.
A test method of a power cycle test circuit applying power semiconductor devices is characterized in that when each test branch starts a power cycle test, a heating current source outputs preset current to flow through diodes to apply load current to a plurality of tested semiconductor devices, and at the moment, a data acquisition module monitors the conduction voltage of the plurality of tested semiconductor devices and the current value output by the heating current source in real time;
when the preset junction temperature or shell temperature or heating time is reached, the current bypass module is started, the current output by the heating current source flows through the current bypass module, the current flowing through the tested object is rapidly closed, the junction temperature and the shell temperature of the tested object are reduced within the time when the current of the tested object is closed, and the data acquisition module monitors the conducting voltage of the tested object during the heating current turn-off period in real time to obtain the junction temperature and the thermal resistance.
Preferably, during the test, a plurality of semiconductor devices under test can be tested in single or multiple series, the gate power module turns on the corresponding selected semiconductor device under test to output the preset driving voltage to the semiconductor device under test, and the gate of the semiconductor device under test is continuously powered to maintain the continuous forward conduction state.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, the anti-reverse diode is added in the main loop, the shunting is prevented by utilizing the unidirectional conductive characteristic of the diode, and the switching between the heating current and the test current can be realized by matching with the auxiliary test module under the condition of not increasing a switch device, so that the problem of low switching rate caused by the switching on and off of a power device is avoided.
(2) According to the invention, a plurality of field effect transistors connected in parallel are adopted to replace an IGBT module as an auxiliary test circuit, so that the test targets of high precision, high speed and high reliability are achieved, and the loss, the structure size and the cost are reduced.
(3) The invention adopts a multi-branch test structure, can expand the test capacity and improve the test efficiency and the test flexibility.
Drawings
FIG. 1 is a schematic diagram of a main circuit of an embodiment of the present invention;
FIG. 2 is a circuit diagram of a first test branch according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a single test branch test according to an embodiment of the present invention.
Detailed Description
In order to facilitate the understanding of the technical solutions of the present invention for those skilled in the art, the technical solutions of the present invention will be further described with reference to the drawings attached to the specification.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, the present embodiment discloses a power cycle test circuit for a power semiconductor device, which includes three test branches, namely a first test branch 1, a second test branch 2, and a third test branch 3; the first testing branch 1, the second testing branch 2 and the third testing branch 3 all adopt the same circuit structure, so this embodiment mainly describes the first testing branch 1 in detail.
The first test branch 1 includes a heating current source P1, a current bypass module U1, a diode D1, a test current source P4, a diode D4, and a semiconductor device under test. The semiconductor devices under test of the first test branch 1 are embodied as four serially connected DUTs 1 (test equipment, semiconductor devices in this embodiment), DUT2, DUT3, DUT4,
the output end of the heating current source P1 is connected with the current bypass module U1, the positive electrode output of the current bypass module U1 is connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected with the negative electrode of the current bypass module U1 after passing through the tested semiconductor device. Thus, the heating current source P1 can output current through diode D1, then through DUT1, DUT2, DUT3, and DUT4 in sequence, and back to the heating current source P1.
The current bypass module U1 comprises a plurality of field effect transistors Q1, … and field effect transistors Qn (n is more than or equal to 2) which are connected in parallel, one end of each of the field effect transistors Q1, … and the field effect transistors Qn which are connected in parallel is connected with the output anode of the heating current source P1, and the other end of each of the field effect transistors Q1, … and the field effect transistors Qn is connected with the output cathode of the heating current source P1; when the current bypass module U1 is turned on, the current from the heating current source P1 will flow back from the current bypass module U1, thereby rapidly turning off the current to the semiconductor device under test.
In the embodiment, a plurality of field effect transistors Q1 and … and a field effect transistor Qn which are connected in parallel are adopted to replace an IGBT module in the prior art as an auxiliary test circuit, so that the test targets of high precision, high speed and high reliability can be achieved, and the loss, the structure size and the cost are reduced.
Meanwhile, compared with the mode that a plurality of field effect transistors are connected in parallel, the IGBT module used as auxiliary test current has the advantages of low conduction loss and high switching speed.
The cathode of the test current source P4 is connected with one end of the tested semiconductor device, the anode is connected with the anode of the diode D4, and the cathode of the diode D4 is connected with the other end of the tested semiconductor device; test current source P4 is therefore able to output a constant small current through diode D4, then through DUT1, DUT2, DUT3 and DUT4 in sequence and back to test current source P4.
The gate power supply module U4 is connected to the gate of the semiconductor device under test, and the gate power supply module U4 has 12 independent adjustable positive and negative voltages and can respectively control the on and off of 12 semiconductor devices under test, so that the gate power supply module U4 outputs four independent gate voltages for controlling the on and off of DUT1, DUT2, DUT3 and DUT 4.
The data acquisition module U5 has a multi-channel high-speed high-precision differential signal acquisition port, and monitors the conduction voltages of the DUT1, the DUT2, the DUT3 and the DUT4 and the current value output by the heating current source P1 in real time.
In the test process, the DUT1, the DUT2, the DUT3 and the DUT4 can be flexibly selected and can be tested singly or in series, the gate power supply module U4 turns on the corresponding correspondingly selected tested piece to output a preset driving voltage to the tested piece, and the gate of the tested piece is continuously powered to keep a continuous forward conduction state. And then applying a load current to the tested piece, wherein the magnitude of the load current is determined according to the application condition of the tested piece. The on and off times (cycle period) should be controlled by monitoring the case temperature Tc, constant junction temperature variation (case temperature is approximately unchanged), fixed time setting, and the test sequence is shown in fig. 3.
When the first test branch 1 starts the power cycle test, the heating current source P1 outputs a preset current to flow through the diode D1 to apply a load current to the DUT1, the DUT2, the DUT3 and the DUT4, and the data acquisition module U5 monitors the turn-on voltages of the DUT1, the DUT2, the DUT3 and the DUT4 and the current value output by the heating current source P1 in real time.
When the preset junction temperature or shell temperature or heating time is reached, the current bypass module U1 is started, the current output by the heating current source P1 flows through the current bypass module U1, the current flowing through the measured object is rapidly closed, the junction temperature and the shell temperature of the measured object are reduced in the current closing time of the measured object, and the data acquisition module U5 monitors the conducting voltage of the measured object in the heating current closing period in real time to obtain the junction temperature and the thermal resistance.
In the process, the diode D1 arranged in the first testing branch 1 utilizes the unidirectional conduction characteristic of the diode, and can be matched with the current bypass module U1 to realize the switching between the heating current and the testing current without increasing a switching device, so that the problem of insufficient switching speed caused by the switching on and off of a power device is avoided.
That is, when the current bypass module U1 is started, the heating current of the semiconductor device under test is turned off by using the characteristic that the voltage of the current bypass module U1 is lower than the forward turn-on voltage of the diode D1 and is turned off, and the test current source P4 is output to the object under test through the diode D4, so that the heating current and the test current are switched.
In the same way, in the second test branch 2, the heating current source P2 applies load currents to the four semiconductor devices DUT5, DUT6, DUT7 and DUT8 via the current bypass module U2 and the diode D2, and the test current source P5 is connected to the four semiconductor devices via the diode D5; four independent gate voltages of the gate power supply module U4 control the on and off of the four semiconductor devices; the data acquisition module U5 monitors the current of the second test branch 2 and the conduction voltage drops of the four semiconductor devices.
In the third test branch 3, the heating current source P3 applies load currents to the four semiconductor devices DUT9, DUT10, DUT11 and DUT12 via the current bypass module U3 and the diode D3, to which the test current source P6 is connected via the diode D6; four independent gate voltages of the gate power supply module U4 control the on and off of the four semiconductor devices; the data acquisition module U5 monitors the current in the third test branch 3 and the conduction voltage drops of the four semiconductor devices.
Because each test circuit is provided with a heating current source, the three test branches of the embodiment work independently, and power cycle test can be simultaneously carried out on the power semiconductor devices with the maximum 12 packaging specifications. The test efficiency and the test flexibility are improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.
The above-mentioned embodiments only represent embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the concept of the present invention, and these embodiments are all within the protection scope of the present invention.
Claims (10)
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Cited By (3)
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| CN115015728A (en) * | 2022-06-30 | 2022-09-06 | 科威尔技术股份有限公司 | SIC MOSFET junction temperature acquisition circuit and method |
| CN117607649A (en) * | 2023-11-23 | 2024-02-27 | 深圳豪成智能科技有限公司 | MOS tube testing circuit, system and method |
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| CN115015728A (en) * | 2022-06-30 | 2022-09-06 | 科威尔技术股份有限公司 | SIC MOSFET junction temperature acquisition circuit and method |
| CN117607649A (en) * | 2023-11-23 | 2024-02-27 | 深圳豪成智能科技有限公司 | MOS tube testing circuit, system and method |
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